ACPI: Separate device_nvs_t
Remove typedef device_nvs_t and move struct device_nvs
outside of global_nvs. Also remove padding and the reserve
for chromeos_acpi_t.
Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index bd9f78e..33923d0 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -8,6 +8,7 @@
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select ACPI_HAS_DEVICE_NVS
select ARCH_ALL_STAGES_X86_32
select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
select BOOT_DEVICE_SUPPORTS_WRITES
diff --git a/src/soc/intel/baytrail/acpi/device_nvs.asl b/src/soc/intel/baytrail/acpi/device_nvs.asl
index 3722856..aa0e953 100644
--- a/src/soc/intel/baytrail/acpi/device_nvs.asl
+++ b/src/soc/intel/baytrail/acpi/device_nvs.asl
@@ -1,68 +1,74 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* Device Enabled in ACPI Mode */
+External (NVSD)
-S0EN, 8, /* SDMA Enable */
-S1EN, 8, /* I2C1 Enable */
-S2EN, 8, /* I2C2 Enable */
-S3EN, 8, /* I2C3 Enable */
-S4EN, 8, /* I2C4 Enable */
-S5EN, 8, /* I2C5 Enable */
-S6EN, 8, /* I2C6 Enable */
-S7EN, 8, /* I2C7 Enable */
-S8EN, 8, /* SDMA2 Enable */
-S9EN, 8, /* SPI Enable */
-SAEN, 8, /* PWM1 Enable */
-SBEN, 8, /* PWM2 Enable */
-SCEN, 8, /* UART2 Enable */
-SDEN, 8, /* UART2 Enable */
-C0EN, 8, /* MMC Enable */
-C1EN, 8, /* SDIO Enable */
-C2EN, 8, /* SD Card Enable */
-LPEN, 8, /* LPE Enable */
+OperationRegion (DNVS, SystemMemory, NVSD, 0x1000)
+Field (DNVS, ByteAcc, NoLock, Preserve)
+{
+ /* Device Enabled in ACPI Mode */
-/* BAR 0 */
+ S0EN, 8, /* SDMA Enable */
+ S1EN, 8, /* I2C1 Enable */
+ S2EN, 8, /* I2C2 Enable */
+ S3EN, 8, /* I2C3 Enable */
+ S4EN, 8, /* I2C4 Enable */
+ S5EN, 8, /* I2C5 Enable */
+ S6EN, 8, /* I2C6 Enable */
+ S7EN, 8, /* I2C7 Enable */
+ S8EN, 8, /* SDMA2 Enable */
+ S9EN, 8, /* SPI Enable */
+ SAEN, 8, /* PWM1 Enable */
+ SBEN, 8, /* PWM2 Enable */
+ SCEN, 8, /* UART2 Enable */
+ SDEN, 8, /* UART2 Enable */
+ C0EN, 8, /* MMC Enable */
+ C1EN, 8, /* SDIO Enable */
+ C2EN, 8, /* SD Card Enable */
+ LPEN, 8, /* LPE Enable */
-S0B0, 32, /* SDMA BAR0 */
-S1B0, 32, /* I2C1 BAR0 */
-S2B0, 32, /* I2C2 BAR0 */
-S3B0, 32, /* I2C3 BAR0 */
-S4B0, 32, /* I2C4 BAR0 */
-S5B0, 32, /* I2C5 BAR0 */
-S6B0, 32, /* I2C6 BAR0 */
-S7B0, 32, /* I2C7 BAR0 */
-S8B0, 32, /* SDMA2 BAR0 */
-S9B0, 32, /* SPI BAR0 */
-SAB0, 32, /* PWM1 BAR0 */
-SBB0, 32, /* PWM2 BAR0 */
-SCB0, 32, /* UART1 BAR0 */
-SDB0, 32, /* UART2 BAR0 */
-C0B0, 32, /* MMC BAR0 */
-C1B0, 32, /* SDIO BAR0 */
-C2B0, 32, /* SD Card BAR0 */
-LPB0, 32, /* LPE BAR0 */
+ /* BAR 0 */
-/* BAR 1 */
+ S0B0, 32, /* SDMA BAR0 */
+ S1B0, 32, /* I2C1 BAR0 */
+ S2B0, 32, /* I2C2 BAR0 */
+ S3B0, 32, /* I2C3 BAR0 */
+ S4B0, 32, /* I2C4 BAR0 */
+ S5B0, 32, /* I2C5 BAR0 */
+ S6B0, 32, /* I2C6 BAR0 */
+ S7B0, 32, /* I2C7 BAR0 */
+ S8B0, 32, /* SDMA2 BAR0 */
+ S9B0, 32, /* SPI BAR0 */
+ SAB0, 32, /* PWM1 BAR0 */
+ SBB0, 32, /* PWM2 BAR0 */
+ SCB0, 32, /* UART1 BAR0 */
+ SDB0, 32, /* UART2 BAR0 */
+ C0B0, 32, /* MMC BAR0 */
+ C1B0, 32, /* SDIO BAR0 */
+ C2B0, 32, /* SD Card BAR0 */
+ LPB0, 32, /* LPE BAR0 */
-S0B1, 32, /* SDMA BAR1 */
-S1B1, 32, /* I2C1 BAR1 */
-S2B1, 32, /* I2C2 BAR1 */
-S3B1, 32, /* I2C3 BAR1 */
-S4B1, 32, /* I2C4 BAR1 */
-S5B1, 32, /* I2C5 BAR1 */
-S6B1, 32, /* I2C6 BAR1 */
-S7B1, 32, /* I2C7 BAR1 */
-S8B1, 32, /* SDMA2 BAR1 */
-S9B1, 32, /* SPI BAR1 */
-SAB1, 32, /* PWM1 BAR1 */
-SBB1, 32, /* PWM2 BAR1 */
-SCB1, 32, /* UART1 BAR1 */
-SDB1, 32, /* UART2 BAR1 */
-C0B1, 32, /* MMC BAR1 */
-C1B1, 32, /* SDIO BAR1 */
-C2B1, 32, /* SD Card BAR1 */
-LPB1, 32, /* LPE BAR1 */
+ /* BAR 1 */
-/* Extra */
+ S0B1, 32, /* SDMA BAR1 */
+ S1B1, 32, /* I2C1 BAR1 */
+ S2B1, 32, /* I2C2 BAR1 */
+ S3B1, 32, /* I2C3 BAR1 */
+ S4B1, 32, /* I2C4 BAR1 */
+ S5B1, 32, /* I2C5 BAR1 */
+ S6B1, 32, /* I2C6 BAR1 */
+ S7B1, 32, /* I2C7 BAR1 */
+ S8B1, 32, /* SDMA2 BAR1 */
+ S9B1, 32, /* SPI BAR1 */
+ SAB1, 32, /* PWM1 BAR1 */
+ SBB1, 32, /* PWM2 BAR1 */
+ SCB1, 32, /* UART1 BAR1 */
+ SDB1, 32, /* UART2 BAR1 */
+ C0B1, 32, /* MMC BAR1 */
+ C1B1, 32, /* SDIO BAR1 */
+ C2B1, 32, /* SD Card BAR1 */
+ LPB1, 32, /* LPE BAR1 */
-LPFW, 32, /* LPE BAR2 Firmware */
+ /* Extra */
+
+ LPFW, 32, /* LPE BAR2 Firmware */
+}
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index def3fc8..293daa9 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -13,7 +13,7 @@
External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
+OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
@@ -56,9 +56,6 @@
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
-
- Offset (0x1000),
- #include <soc/intel/baytrail/acpi/device_nvs.asl>
}
/* Set flag to enable USB charging in S3 */
diff --git a/src/soc/intel/baytrail/acpi/platform.asl b/src/soc/intel/baytrail/acpi/platform.asl
index 67b515a..1433276 100644
--- a/src/soc/intel/baytrail/acpi/platform.asl
+++ b/src/soc/intel/baytrail/acpi/platform.asl
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <soc/intel/baytrail/acpi/device_nvs.asl>
#include <southbridge/intel/common/acpi/platform.asl>
/*
diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h
index 6a5f108..46fd9cc 100644
--- a/src/soc/intel/baytrail/include/soc/device_nvs.h
+++ b/src/soc/intel/baytrail/include/soc/device_nvs.h
@@ -24,7 +24,7 @@
#define SCC_NVS_SDIO 1
#define SCC_NVS_SD 2
-typedef struct {
+struct __packed device_nvs {
/* Device Enabled in ACPI Mode */
u8 lpss_en[14];
u8 scc_en[3];
@@ -42,7 +42,6 @@
/* Extra */
u32 lpe_fw; /* LPE Firmware */
- u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */
-} __packed device_nvs_t;
+};
#endif
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index 105d304..9fb0822 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -4,7 +4,6 @@
#define _BAYTRAIL_NVS_H_
#include <stdint.h>
-#include <soc/device_nvs.h>
struct __packed global_nvs {
/* Miscellaneous */
@@ -43,15 +42,6 @@
u32 obsolete_cmem; /* 0x30 - CBMEM TOC */
u32 tolm; /* 0x34 - Top of Low Memory */
u32 cbmc; /* 0x38 - coreboot memconsole */
- u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */
-
- u8 unused[76];
-
- /* ChromeOS specific (0x100-0xfff) */
- u8 chromeos_reserve[0xf00];
-
- /* Baytrail LPSS (0x1000) */
- device_nvs_t dev;
};
#endif /* _BAYTRAIL_NVS_H_ */
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index 29633e5..a56ce5b 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -12,7 +12,7 @@
#include <soc/iomap.h>
#include <soc/iosf.h>
#include <soc/lpc.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
#include <soc/pattrs.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
@@ -52,20 +52,15 @@
REG_SCRIPT_END
};
- struct global_nvs *gnvs;
-
- /* Find ACPI NVS to update BARs */
- gnvs = acpi_get_gnvs();
- if (!gnvs)
- return;
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
/* Save BAR0, BAR1, and firmware base to ACPI NVS */
- assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);
- assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1);
- assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);
+ assign_device_nvs(dev, &dev_nvs->lpe_bar0, PCI_BASE_ADDRESS_0);
+ assign_device_nvs(dev, &dev_nvs->lpe_bar1, PCI_BASE_ADDRESS_1);
+ assign_device_nvs(dev, &dev_nvs->lpe_fw, FIRMWARE_PCI_REG_BASE);
/* Device is enabled in ACPI mode */
- gnvs->dev.lpe_en = 1;
+ dev_nvs->lpe_en = 1;
/* Put device in ACPI mode */
reg_script_run_on_dev(dev, ops);
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
index afeb687..9f309b4 100644
--- a/src/soc/intel/baytrail/lpss.c
+++ b/src/soc/intel/baytrail/lpss.c
@@ -10,6 +10,7 @@
#include <soc/iosf.h>
#include <soc/nvs.h>
+#include <soc/device_nvs.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
@@ -28,24 +29,19 @@
REG_SCRIPT_END
};
struct resource *bar;
- struct global_nvs *gnvs;
-
- /* Find ACPI NVS to update BARs */
- gnvs = acpi_get_gnvs();
- if (!gnvs)
- return;
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
/* Save BAR0 and BAR1 to ACPI NVS */
bar = find_resource(dev, PCI_BASE_ADDRESS_0);
if (bar)
- gnvs->dev.lpss_bar0[nvs_index] = (u32)bar->base;
+ dev_nvs->lpss_bar0[nvs_index] = (u32)bar->base;
bar = find_resource(dev, PCI_BASE_ADDRESS_1);
if (bar)
- gnvs->dev.lpss_bar1[nvs_index] = (u32)bar->base;
+ dev_nvs->lpss_bar1[nvs_index] = (u32)bar->base;
/* Device is enabled in ACPI mode */
- gnvs->dev.lpss_en[nvs_index] = 1;
+ dev_nvs->lpss_en[nvs_index] = 1;
/* Put device in ACPI mode */
reg_script_run_on_dev(dev, ops);
diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c
index 8e3bd48..a1e8eb7 100644
--- a/src/soc/intel/baytrail/scc.c
+++ b/src/soc/intel/baytrail/scc.c
@@ -7,7 +7,7 @@
#include <reg_script.h>
#include <soc/iosf.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
#include <soc/ramstage.h>
static const struct reg_script scc_start_dll[] = {
@@ -80,24 +80,19 @@
REG_SCRIPT_END
};
struct resource *bar;
- struct global_nvs *gnvs;
-
- /* Find ACPI NVS to update BARs */
- gnvs = acpi_get_gnvs();
- if (!gnvs)
- return;
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
/* Save BAR0 and BAR1 to ACPI NVS */
bar = find_resource(dev, PCI_BASE_ADDRESS_0);
if (bar)
- gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base;
+ dev_nvs->scc_bar0[nvs_index] = (u32)bar->base;
bar = find_resource(dev, PCI_BASE_ADDRESS_1);
if (bar)
- gnvs->dev.scc_bar1[nvs_index] = (u32)bar->base;
+ dev_nvs->scc_bar1[nvs_index] = (u32)bar->base;
/* Device is enabled in ACPI mode */
- gnvs->dev.scc_en[nvs_index] = 1;
+ dev_nvs->scc_en[nvs_index] = 1;
/* Put device in ACPI mode */
reg_script_run_on_dev(dev, ops);
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 41eeeda..e48ddba 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
+#include <acpi/acpi_gnvs.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <console/console.h>
@@ -17,6 +18,9 @@
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/nvs.h>
+#include <soc/device_nvs.h>
+
+#include <vendorcode/google/chromeos/gnvs.h>
int southbridge_io_trap_handler(int smif)
{
@@ -204,6 +208,11 @@
*ret = gsmi_exec(sub_command, param);
}
+void *acpi_get_device_nvs(void)
+{
+ return (u8 *)gnvs + GNVS_DEVICE_NVS_OFFSET;
+}
+
/*
* soc_legacy: A payload (Depthcharge) has indicated that the
* legacy payload (SeaBIOS) is being loaded. Switch devices that are
@@ -212,10 +221,11 @@
*/
static void soc_legacy(void)
{
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
u32 reg32;
/* LPE Device */
- if (gnvs->dev.lpe_en) {
+ if (dev_nvs->lpe_en) {
reg32 = iosf_port58_read(LPE_PCICFGCTR1);
reg32 &=
~(LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN);
@@ -224,7 +234,7 @@
/* SCC Devices */
#define SCC_ACPI_MODE_DISABLE(name_) \
- do { if (gnvs->dev.scc_en[SCC_NVS_ ## name_]) { \
+ do { if (dev_nvs->scc_en[SCC_NVS_ ## name_]) { \
reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \
reg32 &= ~(SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); \
iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \
@@ -236,7 +246,7 @@
/* LPSS Devices */
#define LPSS_ACPI_MODE_DISABLE(name_) \
- do { if (gnvs->dev.lpss_en[LPSS_NVS_ ## name_]) { \
+ do { if (dev_nvs->lpss_en[LPSS_NVS_ ## name_]) { \
reg32 = iosf_lpss_read(LPSS_ ## name_ ## _CTL); \
reg32 &= ~LPSS_CTL_PCI_CFG_DIS | ~LPSS_CTL_ACPI_INT_EN; \
iosf_lpss_write(LPSS_ ## name_ ## _CTL, reg32); \