ramstage: Align stack to 16 bytes

Some SSE instructions could take 128bit memory operands from

AGESA vendorcode was always built with SSE enabled, but until
now stack alignment was not known to cause major issues. Seems
like GCC-6.3 more likely emits instructions that depend on the
16 byte alignment of stack.

Change-Id: Iea3de54f20ff242105bce5a5edbbd76b04c0116c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18823
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 29d3a53..9ad2698 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -110,6 +110,8 @@
 	post_code(POST_PRE_HARDWAREMAIN)	/* post fe */
+	andl	$0xFFFFFFF0, %esp
 	call gdb_hw_init
 	call gdb_stub_breakpoint