| ## |
| ## Only use the option table in a normal image |
| ## |
| default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE |
| |
| ## CONFIG_XIP_ROM_SIZE must be a power of 2. |
| default CONFIG_XIP_ROM_SIZE = 64 * 1024 |
| include /config/nofailovercalculation.lb |
| |
| ## Set all of the defaults for an x86 architecture |
| ## |
| |
| arch i386 end |
| |
| ## |
| ## Build the objects we have code for in this directory. |
| ## |
| |
| driver mainboard.o |
| if CONFIG_HAVE_MP_TABLE object mptable.o end |
| if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end |
| object reset.o |
| |
| ## |
| ## Romcc output |
| ## |
| makerule ./failover.E |
| depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" |
| action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" |
| end |
| |
| makerule ./failover.inc |
| depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" |
| action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" |
| end |
| |
| makerule ./auto.E |
| depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" |
| action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" |
| end |
| |
| makerule ./auto.inc |
| depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" |
| action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" |
| end |
| |
| ## |
| ## Build our 16 bit and 32 bit coreboot entry code |
| ## |
| mainboardinit cpu/x86/16bit/entry16.inc |
| mainboardinit cpu/x86/32bit/entry32.inc |
| ldscript /cpu/x86/16bit/entry16.lds |
| ldscript /cpu/x86/32bit/entry32.lds |
| |
| ## |
| ## Build our reset vector (This is where coreboot is entered) |
| ## |
| if CONFIG_USE_FALLBACK_IMAGE |
| mainboardinit cpu/x86/16bit/reset16.inc |
| ldscript /cpu/x86/16bit/reset16.lds |
| else |
| mainboardinit cpu/x86/32bit/reset32.inc |
| ldscript /cpu/x86/32bit/reset32.lds |
| end |
| |
| ### Should this be in the northbridge code? |
| mainboardinit arch/i386/lib/cpu_reset.inc |
| |
| ## |
| ## Include an id string (For safe flashing) |
| ## |
| mainboardinit arch/i386/lib/id.inc |
| ldscript /arch/i386/lib/id.lds |
| |
| ### |
| ### This is the early phase of coreboot startup |
| ### Things are delicate and we test to see if we should |
| ### failover to another image. |
| ### |
| if CONFIG_USE_FALLBACK_IMAGE |
| ldscript /arch/i386/lib/failover.lds |
| mainboardinit ./failover.inc |
| end |
| |
| ### |
| ### O.k. We aren't just an intermediary anymore! |
| ### |
| |
| ## |
| ## Setup RAM |
| ## |
| mainboardinit cpu/x86/fpu/enable_fpu.inc |
| mainboardinit cpu/x86/mmx/enable_mmx.inc |
| mainboardinit cpu/x86/sse/enable_sse.inc |
| mainboardinit ./auto.inc |
| mainboardinit cpu/x86/sse/disable_sse.inc |
| mainboardinit cpu/x86/mmx/disable_mmx.inc |
| |
| |
| ## |
| ## Include the secondary Configuration files |
| ## |
| dir /pc80 |
| config chip.h |
| |
| chip northbridge/intel/e7520 # MCH |
| chip drivers/generic/debug # DEBUGGING |
| device pnp 00.0 on end |
| device pnp 00.1 off end |
| device pnp 00.2 off end |
| device pnp 00.3 off end |
| end |
| device pci_domain 0 on |
| chip southbridge/intel/esb6300 # ESB6300 |
| register "pirq_a_d" = "0x0b070a05" |
| register "pirq_e_h" = "0x0a808080" |
| |
| device pci 1c.0 on |
| chip drivers/generic/generic |
| device pci 01.0 on end # onboard gige1 |
| device pci 02.0 on end # onboard gige2 |
| end |
| end |
| |
| # USB ports |
| device pci 1d.0 on end |
| device pci 1d.1 on end |
| device pci 1d.4 on end # Southbridge Watchdog timer |
| device pci 1d.5 on end # Southbridge I/O apic1 |
| device pci 1d.7 on end |
| |
| # VGA / PCI 32-bit |
| device pci 1e.0 on |
| chip drivers/generic/generic |
| device pci 01.0 on end |
| end |
| end |
| |
| |
| device pci 1f.0 on # ISA bridge |
| chip superio/winbond/w83627hf |
| device pnp 2e.0 off end |
| device pnp 2e.2 on |
| io 0x60 = 0x3f8 |
| irq 0x70 = 4 |
| end |
| device pnp 2e.3 on |
| io 0x60 = 0x2f8 |
| irq 0x70 = 3 |
| end |
| device pnp 2e.4 off end |
| device pnp 2e.5 off end |
| device pnp 2e.6 off end |
| device pnp 2e.7 off end |
| device pnp 2e.9 off end |
| device pnp 2e.a on end |
| device pnp 2e.b off end |
| end |
| end |
| device pci 1f.1 on end |
| device pci 1f.2 off end |
| device pci 1f.3 on end # SMBus |
| device pci 1f.5 off end |
| device pci 1f.6 off end |
| end |
| |
| device pci 00.0 on end # Northbridge |
| device pci 00.1 on end # Northbridge Error reporting |
| device pci 01.0 on end |
| device pci 02.0 on |
| chip southbridge/intel/pxhd # PXHD 6700 |
| device pci 00.0 on end # bridge |
| device pci 00.1 on end # I/O apic |
| device pci 00.2 on end # bridge |
| device pci 00.3 on end # I/O apic |
| end |
| end |
| # device register "intrline" = "0x00070105" |
| device pci 04.0 on end |
| device pci 06.0 on end |
| end |
| |
| device apic_cluster 0 on |
| chip cpu/intel/socket_mPGA604 # CPU 0 |
| device apic 0 on end |
| end |
| chip cpu/intel/socket_mPGA604 # CPU 1 |
| device apic 6 on end |
| end |
| end |
| end |