| ## CONFIG_XIP_ROM_SIZE must be a power of 2. |
| default CONFIG_XIP_ROM_SIZE = 64 * 1024 |
| include /config/nofailovercalculation.lb |
| |
| ## |
| ## Set all of the defaults for an x86 architecture |
| ## |
| |
| arch i386 end |
| |
| ## |
| ## Build the objects we have code for in this directory. |
| ## |
| |
| driver mainboard.o |
| if CONFIG_HAVE_MP_TABLE object mptable.o end |
| if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end |
| #object reset.o |
| |
| if CONFIG_USE_INIT |
| |
| makerule ./auto.o |
| depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" |
| action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" |
| end |
| |
| else |
| |
| makerule ./auto.inc |
| depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" |
| action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" |
| action "perl -e 's/\.rodata/.rom.data/g' -pi $@" |
| action "perl -e 's/\.text/.section .rom.text/g' -pi $@" |
| end |
| |
| end |
| |
| ## |
| ## Build our 16 bit and 32 bit coreboot entry code |
| ## |
| if CONFIG_USE_FALLBACK_IMAGE |
| mainboardinit cpu/x86/16bit/entry16.inc |
| ldscript /cpu/x86/16bit/entry16.lds |
| end |
| |
| mainboardinit cpu/x86/32bit/entry32.inc |
| |
| if CONFIG_USE_INIT |
| ldscript /cpu/x86/32bit/entry32.lds |
| end |
| |
| if CONFIG_USE_INIT |
| ldscript /cpu/amd/car/cache_as_ram.lds |
| end |
| |
| ## |
| ## Build our reset vector (This is where coreboot is entered) |
| ## |
| if CONFIG_USE_FALLBACK_IMAGE |
| mainboardinit cpu/x86/16bit/reset16.inc |
| ldscript /cpu/x86/16bit/reset16.lds |
| else |
| mainboardinit cpu/x86/32bit/reset32.inc |
| ldscript /cpu/x86/32bit/reset32.lds |
| end |
| |
| ## |
| ## Include an id string (For safe flashing) |
| ## |
| mainboardinit arch/i386/lib/id.inc |
| ldscript /arch/i386/lib/id.lds |
| |
| ## |
| ## Setup Cache-As-Ram |
| ## |
| mainboardinit cpu/amd/car/cache_as_ram.inc |
| |
| ### |
| ### This is the early phase of coreboot startup |
| ### Things are delicate and we test to see if we should |
| ### failover to another image. |
| ### |
| if CONFIG_USE_FALLBACK_IMAGE |
| ldscript /arch/i386/lib/failover.lds |
| end |
| |
| ### |
| ### O.k. We aren't just an intermediary anymore! |
| ### |
| |
| ## |
| ## Setup RAM |
| ## |
| if CONFIG_USE_INIT |
| initobject auto.o |
| else |
| mainboardinit ./auto.inc |
| end |
| |
| config chip.h |
| |
| # FIXME: ROM for onboard VGA |
| |
| chip northbridge/amd/amdk8/root_complex |
| device apic_cluster 0 on |
| chip cpu/amd/socket_940 |
| device apic 0 on end |
| end |
| chip cpu/amd/socket_940 |
| device apic 1 on end |
| end |
| end |
| |
| device pci_domain 0 on |
| chip northbridge/amd/amdk8 |
| device pci 18.0 on end # LDT 0 |
| device pci 18.0 on # LDT 1 |
| chip southbridge/amd/amd8131 |
| device pci 0.0 on end |
| device pci 0.1 on end |
| device pci 1.0 on end |
| device pci 1.1 on end |
| end |
| chip southbridge/amd/amd8111 |
| device pci 0.0 on |
| device pci 0.0 on end |
| device pci 0.1 on end |
| device pci 0.2 on end |
| device pci 1.0 on end |
| end |
| device pci 1.0 on |
| chip superio/winbond/w83627hf |
| device pnp 2e.0 on # Floppy |
| io 0x60 = 0x3f0 |
| irq 0x70 = 6 |
| drq 0x74 = 2 |
| end |
| device pnp 2e.1 off # Parallel Port |
| io 0x60 = 0x378 |
| irq 0x70 = 7 |
| end |
| device pnp 2e.2 on # Com1 |
| io 0x60 = 0x3f8 |
| irq 0x70 = 4 |
| end |
| device pnp 2e.3 on # Com2 |
| io 0x60 = 0x2f8 |
| irq 0x70 = 3 |
| end |
| device pnp 2e.5 on # Keyboard |
| io 0x60 = 0x60 |
| io 0x62 = 0x64 |
| irq 0x70 = 1 |
| irq 0x72 = 12 |
| end |
| device pnp 2e.6 off # CIR |
| io 0x60 = 0x100 |
| end |
| device pnp 2e.7 off # GAME_MIDI_GIPO1 |
| io 0x60 = 0x220 |
| io 0x62 = 0x300 |
| irq 0x70 = 9 |
| end |
| device pnp 2e.8 off end # GPIO2 |
| device pnp 2e.9 off end # GPIO3 |
| device pnp 2e.a off end # ACPI |
| device pnp 2e.b on # HW Monitor |
| io 0x60 = 0x290 |
| irq 0x70 = 5 |
| end |
| end |
| end |
| device pci 1.1 on end |
| device pci 1.2 on end |
| device pci 1.3 on end |
| device pci 1.5 on end |
| device pci 1.6 on end |
| end |
| end # LDT1 |
| device pci 18.0 on end # LDT2 |
| device pci 18.1 on end |
| device pci 18.2 on end |
| device pci 18.3 on end |
| end |
| chip northbridge/amd/amdk8 |
| device pci 19.0 on end |
| device pci 19.0 on end |
| device pci 19.0 on end |
| device pci 19.1 on end |
| device pci 19.2 on end |
| device pci 19.3 on end |
| end |
| end |
| end |
| |