src/mainboard/kontron/986lcd-m/Options.lb - coreboot - Gitiles

 ##
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2007-2008 coresystems GmbH
 ##
 ## This program is free software; you can redistribute it and/or
 ## modify it under the terms of the GNU General Public License as
 ## published by the Free Software Foundation; version 2 of
 ## the License.
 ##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 ## MA 02110-1301 USA
 ##

 # Tables
 uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_HAVE_PIRQ_TABLE
 uses CONFIG_IRQ_SLOT_COUNT
 uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_USE_OPTION_TABLE
 uses CONFIG_LB_CKS_RANGE_START
 uses CONFIG_LB_CKS_RANGE_END
 uses CONFIG_LB_CKS_LOC
 uses CONFIG_HAVE_ACPI_TABLES
 uses CONFIG_HAVE_ACPI_RESUME
 uses CONFIG_HAVE_MAINBOARD_RESOURCES
 # SMP
 uses CONFIG_SMP
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_AP_IN_SIPI_WAIT
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_IOAPIC
 # Image Size
 uses CONFIG_USE_FALLBACK_IMAGE
 uses CONFIG_HAVE_FALLBACK_BOOT
 uses CONFIG_FALLBACK_SIZE
 uses CONFIG_ROM_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_IMAGE_SIZE
 uses CONFIG_ROM_SECTION_SIZE
 uses CONFIG_ROM_SECTION_OFFSET
 # Payload
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
 # Build Internals
 uses CONFIG_RAMBASE
 uses CONFIG_ROMBASE
 uses CONFIG_STACK_SIZE
 uses CONFIG_HEAP_SIZE
 uses CONFIG_USE_DCACHE_RAM
 uses CONFIG_DCACHE_RAM_BASE
 uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
 uses CONFIG_XIP_ROM_BASE
 uses CONFIG_XIP_ROM_SIZE
 uses CONFIG_HAVE_HARD_RESET
 uses CONFIG_HAVE_SMI_HANDLER
 uses CONFIG_PCIE_CONFIGSPACE_HOLE
 uses CONFIG_MMCONF_SUPPORT
 uses CONFIG_MMCONF_BASE_ADDRESS
 uses CONFIG_GFXUMA

 #
 uses CONFIG_MAINBOARD
 uses CONFIG_MAINBOARD_PART_NUMBER
 uses CONFIG_MAINBOARD_VENDOR
 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 # Timers
 uses CONFIG_UDELAY_LAPIC
 # Console
 uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_TTYS0_BAUD
 uses CONFIG_TTYS0_BASE
 uses CONFIG_TTYS0_LCS
 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_VGA_ROM_RUN
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_DEBUG
 # Toolchain
 uses CC
 uses HOSTCC
 uses CONFIG_CROSS_COMPILE
 uses CONFIG_OBJCOPY
 # Tweaks
 uses CONFIG_GDB_STUB
 uses CONFIG_MAX_REBOOT_CNT
 uses CONFIG_USE_WATCHDOG_ON_BOOT
 uses COREBOOT_EXTRA_VERSION
 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL

 ###
 ### Build options
 ###

 ##
 ##
 default CONFIG_MAX_REBOOT_CNT=3

 ##
 ## Use the watchdog to break out of a lockup condition
 ##
 default CONFIG_USE_WATCHDOG_ON_BOOT=0

 ##
 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
 default CONFIG_ROM_SIZE=1024*1024


 ##
 ## Build code for the fallback boot
 ##
 default CONFIG_HAVE_FALLBACK_BOOT=1

 ##
 ## Delay timer options
 ##
 default CONFIG_UDELAY_LAPIC=1

 ##
 ## Build code to reset the motherboard from coreboot
 ##
 default CONFIG_HAVE_HARD_RESET=1

 ##
 ## Build SMI handler
 ##
 default CONFIG_HAVE_SMI_HANDLER=1

 ##
 ## Leave a hole for mmapped PCIe config space
 ##

 default CONFIG_PCIE_CONFIGSPACE_HOLE=1
 default CONFIG_MMCONF_SUPPORT=1
 default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000

 ##
 ## UMA
 ##
 default CONFIG_GFXUMA=1

 ##
 ## Build code to export a programmable irq routing table
 ##
 default CONFIG_HAVE_PIRQ_TABLE=1
 default CONFIG_IRQ_SLOT_COUNT=18

 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
 default CONFIG_HAVE_MP_TABLE=1

 ##
 ## Build code to provide ACPI support
 ##
 default CONFIG_HAVE_ACPI_TABLES=1
 default CONFIG_HAVE_MAINBOARD_RESOURCES=1
 default CONFIG_HAVE_ACPI_RESUME=1

 ##
 ## Build code to export a CMOS option table
 ##
 default CONFIG_HAVE_OPTION_TABLE=1

 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default CONFIG_LB_CKS_RANGE_START=49
 default CONFIG_LB_CKS_RANGE_END=122
 default CONFIG_LB_CKS_LOC=123

 #VGA Console
 default CONFIG_CONSOLE_VGA=1
 # There are some network option roms that don't work with
 # coreboot's x86emu. Thus, we only execute the VGA option rom
 # for now:
 default CONFIG_VGA_ROM_RUN=1
 default CONFIG_PCI_ROM_RUN=0
 default CONFIG_DEBUG=0

 ##
 ## Build code for SMP support
 ## Only worry about 2 micro processors
 ##
 default CONFIG_SMP=1
 default CONFIG_MAX_CPUS=4
 default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 default CONFIG_AP_IN_SIPI_WAIT=1

 ##
 ## enable CACHE_AS_RAM specifics
 ##
 default CONFIG_USE_DCACHE_RAM=1
 default CONFIG_DCACHE_RAM_SIZE=0x8000
 default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024)
 default CONFIG_USE_PRINTK_IN_CAR=1

 ##
 ## Execute In Place settings
 ##

 default CONFIG_XIP_ROM_SIZE = 128 * 1024
 default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE )

 ##
 ## Build code to setup a generic IOAPIC
 ##
 default CONFIG_IOAPIC=1

 ##
 ## Clean up the motherboard id strings
 ##
 default CONFIG_MAINBOARD_PART_NUMBER="986LCD-M"
 default CONFIG_MAINBOARD_VENDOR=     "KONTRON"

 ###
 ### coreboot layout values
 ###

 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default CONFIG_ROM_IMAGE_SIZE = 0x10000

 ##
 ## Use a small 32K stack
 ##
 default CONFIG_STACK_SIZE=0x8000

 ##
 ## Use a small 32K heap
 ##
 default CONFIG_HEAP_SIZE=0x8000


 ###
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
 default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE

 ##
 ## coreboot C code runs at this location in RAM
 ##
 default CONFIG_RAMBASE=0x00100000

 ##
 ## Load the payload from the ROM
 ##
 default CONFIG_ROM_PAYLOAD=1

 ###
 ### Defaults of options that you may want to override in the target config file
 ###

 ##
 ## The default compiler
 ##
 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"

 ##
 ## Disable the gdb stub by default
 ##
 default CONFIG_GDB_STUB=0

 ##
 ## The Serial Console
 ##

 # To Enable the Serial Console
 default CONFIG_CONSOLE_SERIAL8250=1

 ## Select the serial console baud rate
 default CONFIG_TTYS0_BAUD=115200
 #default CONFIG_TTYS0_BAUD=57600
 #default CONFIG_TTYS0_BAUD=38400
 #default CONFIG_TTYS0_BAUD=19200
 #default CONFIG_TTYS0_BAUD=9600
 #default CONFIG_TTYS0_BAUD=4800
 #default CONFIG_TTYS0_BAUD=2400
 #default CONFIG_TTYS0_BAUD=1200

 # Select the serial console base port
 default CONFIG_TTYS0_BASE=0x3f8

 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
 default CONFIG_TTYS0_LCS=0x3

 ##
 ### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable
 ## ALERT      2   action must be taken immediately
 ## CRIT       3   critical conditions
 ## ERR        4   error conditions
 ## WARNING    5   warning conditions
 ## NOTICE     6   normal but significant condition
 ## INFO       7   informational
 ## CONFIG_DEBUG      8   debug-level messages
 ## SPEW       9   Way too many details

 ## Request this level of debugging output
 default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
 ## At a maximum only compile in this level of debugging
 default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9

 ##
 ## Select power on after power fail setting
 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"

 ### End Options.lb
 end
	##
	## This file is part of the coreboot project.
	##
	## Copyright (C) 2007-2008 coresystems GmbH
	##
	## This program is free software; you can redistribute it and/or
	## modify it under the terms of the GNU General Public License as
	## published by the Free Software Foundation; version 2 of
	## the License.
	##
	## This program is distributed in the hope that it will be useful,
	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	## GNU General Public License for more details.
	##
	## You should have received a copy of the GNU General Public License
	## along with this program; if not, write to the Free Software
	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
	## MA 02110-1301 USA
	##

	# Tables
	uses CONFIG_HAVE_MP_TABLE
	uses CONFIG_HAVE_PIRQ_TABLE
	uses CONFIG_IRQ_SLOT_COUNT
	uses CONFIG_HAVE_OPTION_TABLE
	uses CONFIG_USE_OPTION_TABLE
	uses CONFIG_LB_CKS_RANGE_START
	uses CONFIG_LB_CKS_RANGE_END
	uses CONFIG_LB_CKS_LOC
	uses CONFIG_HAVE_ACPI_TABLES
	uses CONFIG_HAVE_ACPI_RESUME
	uses CONFIG_HAVE_MAINBOARD_RESOURCES
	# SMP
	uses CONFIG_SMP
	uses CONFIG_LOGICAL_CPUS
	uses CONFIG_AP_IN_SIPI_WAIT
	uses CONFIG_MAX_CPUS
	uses CONFIG_MAX_PHYSICAL_CPUS
	uses CONFIG_IOAPIC
	# Image Size
	uses CONFIG_USE_FALLBACK_IMAGE
	uses CONFIG_HAVE_FALLBACK_BOOT
	uses CONFIG_FALLBACK_SIZE
	uses CONFIG_ROM_SIZE
	uses CONFIG_ROM_SECTION_SIZE
	uses CONFIG_ROM_IMAGE_SIZE
	uses CONFIG_ROM_SECTION_SIZE
	uses CONFIG_ROM_SECTION_OFFSET
	# Payload
	uses CONFIG_ROM_PAYLOAD
	uses CONFIG_COMPRESSED_PAYLOAD_LZMA
	uses CONFIG_PRECOMPRESSED_PAYLOAD
	# Build Internals
	uses CONFIG_RAMBASE
	uses CONFIG_ROMBASE
	uses CONFIG_STACK_SIZE
	uses CONFIG_HEAP_SIZE
	uses CONFIG_USE_DCACHE_RAM
	uses CONFIG_DCACHE_RAM_BASE
	uses CONFIG_DCACHE_RAM_SIZE
	uses CONFIG_USE_INIT
	uses CONFIG_USE_PRINTK_IN_CAR
	uses CONFIG_XIP_ROM_BASE
	uses CONFIG_XIP_ROM_SIZE
	uses CONFIG_HAVE_HARD_RESET
	uses CONFIG_HAVE_SMI_HANDLER
	uses CONFIG_PCIE_CONFIGSPACE_HOLE
	uses CONFIG_MMCONF_SUPPORT
	uses CONFIG_MMCONF_BASE_ADDRESS
	uses CONFIG_GFXUMA

	#
	uses CONFIG_MAINBOARD
	uses CONFIG_MAINBOARD_PART_NUMBER
	uses CONFIG_MAINBOARD_VENDOR
	uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
	uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
	# Timers
	uses CONFIG_UDELAY_LAPIC
	# Console
	uses CONFIG_CONSOLE_SERIAL8250
	uses CONFIG_TTYS0_BAUD
	uses CONFIG_TTYS0_BASE
	uses CONFIG_TTYS0_LCS
	uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
	uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
	uses CONFIG_CONSOLE_VGA
	uses CONFIG_VGA_ROM_RUN
	uses CONFIG_PCI_ROM_RUN
	uses CONFIG_DEBUG
	# Toolchain
	uses CC
	uses HOSTCC
	uses CONFIG_CROSS_COMPILE
	uses CONFIG_OBJCOPY
	# Tweaks
	uses CONFIG_GDB_STUB
	uses CONFIG_MAX_REBOOT_CNT
	uses CONFIG_USE_WATCHDOG_ON_BOOT
	uses COREBOOT_EXTRA_VERSION
	uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL

	###
	### Build options
	###

	##
	##
	default CONFIG_MAX_REBOOT_CNT=3

	##
	## Use the watchdog to break out of a lockup condition
	##
	default CONFIG_USE_WATCHDOG_ON_BOOT=0

	##
	## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
	##
	default CONFIG_ROM_SIZE=1024*1024


	##
	## Build code for the fallback boot
	##
	default CONFIG_HAVE_FALLBACK_BOOT=1

	##
	## Delay timer options
	##
	default CONFIG_UDELAY_LAPIC=1

	##
	## Build code to reset the motherboard from coreboot
	##
	default CONFIG_HAVE_HARD_RESET=1

	##
	## Build SMI handler
	##
	default CONFIG_HAVE_SMI_HANDLER=1

	##
	## Leave a hole for mmapped PCIe config space
	##

	default CONFIG_PCIE_CONFIGSPACE_HOLE=1
	default CONFIG_MMCONF_SUPPORT=1
	default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000

	##
	## UMA
	##
	default CONFIG_GFXUMA=1

	##
	## Build code to export a programmable irq routing table
	##
	default CONFIG_HAVE_PIRQ_TABLE=1
	default CONFIG_IRQ_SLOT_COUNT=18

	##
	## Build code to export an x86 MP table
	## Useful for specifying IRQ routing values
	##
	default CONFIG_HAVE_MP_TABLE=1

	##
	## Build code to provide ACPI support
	##
	default CONFIG_HAVE_ACPI_TABLES=1
	default CONFIG_HAVE_MAINBOARD_RESOURCES=1
	default CONFIG_HAVE_ACPI_RESUME=1

	##
	## Build code to export a CMOS option table
	##
	default CONFIG_HAVE_OPTION_TABLE=1

	##
	## Move the default coreboot cmos range off of AMD RTC registers
	##
	default CONFIG_LB_CKS_RANGE_START=49
	default CONFIG_LB_CKS_RANGE_END=122
	default CONFIG_LB_CKS_LOC=123

	#VGA Console
	default CONFIG_CONSOLE_VGA=1
	# There are some network option roms that don't work with
	# coreboot's x86emu. Thus, we only execute the VGA option rom
	# for now:
	default CONFIG_VGA_ROM_RUN=1
	default CONFIG_PCI_ROM_RUN=0
	default CONFIG_DEBUG=0

	##
	## Build code for SMP support
	## Only worry about 2 micro processors
	##
	default CONFIG_SMP=1
	default CONFIG_MAX_CPUS=4
	default CONFIG_MAX_PHYSICAL_CPUS=2
	default CONFIG_LOGICAL_CPUS=1
	default CONFIG_AP_IN_SIPI_WAIT=1

	##
	## enable CACHE_AS_RAM specifics
	##
	default CONFIG_USE_DCACHE_RAM=1
	default CONFIG_DCACHE_RAM_SIZE=0x8000
	default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024)
	default CONFIG_USE_PRINTK_IN_CAR=1

	##
	## Execute In Place settings
	##

	default CONFIG_XIP_ROM_SIZE = 128 * 1024
	default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE )

	##
	## Build code to setup a generic IOAPIC
	##
	default CONFIG_IOAPIC=1

	##
	## Clean up the motherboard id strings
	##
	default CONFIG_MAINBOARD_PART_NUMBER="986LCD-M"
	default CONFIG_MAINBOARD_VENDOR= "KONTRON"

	###
	### coreboot layout values
	###

	## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
	default CONFIG_ROM_IMAGE_SIZE = 0x10000

	##
	## Use a small 32K stack
	##
	default CONFIG_STACK_SIZE=0x8000

	##
	## Use a small 32K heap
	##
	default CONFIG_HEAP_SIZE=0x8000


	###
	### Compute the location and size of where this firmware image
	### (coreboot plus bootloader) will live in the boot rom chip.
	###
	default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE

	##
	## coreboot C code runs at this location in RAM
	##
	default CONFIG_RAMBASE=0x00100000

	##
	## Load the payload from the ROM
	##
	default CONFIG_ROM_PAYLOAD=1

	###
	### Defaults of options that you may want to override in the target config file
	###

	##
	## The default compiler
	##
	default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
	default HOSTCC="gcc"

	##
	## Disable the gdb stub by default
	##
	default CONFIG_GDB_STUB=0

	##
	## The Serial Console
	##

	# To Enable the Serial Console
	default CONFIG_CONSOLE_SERIAL8250=1

	## Select the serial console baud rate
	default CONFIG_TTYS0_BAUD=115200
	#default CONFIG_TTYS0_BAUD=57600
	#default CONFIG_TTYS0_BAUD=38400
	#default CONFIG_TTYS0_BAUD=19200
	#default CONFIG_TTYS0_BAUD=9600
	#default CONFIG_TTYS0_BAUD=4800
	#default CONFIG_TTYS0_BAUD=2400
	#default CONFIG_TTYS0_BAUD=1200

	# Select the serial console base port
	default CONFIG_TTYS0_BASE=0x3f8

	# Select the serial protocol
	# This defaults to 8 data bits, 1 stop bit, and no parity
	default CONFIG_TTYS0_LCS=0x3

	##
	### Select the coreboot loglevel
	##
	## EMERG 1 system is unusable
	## ALERT 2 action must be taken immediately
	## CRIT 3 critical conditions
	## ERR 4 error conditions
	## WARNING 5 warning conditions
	## NOTICE 6 normal but significant condition
	## INFO 7 informational
	## CONFIG_DEBUG 8 debug-level messages
	## SPEW 9 Way too many details

	## Request this level of debugging output
	default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
	## At a maximum only compile in this level of debugging
	default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9

	##
	## Select power on after power fail setting
	default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"

	### End Options.lb
	end