Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
44e4a4e4db23677c960591d3209004f4f8b80326
/
.
/
src
/
southbridge
/
amd
/
sr5650
/
Makefile.inc
blob: f695a112a659db48da8513a10f25354939b6fbc6 [
file
] [
log
] [
blame
]
ifeq
(
$
(
CONFIG_SOUTHBRIDGE_AMD_SR5650
),
y
)
ramstage
-
y
+=
sr5650
.
c
ramstage
-
y
+=
pcie
.
c
ramstage
-
y
+=
ht
.
c
romstage
-
y
+=
early_setup
.
c
endif