| config SOC_INTEL_BROADWELL |
| bool |
| help |
| Intel Broadwell and Haswell ULT support. |
| |
| if SOC_INTEL_BROADWELL |
| |
| config INTEL_LYNXPOINT_LP |
| bool |
| default y if SOC_INTEL_BROADWELL |
| |
| config CPU_SPECIFIC_OPTIONS |
| def_bool y |
| select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
| select ARCH_ALL_STAGES_X86_32 |
| select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES |
| select BOOT_DEVICE_SUPPORTS_WRITES |
| select CACHE_MRC_SETTINGS |
| select MRC_SETTINGS_PROTECT |
| select CPU_INTEL_COMMON |
| select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| select SUPPORT_CPU_UCODE_IN_CBFS |
| select HAVE_SMI_HANDLER |
| select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS |
| select SOUTHBRIDGE_INTEL_COMMON_RESET |
| select SOUTHBRIDGE_INTEL_COMMON_RTC |
| select SOUTHBRIDGE_INTEL_COMMON_SMBUS |
| select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 |
| select HAVE_USBDEBUG |
| select IOAPIC |
| select REG_SCRIPT |
| select PARALLEL_MP |
| select RTC |
| select SPI_FLASH |
| select SSE2 |
| select TSC_SYNC_MFENCE |
| select UDELAY_TSC |
| select TSC_MONOTONIC_TIMER |
| select SOC_INTEL_COMMON |
| select INTEL_DESCRIPTOR_MODE_CAPABLE |
| select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT |
| select INTEL_GMA_ACPI |
| select HAVE_POWER_STATE_AFTER_FAILURE |
| select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE |
| |
| config MAX_CPUS |
| int |
| default 8 |
| |
| config PCIEXP_ASPM |
| bool |
| default y |
| |
| config PCIEXP_AER |
| bool |
| default y |
| |
| config PCIEXP_COMMON_CLOCK |
| bool |
| default y |
| |
| config PCIEXP_CLK_PM |
| bool |
| default y |
| |
| config PCIEXP_L1_SUB_STATE |
| bool |
| default y |
| |
| config BROADWELL_VBOOT_IN_BOOTBLOCK |
| depends on VBOOT |
| bool "Start verstage in bootblock" |
| default y |
| select VBOOT_STARTS_IN_BOOTBLOCK |
| select VBOOT_SEPARATE_VERSTAGE |
| help |
| Broadwell can either start verstage in a separate stage |
| right after the bootblock has run or it can start it |
| after romstage for compatibility reasons. |
| Broadwell however uses a mrc.bin to initialse memory which |
| needs to be located at a fixed offset. Therefore even with |
| a separate verstage starting after the bootblock that same |
| binary is used meaning a jump is made from RW to the RO region |
| and back to the RW region after the binary is done. |
| |
| config VBOOT |
| select VBOOT_MUST_REQUEST_DISPLAY |
| select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK |
| |
| config MMCONF_BASE_ADDRESS |
| hex |
| default 0xf0000000 |
| |
| config SMM_TSEG_SIZE |
| hex |
| default 0x800000 |
| |
| config IED_REGION_SIZE |
| hex |
| default 0x400000 |
| |
| config SMM_RESERVED_SIZE |
| hex |
| default 0x100000 |
| |
| config VGA_BIOS_ID |
| string |
| default "8086,0406" |
| |
| config DCACHE_RAM_BASE |
| hex |
| default 0xff7c0000 |
| |
| config DCACHE_RAM_SIZE |
| hex |
| default 0x10000 |
| help |
| The size of the cache-as-ram region required during bootblock |
| and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| must add up to a power of 2. |
| |
| config DCACHE_RAM_MRC_VAR_SIZE |
| hex |
| default 0x30000 |
| help |
| The amount of cache-as-ram region required by the reference code. |
| |
| config DCACHE_BSP_STACK_SIZE |
| hex |
| default 0x2000 |
| help |
| The amount of anticipated stack usage in CAR by bootblock and |
| other stages. |
| |
| config HAVE_MRC |
| bool "Add a Memory Reference Code binary" |
| help |
| Select this option to add a Memory Reference Code binary to |
| the resulting coreboot image. |
| |
| Note: Without this binary coreboot will not work |
| |
| if HAVE_MRC |
| |
| config MRC_FILE |
| string "Intel Memory Reference Code path and filename" |
| depends on HAVE_MRC |
| default "mrc.bin" |
| help |
| The filename of the file to use as Memory Reference Code binary. |
| |
| config MRC_BIN_ADDRESS |
| hex |
| default 0xfffa0000 |
| |
| # The UEFI System Agent binary needs to be at a fixed offset in the flash |
| # and can therefore only reside in the COREBOOT fmap region |
| config RO_REGION_ONLY |
| string |
| depends on VBOOT |
| default "mrc.bin" |
| |
| endif # HAVE_MRC |
| |
| config PRE_GRAPHICS_DELAY |
| int "Graphics initialization delay in ms" |
| default 0 |
| help |
| On some systems, coreboot boots so fast that connected monitors |
| (mostly TVs) won't be able to wake up fast enough to talk to the |
| VBIOS. On those systems we need to wait for a bit before executing |
| the VBIOS. |
| |
| config INTEL_PCH_UART_CONSOLE |
| bool "Use Serial IO UART for console" |
| default n |
| select DRIVERS_UART_8250MEM |
| |
| config INTEL_PCH_UART_CONSOLE_NUMBER |
| hex "Serial IO UART number to use for console" |
| default 0x0 |
| depends on INTEL_PCH_UART_CONSOLE |
| |
| config TTYS0_BASE |
| hex |
| default 0xd6000000 |
| depends on INTEL_PCH_UART_CONSOLE |
| |
| config EHCI_BAR |
| hex |
| default 0xd8000000 |
| |
| config SERIRQ_CONTINUOUS_MODE |
| bool |
| default y |
| help |
| If you set this option to y, the serial IRQ machine will be |
| operated in continuous mode. |
| |
| config HAVE_REFCODE_BLOB |
| depends on ARCH_X86 |
| bool "An external reference code blob should be put into cbfs." |
| default n |
| help |
| The reference code blob will be placed into cbfs. |
| |
| if HAVE_REFCODE_BLOB |
| |
| config REFCODE_BLOB_FILE |
| string "Path and filename to reference code blob." |
| default "refcode.elf" |
| help |
| The path and filename to the file to be added to cbfs. |
| |
| endif # HAVE_REFCODE_BLOB |
| |
| endif |