| chip soc/intel/tigerlake |
| # Power limits |
| register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ |
| .tdp_pl1_override = 20, |
| .tdp_pl2_override = 30, |
| }" |
| register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ |
| .tdp_pl1_override = 20, |
| .tdp_pl2_override = 30, |
| }" |
| |
| # GPE configuration |
| register "pmc_gpe0_dw0" = "PMC_GPP_R" |
| register "pmc_gpe0_dw1" = "PMC_GPP_B" |
| register "pmc_gpe0_dw2" = "PMC_GPP_D" |
| |
| device domain 0 on |
| subsystemid 0x1558 0x14a1 inherit |
| |
| device ref peg on |
| # PCIe PEG0 x4, Clock 3 (SSD1) |
| # Despite the name, SSD2_CLKREQ# is used for SSD1 |
| register "PcieClkSrcUsage[3]" = "0x40" |
| register "PcieClkSrcClkReq[3]" = "3" |
| chip soc/intel/common/block/pcie/rtd3 |
| register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # SSD1_PWR_DN# |
| register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # GPP_C12_RTD3 (labeled incorrectly) |
| register "srcclk_pin" = "3" # SSD2_CLKREQ# |
| device generic 0 on end |
| end |
| end |
| device ref north_xhci on # J_TYPEC1 |
| register "UsbTcPortEn" = "1" |
| register "TcssXhciEn" = "1" |
| chip drivers/usb/acpi |
| device ref tcss_root_hub on |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 J_TYPEC1"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "group" = "ACPI_PLD_GROUP(1, 1)" |
| device ref tcss_usb3_port1 on end |
| end |
| end |
| end |
| end |
| device ref tbt_dma0 on # J_TYPEC1 |
| chip drivers/intel/usb4/retimer |
| register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" |
| use tcss_usb3_port1 as dfp[0].typec_port |
| device generic 0 on end |
| end |
| end |
| |
| device ref south_xhci on |
| register "usb2_ports" = "{ |
| [0] = USB2_PORT_MID(OC_SKIP), /* J_USB3_1 */ |
| [1] = USB2_PORT_MID(OC_SKIP), /* J_USB3_2 */ |
| [2] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC1 */ |
| [6] = USB2_PORT_MID(OC_SKIP), /* Camera */ |
| [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ |
| }" |
| register "usb3_ports" = "{ |
| [0] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_1 */ |
| [1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_2 */ |
| }" |
| # ACPI |
| chip drivers/usb/acpi |
| device ref xhci_root_hub on |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 J_USB3_1"" |
| register "type" = "UPC_TYPE_A" |
| register "group" = "ACPI_PLD_GROUP(1, 2)" |
| device ref usb2_port1 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 J_USB3_2"" |
| register "type" = "UPC_TYPE_A" |
| register "group" = "ACPI_PLD_GROUP(2, 1)" |
| device ref usb2_port2 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 J_TYPEC1"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "group" = "ACPI_PLD_GROUP(1, 1)" |
| device ref usb2_port3 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Camera"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| device ref usb2_port7 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Bluetooth"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| device ref usb2_port10 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 J_USB3_1"" |
| register "type" = "UPC_TYPE_A" |
| register "group" = "ACPI_PLD_GROUP(1, 1)" |
| device ref usb3_port1 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 J_USB3_2"" |
| register "type" = "UPC_TYPE_A" |
| register "group" = "ACPI_PLD_GROUP(2, 1)" |
| device ref usb3_port2 on end |
| end |
| end |
| end |
| end |
| device ref sata on |
| # SATA1 (SSD2) |
| register "SataPortsEnable[1]" = "1" |
| register "SataPortsDevSlp[1]" = "1" |
| register "SataPortsEnableDitoConfig[1]" = "1" |
| register "SataSalpSupport" = "1" |
| end |
| device ref pcie_rp3 on |
| # PCIe root port #3 x1, Clock 1 (WLAN) |
| register "PcieRpEnable[2]" = "1" |
| register "PcieRpLtrEnable[2]" = "1" |
| register "PcieClkSrcUsage[1]" = "2" |
| register "PcieClkSrcClkReq[1]" = "1" |
| register "PcieRpSlotImplemented[2]" = "1" |
| end |
| device ref pcie_rp6 on |
| # PCIe root port #6 x1, Clock 2 (CARD) |
| register "PcieRpEnable[5]" = "1" |
| register "PcieRpLtrEnable[5]" = "1" |
| register "PcieClkSrcUsage[2]" = "5" |
| register "PcieClkSrcClkReq[2]" = "2" |
| end |
| device ref pcie_rp9 on |
| # PCIe root port #9 x4, Clock 0 (SSD2) |
| # Despite the name, SSD1_CLKREQ# is used for SSD2 |
| register "PcieRpEnable[8]" = "1" |
| register "PcieRpLtrEnable[8]" = "1" |
| register "PcieClkSrcUsage[0]" = "8" |
| register "PcieClkSrcClkReq[0]" = "0" |
| register "PcieRpSlotImplemented[8]" = "1" |
| chip soc/intel/common/block/pcie/rtd3 |
| register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_DN# |
| register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" # GPP_D13_RTD3 (labeled incorrectly) |
| register "srcclk_pin" = "0" |
| device generic 0 on end |
| end |
| end |
| device ref pmc hidden |
| # The pmc_mux chip driver is a placeholder for the |
| # PMC.MUX device in the ACPI hierarchy. |
| chip drivers/intel/pmc_mux |
| device generic 0 on |
| chip drivers/intel/pmc_mux/conn |
| # J_TYPEC1 |
| use usb2_port3 as usb2_port |
| use tcss_usb3_port1 as usb3_port |
| # SBU & HSL follow CC |
| device generic 0 alias conn0 on end |
| end |
| end |
| end |
| end |
| end |
| end |