| config SOC_INTEL_COMMON_BLOCK_TCSS |
| def_bool n |
| select FSPS_USE_MULTI_PHASE_INIT |
| help |
| Sets up USB2/3 port mapping in TCSS MUX and sets MUX to disconnect state |
| |
| config ENABLE_TCSS_DISPLAY_DETECTION |
| bool "Enable detection of displays over USB Type-C ports with TCSS" |
| depends on SOC_INTEL_COMMON_BLOCK_TCSS && RUN_FSP_GOP |
| help |
| Enable displays to be detected over Type-C ports during boot. |
| |
| config SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR |
| def_bool n |
| depends on SOC_INTEL_COMMON_BLOCK_TCSS |
| help |
| Enable TCSS registers access through REGBAR for platforms like |
| Tiger Lake and Alder Lake |
| |
| config SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_SBI |
| def_bool n |
| depends on SOC_INTEL_COMMON_BLOCK_TCSS |
| help |
| Enable TCSS registers access through Sideband interface on applicable SoC platforms |