| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| |
| chip northbridge/intel/sandybridge |
| device cpu_cluster 0x0 on |
| chip cpu/intel/model_206ax |
| register "c1_acpower" = "1" |
| register "c1_battery" = "1" |
| register "c2_acpower" = "3" |
| register "c2_battery" = "3" |
| register "c3_acpower" = "5" |
| register "c3_battery" = "5" |
| device lapic 0x0 on end |
| device lapic 0xacac off end |
| end |
| end |
| device domain 0x0 on |
| subsystemid 0x1043 0x84ca inherit |
| device pci 00.0 on end # Host bridge |
| device pci 01.0 on end # PCIe Bridge for discrete graphics |
| device pci 02.0 on end # Internal graphics VGA controller |
| |
| chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH |
| register "c2_latency" = "0x0065" |
| register "gen1_dec" = "0x000c0291" |
| register "gen4_dec" = "0x0000ff29" |
| register "pcie_port_coalesce" = "1" |
| register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII |
| register "sata_port_map" = "0x3f" # Enable the six SATA ports |
| register "spi_lvscc" = "0x2005" |
| register "spi_uvscc" = "0x2005" |
| register "superspeed_capable_ports" = "0x0000000f" |
| register "xhci_overcurrent_mapping" = "0x00000c03" |
| register "xhci_switchable_ports" = "0x0000000f" # the 4 ports |
| |
| device pci 14.0 on end # USB 3.0 Controller |
| device pci 16.0 on end # Management Engine Interface 1 |
| device pci 16.1 off end # Management Engine Interface 2 |
| device pci 16.2 off end # Management Engine IDE-R |
| device pci 16.3 off end # Management Engine KT |
| device pci 19.0 off end # Intel Gigabit Ethernet |
| device pci 1a.0 on end # USB2 EHCI 2 |
| device pci 1b.0 on end # High Definition Audio controller |
| device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 |
| device pci 1c.1 on end # PCIe Port 2 RTL8111F |
| device pci 1c.2 off end # PCIe Port 3 unused |
| device pci 1c.3 off end # PCIe Port 4 unused |
| device pci 1c.4 off end # PCIe Port 5 unused |
| device pci 1c.5 on end # PCIe Port 6 ASM1042 USB3 |
| device pci 1c.6 on end # PCIe Port 7 ASM1061 eSATA |
| device pci 1c.7 off end # PCIe Port 8 unused |
| device pci 1d.0 on end # USB2 EHCI 1 |
| device pci 1e.0 off end # PCI bridge |
| device pci 1f.0 on # LPC bridge |
| chip superio/nuvoton/nct6779d |
| device pnp 2e.1 off end # Parallel |
| device pnp 2e.2 off end # UART A |
| device pnp 2e.3 on # UART B, IR |
| io 0x60 = 0x2f8 # COM2 address |
| end |
| device pnp 2e.5 on # PS2 KBC |
| io 0x60 = 0x0060 # KBC1 base |
| io 0x62 = 0x0064 # KBC2 base |
| irq 0x70 = 1 # Keyboard IRQ |
| irq 0x72 = 12 # Mouse IRQ |
| |
| # KBC 12Mhz/A20 speed/sw KBRST |
| drq 0xf0 = 0x82 |
| end |
| device pnp 2e.6 off end # CIR |
| device pnp 2e.7 on end # GPIOs 6-8 |
| device pnp 2e.8 off end # WDT1 GPIO 0-1 |
| device pnp 2e.9 off end # GPIO 1-8 |
| device pnp 2e.a on # ACPI |
| drq 0xe4 = 0x10 # Enable 3VSBS to power RAM on S3 |
| drq 0xe7 = 0x10 # 0.5s S3 delay for compatibility |
| end |
| device pnp 2e.b off end # HWM, LED |
| device pnp 2e.d off end # WDT1 |
| device pnp 2e.e off end # CIR wake-up |
| device pnp 2e.f on # GPIO PP/OD |
| drq 0xe6 = 0x7f # GP7 PP |
| end |
| device pnp 2e.14 on end # Port 80 UART |
| device pnp 2e.16 off end # Deep sleep |
| end |
| chip drivers/pc80/tpm |
| device pnp 4e.0 on end # TPM |
| end |
| end |
| device pci 1f.2 on end # SATA Controller 1 |
| device pci 1f.3 on end # SMBus |
| device pci 1f.5 off end # SATA Controller 2 |
| device pci 1f.6 off end # Thermal |
| end |
| end |
| end |