| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; either version 2 of the License, or |
| ## (at your option) any later version. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| ## You should have received a copy of the GNU General Public License |
| ## along with this program; if not, write to the Free Software |
| ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| ## |
| |
| uses HAVE_MP_TABLE |
| uses CONFIG_ROMFS |
| uses HAVE_PIRQ_TABLE |
| uses USE_FALLBACK_IMAGE |
| uses USE_FAILOVER_IMAGE |
| uses HAVE_FALLBACK_BOOT |
| uses HAVE_FAILOVER_BOOT |
| uses HAVE_HARD_RESET |
| uses IRQ_SLOT_COUNT |
| uses HAVE_OPTION_TABLE |
| uses CONFIG_MAX_CPUS |
| uses CONFIG_MAX_PHYSICAL_CPUS |
| uses CONFIG_LOGICAL_CPUS |
| uses CONFIG_IOAPIC |
| uses CONFIG_SMP |
| uses FALLBACK_SIZE |
| uses FAILOVER_SIZE |
| uses ROM_SIZE |
| uses ROM_SECTION_SIZE |
| uses ROM_IMAGE_SIZE |
| uses ROM_SECTION_SIZE |
| uses ROM_SECTION_OFFSET |
| uses CONFIG_ROM_PAYLOAD |
| uses CONFIG_ROM_PAYLOAD_START |
| uses CONFIG_COMPRESSED_PAYLOAD_NRV2B |
| uses CONFIG_COMPRESSED_PAYLOAD_LZMA |
| uses CONFIG_PRECOMPRESSED_PAYLOAD |
| uses PAYLOAD_SIZE |
| uses _ROMBASE |
| uses XIP_ROM_SIZE |
| uses XIP_ROM_BASE |
| uses STACK_SIZE |
| uses HEAP_SIZE |
| uses USE_OPTION_TABLE |
| uses LB_CKS_RANGE_START |
| uses LB_CKS_RANGE_END |
| uses LB_CKS_LOC |
| uses MAINBOARD_PART_NUMBER |
| uses MAINBOARD_VENDOR |
| uses MAINBOARD |
| uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID |
| uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID |
| uses COREBOOT_EXTRA_VERSION |
| uses _RAMBASE |
| uses TTYS0_BAUD |
| uses TTYS0_BASE |
| uses TTYS0_LCS |
| uses DEFAULT_CONSOLE_LOGLEVEL |
| uses MAXIMUM_CONSOLE_LOGLEVEL |
| uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL |
| uses CONFIG_CONSOLE_SERIAL8250 |
| uses HAVE_INIT_TIMER # ? |
| uses CROSS_COMPILE |
| uses CC |
| uses HOSTCC |
| uses OBJCOPY |
| uses CONFIG_CONSOLE_VGA |
| uses CONFIG_PCI_ROM_RUN |
| uses CONFIG_USBDEBUG_DIRECT |
| uses HW_MEM_HOLE_SIZEK |
| uses HW_MEM_HOLE_SIZE_AUTO_INC |
| uses K8_HT_FREQ_1G_SUPPORT |
| uses HT_CHAIN_UNITID_BASE |
| uses HT_CHAIN_END_UNITID_BASE |
| uses SB_HT_CHAIN_ON_BUS0 |
| uses SB_HT_CHAIN_UNITID_OFFSET_ONLY |
| uses USE_DCACHE_RAM |
| uses DCACHE_RAM_BASE |
| uses DCACHE_RAM_SIZE |
| uses DCACHE_RAM_GLOBAL_VAR_SIZE |
| uses CONFIG_USE_INIT |
| uses SERIAL_CPU_INIT |
| uses ENABLE_APIC_EXT_ID |
| uses APIC_ID_OFFSET |
| uses LIFT_BSP_APIC_ID |
| uses CONFIG_PCI_64BIT_PREF_MEM |
| uses CONFIG_LB_MEM_TOPK |
| uses CONFIG_AP_CODE_IN_CAR |
| uses MEM_TRAIN_SEQ |
| uses WAIT_BEFORE_CPUS_INIT |
| uses CONFIG_USE_PRINTK_IN_CAR |
| |
| default ROM_SIZE = 512 * 1024 |
| default FALLBACK_SIZE = (256 * 1024) - (4 * 1024) |
| default FAILOVER_SIZE = 4 * 1024 |
| default CONFIG_LB_MEM_TOPK = 2048 # 1MB more for pgtbl. |
| default HAVE_FALLBACK_BOOT = 1 |
| default HAVE_FAILOVER_BOOT = 1 |
| default HAVE_HARD_RESET = 1 |
| default HAVE_PIRQ_TABLE = 1 |
| default IRQ_SLOT_COUNT = 11 # TODO: Check if correct. |
| default HAVE_MP_TABLE = 1 # TODO: Check if correct. |
| default HAVE_OPTION_TABLE = 1 |
| default CONFIG_SMP = 1 |
| default CONFIG_MAX_CPUS = 2 |
| default CONFIG_MAX_PHYSICAL_CPUS = 1 |
| default CONFIG_LOGICAL_CPUS = 1 |
| # default SERIAL_CPU_INIT = 0 |
| default ENABLE_APIC_EXT_ID = 0 |
| default APIC_ID_OFFSET = 0x10 |
| default LIFT_BSP_APIC_ID = 1 |
| |
| # Move the default coreboot CMOS range off of AMD RTC registers. |
| default LB_CKS_RANGE_START = 49 |
| default LB_CKS_RANGE_END = 122 |
| default LB_CKS_LOC = 123 |
| |
| # Memory hole size. 0 means disable, others will enable the hole. In that |
| # case, if it is smaller than mmio_basek, it will use mmio_basek instead. |
| # default HW_MEM_HOLE_SIZEK = 0x200000 # 2GB |
| default HW_MEM_HOLE_SIZEK = 0x100000 # 1GB |
| # default HW_MEM_HOLE_SIZEK = 0x80000 # 512MB |
| |
| # Make auto increase hole size to avoid hole_startk equal to basek so as |
| # to make some kernel happy. |
| # default HW_MEM_HOLE_SIZE_AUTO_INC = 1 |
| |
| # Opteron K8 1G HT support. |
| default K8_HT_FREQ_1G_SUPPORT = 1 |
| |
| # HT Unit ID offset, default is 1, the typical one, 0 means only one HT device. |
| default HT_CHAIN_UNITID_BASE = 0 |
| |
| # Real SB Unit ID, default is 0x20, mean don't touch it at last. |
| # default HT_CHAIN_END_UNITID_BASE = 0x6 |
| |
| # Make the SB HT chain on bus 0, default is not (0). |
| default SB_HT_CHAIN_ON_BUS0 = 2 |
| |
| # Only offset for SB chain? Default is yes (1). |
| default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 |
| |
| # Allow capable device use that above 4GB. |
| # default CONFIG_PCI_64BIT_PREF_MEM = 1 |
| |
| default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. |
| default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA. |
| default CONFIG_USBDEBUG_DIRECT = 0 |
| default USE_DCACHE_RAM = 1 |
| default DCACHE_RAM_BASE = 0xc8000 |
| default DCACHE_RAM_SIZE = 0x08000 |
| default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 |
| default CONFIG_USE_INIT = 0 |
| default CONFIG_AP_CODE_IN_CAR = 0 |
| default MEM_TRAIN_SEQ = 2 |
| default WAIT_BEFORE_CPUS_INIT = 0 |
| default CONFIG_IOAPIC = 1 |
| default MAINBOARD_PART_NUMBER = "K9N Neo (MS-7260)" |
| default MAINBOARD_VENDOR = "MSI" |
| default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 |
| default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260 |
| default ROM_IMAGE_SIZE = 65536 |
| default STACK_SIZE = 0x2000 |
| default HEAP_SIZE = 0x8000 |
| default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE) |
| default _RAMBASE = 0x00100000 |
| default CONFIG_ROM_PAYLOAD = 1 |
| default CC = "$(CROSS_COMPILE)gcc -m32" |
| default HOSTCC = "gcc" |
| default CONFIG_USE_PRINTK_IN_CAR = 1 |
| default CONFIG_CONSOLE_SERIAL8250 = 1 |
| default TTYS0_BAUD = 115200 |
| default TTYS0_BASE = 0x3f8 |
| default TTYS0_LCS = 0x3 |
| default DEFAULT_CONSOLE_LOGLEVEL = 9 |
| default MAXIMUM_CONSOLE_LOGLEVEL = 9 |
| default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" |
| |
| # |
| # ROMFS |
| # |
| # |
| default CONFIG_ROMFS=0 |
| end |