| # SPDX-License-Identifier: GPL-2.0-only |
| |
| config SOC_AMD_CEZANNE |
| bool |
| help |
| AMD Cezanne support |
| |
| if SOC_AMD_CEZANNE |
| |
| config SOC_SPECIFIC_OPTIONS |
| def_bool y |
| select ACPI_SOC_NVS |
| select ARCH_BOOTBLOCK_X86_32 |
| select ARCH_VERSTAGE_X86_32 |
| select ARCH_ROMSTAGE_X86_32 |
| select ARCH_RAMSTAGE_X86_32 |
| select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
| select DRIVERS_USB_ACPI |
| select DRIVERS_I2C_DESIGNWARE |
| select DRIVERS_USB_PCI_XHCI |
| select FSP_COMPRESS_FSP_M_LZMA |
| select FSP_COMPRESS_FSP_S_LZMA |
| select GENERIC_GPIO_LIB |
| select HAVE_ACPI_TABLES |
| select HAVE_CF9_RESET |
| select HAVE_EM100_SUPPORT |
| select HAVE_FSP_GOP |
| select HAVE_SMI_HANDLER |
| select IDT_IN_EVERY_STAGE |
| select IOAPIC |
| select PARALLEL_MP |
| select PARALLEL_MP_AP_WORK |
| select PLATFORM_USES_FSP2_0 |
| select PROVIDES_ROM_SHARING |
| select RESET_VECTOR_IN_RAM |
| select RTC |
| select SOC_AMD_COMMON |
| select SOC_AMD_COMMON_BLOCK_ACPI |
| select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
| select SOC_AMD_COMMON_BLOCK_ACPI_GPIO |
| select SOC_AMD_COMMON_BLOCK_AOAC |
| select SOC_AMD_COMMON_BLOCK_APOB |
| select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
| select SOC_AMD_COMMON_BLOCK_DATA_FABRIC |
| select SOC_AMD_COMMON_BLOCK_GRAPHICS |
| select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
| select SOC_AMD_COMMON_BLOCK_I2C |
| select SOC_AMD_COMMON_BLOCK_LPC |
| select SOC_AMD_COMMON_BLOCK_NONCAR |
| select SOC_AMD_COMMON_BLOCK_PCI |
| select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
| select SOC_AMD_COMMON_BLOCK_PM |
| select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE |
| select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
| select SOC_AMD_COMMON_BLOCK_SMBUS |
| select SOC_AMD_COMMON_BLOCK_SMI |
| select SOC_AMD_COMMON_BLOCK_SMM |
| select SOC_AMD_COMMON_BLOCK_SMU |
| select SOC_AMD_COMMON_BLOCK_SPI |
| select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H |
| select SOC_AMD_COMMON_BLOCK_UART |
| select SOC_AMD_COMMON_BLOCK_UCODE |
| select SSE2 |
| select UDK_2017_BINDING |
| select X86_AMD_FIXED_MTRRS |
| select X86_AMD_INIT_SIPI |
| |
| config SOC_AMD_COMMON_BLOCK_UCODE_SIZE |
| default 5568 |
| |
| config CHIPSET_DEVICETREE |
| string |
| default "soc/amd/cezanne/chipset.cb" |
| |
| config EARLY_RESERVED_DRAM_BASE |
| hex |
| default 0x2000000 |
| help |
| This variable defines the base address of the DRAM which is reserved |
| for usage by coreboot in early stages (i.e. before ramstage is up). |
| This memory gets reserved in BIOS tables to ensure that the OS does |
| not use it, thus preventing corruption of OS memory in case of S3 |
| resume. |
| |
| config EARLYRAM_BSP_STACK_SIZE |
| hex |
| default 0x1000 |
| |
| config PSP_APOB_DRAM_ADDRESS |
| hex |
| default 0x2001000 |
| help |
| Location in DRAM where the PSP will copy the AGESA PSP Output |
| Block. |
| |
| config PRERAM_CBMEM_CONSOLE_SIZE |
| hex |
| default 0x1600 |
| help |
| Increase this value if preram cbmem console is getting truncated |
| |
| config C_ENV_BOOTBLOCK_SIZE |
| hex |
| default 0x10000 |
| help |
| Sets the size of the bootblock stage that should be loaded in DRAM. |
| This variable controls the DRAM allocation size in linker script |
| for bootblock stage. |
| |
| config ROMSTAGE_ADDR |
| hex |
| default 0x2040000 |
| help |
| Sets the address in DRAM where romstage should be loaded. |
| |
| config ROMSTAGE_SIZE |
| hex |
| default 0x80000 |
| help |
| Sets the size of DRAM allocation for romstage in linker script. |
| |
| config FSP_M_ADDR |
| hex |
| default 0x20C0000 |
| help |
| Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| performs relocation of FSP-M to this address. |
| |
| config FSP_M_SIZE |
| hex |
| default 0x80000 |
| help |
| Sets the size of DRAM allocation for FSP-M in linker script. |
| |
| config FSP_TEMP_RAM_SIZE |
| hex |
| default 0x40000 |
| help |
| The amount of coreboot-allocated heap and stack usage by the FSP. |
| |
| config VERSTAGE_ADDR |
| hex |
| depends on VBOOT_SEPARATE_VERSTAGE |
| default 0x2140000 |
| help |
| Sets the address in DRAM where verstage should be loaded if running |
| as a separate stage on x86. |
| |
| config VERSTAGE_SIZE |
| hex |
| depends on VBOOT_SEPARATE_VERSTAGE |
| default 0x80000 |
| help |
| Sets the size of DRAM allocation for verstage in linker script if |
| running as a separate stage on x86. |
| |
| config RAMBASE |
| hex |
| default 0x10000000 |
| |
| config RO_REGION_ONLY |
| string |
| depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A |
| default "apu/amdfw" |
| |
| config CPU_ADDR_BITS |
| int |
| default 48 |
| |
| config MMCONF_BASE_ADDRESS |
| default 0xF8000000 |
| |
| config MMCONF_BUS_NUMBER |
| default 64 |
| |
| config MAX_CPUS |
| int |
| default 16 |
| |
| config CONSOLE_UART_BASE_ADDRESS |
| depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| hex |
| default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| |
| config SMM_TSEG_SIZE |
| hex |
| default 0x800000 if HAVE_SMI_HANDLER |
| default 0x0 |
| |
| config SMM_RESERVED_SIZE |
| hex |
| default 0x180000 |
| |
| config SMM_MODULE_STACK_SIZE |
| hex |
| default 0x800 |
| |
| config ACPI_BERT |
| bool "Build ACPI BERT Table" |
| default y |
| depends on HAVE_ACPI_TABLES |
| help |
| Report Machine Check errors identified in POST to the OS in an |
| ACPI Boot Error Record Table. |
| |
| config ACPI_BERT_SIZE |
| hex |
| default 0x4000 if ACPI_BERT |
| default 0x0 |
| help |
| Specify the amount of DRAM reserved for gathering the data used to |
| generate the ACPI table. |
| |
| config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| int |
| default 150 |
| |
| config DISABLE_SPI_FLASH_ROM_SHARING |
| def_bool n |
| help |
| Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin |
| which indicates a board level ROM transaction request. This |
| removes arbitration with board and assumes the chipset controls |
| the SPI flash bus entirely. |
| |
| config DISABLE_KEYBOARD_RESET_PIN |
| bool |
| help |
| Instruct the SoC to not use the state of GPIO_129 as keyboard reset |
| signal. When this pin is used as GPIO and the keyboard reset |
| functionality isn't disabled, configuring it as an output and driving |
| it as 0 will cause a reset. |
| |
| config ACPI_SSDT_PSD_INDEPENDENT |
| bool "Allow core p-state independent transitions" |
| default y |
| help |
| AMD recommends the ACPI _PSD object to be configured to cause |
| cores to transition between p-states independently. A vendor may |
| choose to generate _PSD object to allow cores to transition together. |
| |
| menu "PSP Configuration Options" |
| |
| config AMD_FWM_POSITION_INDEX |
| int "Firmware Directory Table location (0 to 5)" |
| range 0 5 |
| default 0 if BOARD_ROMSIZE_KB_512 |
| default 1 if BOARD_ROMSIZE_KB_1024 |
| default 2 if BOARD_ROMSIZE_KB_2048 |
| default 3 if BOARD_ROMSIZE_KB_4096 |
| default 4 if BOARD_ROMSIZE_KB_8192 |
| default 5 if BOARD_ROMSIZE_KB_16384 |
| help |
| Typically this is calculated by the ROM size, but there may |
| be situations where you want to put the firmware directory |
| table in a different location. |
| 0: 512 KB - 0xFFFA0000 |
| 1: 1 MB - 0xFFF20000 |
| 2: 2 MB - 0xFFE20000 |
| 3: 4 MB - 0xFFC20000 |
| 4: 8 MB - 0xFF820000 |
| 5: 16 MB - 0xFF020000 |
| |
| comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 0 |
| comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 1 |
| comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 2 |
| comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 3 |
| comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 4 |
| comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 5 |
| |
| config AMDFW_CONFIG_FILE |
| string |
| default "src/soc/amd/cezanne/fw.cfg" |
| |
| config PSP_DISABLE_POSTCODES |
| bool "Disable PSP post codes" |
| help |
| Disables the output of port80 post codes from PSP. |
| |
| config PSP_POSTCODES_ON_ESPI |
| bool "Use eSPI bus for PSP post codes" |
| default y |
| depends on !PSP_DISABLE_POSTCODES |
| help |
| Select to send PSP port80 post codes on eSPI bus. |
| If not selected, PSP port80 codes will be sent on LPC bus. |
| |
| config PSP_LOAD_MP2_FW |
| bool |
| default n |
| help |
| Include the MP2 firmwares and configuration into the PSP build. |
| |
| If unsure, answer 'n' |
| |
| config PSP_UNLOCK_SECURE_DEBUG |
| bool "Unlock secure debug" |
| default y |
| help |
| Select this item to enable secure debug options in PSP. |
| |
| config HAVE_PSP_WHITELIST_FILE |
| bool "Include a debug whitelist file in PSP build" |
| default n |
| help |
| Support secured unlock prior to reset using a whitelisted |
| serial number. This feature requires a signed whitelist image |
| and bootloader from AMD. |
| |
| If unsure, answer 'n' |
| |
| config PSP_WHITELIST_FILE |
| string "Debug whitelist file path" |
| depends on HAVE_PSP_WHITELIST_FILE |
| default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin" |
| |
| config PSP_SOFTFUSE_BITS |
| string "PSP Soft Fuse bits to enable" |
| default "28 6" |
| help |
| Space separated list of Soft Fuse bits to enable. |
| Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) |
| Bit 7: Disable PSP postcodes on Renoir and newer chips only |
| (Set by PSP_DISABLE_PORT80) |
| Bit 15: PSP post code destination: 0=LPC 1=eSPI |
| (Set by PSP_INITIALIZE_ESPI) |
| Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) |
| |
| See #55758 (NDA) for additional bit definitions. |
| |
| endmenu |
| |
| config VBOOT |
| select VBOOT_VBNV_CMOS |
| select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| |
| endif # SOC_AMD_CEZANNE |