AMD CPU and chipset fixes for compilation with gcc 4.6
Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/266
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c
index bf80ef8..2ecc0d0 100644
--- a/src/northbridge/amd/amdk8/early_ht.c
+++ b/src/northbridge/amd/amdk8/early_ht.c
@@ -16,8 +16,8 @@
device_t dev;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
//let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
- unsigned real_last_unitid;
- uint8_t real_last_pos;
+ unsigned real_last_unitid = 0;
+ uint8_t real_last_pos = 0;
int ht_dev_num = 0; // except host_bridge
uint8_t end_used = 0;
#endif
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 4d0d025..a14adac 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -305,8 +305,8 @@
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
//let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
- unsigned real_last_unitid;
- uint8_t real_last_pos;
+ unsigned real_last_unitid = 0;
+ uint8_t real_last_pos = 0;
int ht_dev_num = 0;
uint8_t end_used = 0;
#endif
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 1191536..1faed5a 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -1353,7 +1353,7 @@
u16 tCKproposed16x;
u8 CLactual, CLdesired, CLT_Fail;
- u8 smbaddr, byte, bytex;
+ u8 smbaddr, byte = 0, bytex = 0;
CASLatLow = 0xFF;
CASLatHigh = 0xFF;
@@ -2768,7 +2768,7 @@
static void Get_WrDatGross_Diff(struct DCTStatStruc *pDCTstat,
u8 dct, u32 dev, u32 index_reg)
{
- u8 Smallest, Largest;
+ u8 Smallest = 0, Largest = 0;
u32 val;
u8 byte, bytex;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 54fdedf..3e1b13d 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -849,7 +849,7 @@
u32 value;
u8 j;
u32 value_test;
- u32 value_r, value_r_test;
+ u32 value_r = 0, value_r_test = 0;
u8 pattern, channel, BeatCnt;
struct DCTStatStruc *ptrAddr;
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index b8c7d04..cf6d2df 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -190,7 +190,7 @@
{
/* NB_InitGFXStraps */
u32 MMIOBase, apc04, apc18, apc24, romstrap2;
- msr_t pcie_mmio_save;
+ msr_t pcie_mmio_save = { 0, 0 };
volatile u32 * strap;
// disable processor pcie mmio, if enabled