| ## SPDX-License-Identifier: GPL-2.0-only |
| |
| config SOC_INTEL_SKYLAKE_SP |
| bool |
| select XEON_SP_COMMON_BASE |
| select PLATFORM_USES_FSP2_0 |
| select NO_FSP_TEMP_RAM_EXIT |
| select UDK_202005_BINDING |
| help |
| Intel Skylake-SP support |
| |
| if SOC_INTEL_SKYLAKE_SP |
| |
| config FSP_HEADER_PATH |
| string "Location of FSP headers" |
| default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" |
| |
| config MAX_SOCKET |
| int |
| default 2 |
| |
| # For 2S config, the number of cpus could be as high as |
| # 2 threads * 20 cores * 2 sockets |
| config MAX_CPUS |
| int |
| default 80 |
| |
| config PCR_BASE_ADDRESS |
| hex |
| default 0xfd000000 |
| help |
| This option allows you to select MMIO Base Address of sideband bus. |
| |
| config DCACHE_RAM_BASE |
| hex |
| default 0xfe800000 |
| |
| config DCACHE_RAM_SIZE |
| hex |
| default 0x200000 |
| |
| config DCACHE_BSP_STACK_SIZE |
| hex |
| default 0x10000 |
| |
| config CPU_MICROCODE_CBFS_LOC |
| hex |
| default 0xfff0fdc0 |
| |
| config CPU_MICROCODE_CBFS_LEN |
| hex |
| default 0x7C00 |
| |
| config IED_REGION_SIZE |
| hex |
| default 0x400000 |
| |
| config IFD_CHIPSET |
| string |
| default "lbg" |
| |
| config XEON_SP_HAVE_IIO_IOAPIC |
| bool |
| default y |
| |
| endif |