| chip soc/intel/elkhartlake |
| |
| device cpu_cluster 0 on end |
| |
| # GPE configuration |
| # Note that GPE events called out in ASL code rely on this |
| # route. i.e. If this route changes then the affected GPE |
| # offset bits also need to be changed. |
| register "pmc_gpe0_dw0" = "GPP_B" |
| register "pmc_gpe0_dw1" = "GPP_F" |
| register "pmc_gpe0_dw2" = "GPP_E" |
| |
| # FSP configuration |
| register "SaGv" = "SaGv_Disabled" |
| |
| # Enable IBECC for the complete memory |
| register "ibecc" = "{ |
| .enable = 1, |
| .mode = IBECC_ALL |
| }" |
| |
| # USB related UPDs |
| register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # X125 |
| register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # X135 |
| register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # internal USB-OC |
| register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Port is unused |
| register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Port is unused |
| register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Port is unused |
| register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Port is unused |
| register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Port is unused |
| register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Port is unused |
| register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Port is unused |
| |
| register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1 |
| register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Port is not used |
| register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Port is not used |
| register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Port is not used |
| |
| # Skip the CPU replacement check |
| register "SkipCpuReplacementCheck" = "1" |
| |
| # PCIe root ports related UPDs |
| register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" |
| register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" |
| register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" |
| register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE" |
| register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" |
| register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" |
| |
| register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" |
| register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" |
| register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" |
| register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED" |
| register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" |
| register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" |
| |
| # Disable all L1 substates for PCIe root ports |
| register "PcieRpL1Substates[0]" = "L1_SS_DISABLED" |
| register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" |
| register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" |
| register "PcieRpL1Substates[3]" = "L1_SS_DISABLED" |
| register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" |
| |
| # Disable LTR for all PCIe root ports |
| register "PcieRpLtrDisable[0]" = "true" |
| register "PcieRpLtrDisable[1]" = "true" |
| register "PcieRpLtrDisable[2]" = "true" |
| register "PcieRpLtrDisable[3]" = "true" |
| register "PcieRpLtrDisable[4]" = "true" |
| |
| # Determines PCIe root port speed |
| register "PcieRpPcieSpeed[3]" = "1" |
| register "PcieRpPcieSpeed[4]" = "1" |
| |
| register "PcieRpMaxPayload[1]" = "RpMaxPayload_256" |
| register "PcieRpMaxPayload[2]" = "RpMaxPayload_256" |
| |
| # Storage (SATA/SDCARD/EMMC) related UPDs |
| register "SataSalpSupport" = "0" |
| register "SataPortsEnable[0]" = "1" |
| register "SataPortsEnable[1]" = "1" |
| register "SataPortsDevSlp[0]" = "0" |
| register "SataPortsDevSlp[1]" = "0" |
| register "SataSpeed" = "SATA_GEN2" |
| |
| register "ScsEmmcHs400Enabled" = "0" |
| register "ScsEmmcDdr50Enabled" = "1" |
| register "SdCardPowerEnableActiveHigh" = "1" |
| # GPIO for SD card detect |
| register "sdcard_cd_gpio" = "GPP_G5" |
| |
| # LPSS Serial IO (I2C/UART/GSPI) related UPDs |
| register "SerialIoI2cMode" = "{ |
| [PchSerialIoIndexI2C0] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C6] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C7] = PchSerialIoDisabled, |
| }" |
| |
| register "SerialIoI2cPadsTermination" = "{ |
| [PchSerialIoIndexI2C0] = 1, |
| [PchSerialIoIndexI2C1] = 1, |
| [PchSerialIoIndexI2C2] = 1, |
| [PchSerialIoIndexI2C3] = 1, |
| [PchSerialIoIndexI2C4] = 1, |
| [PchSerialIoIndexI2C5] = 1, |
| [PchSerialIoIndexI2C6] = 1, |
| [PchSerialIoIndexI2C7] = 1, |
| }" |
| |
| register "SerialIoUartMode" = "{ |
| [PchSerialIoIndexUART0] = PchSerialIoPci, |
| [PchSerialIoIndexUART1] = PchSerialIoPci, |
| [PchSerialIoIndexUART2] = PchSerialIoSkipInit, |
| }" |
| |
| register "SerialIoUartDmaEnable" = "{ |
| [PchSerialIoIndexUART0] = 1, |
| [PchSerialIoIndexUART1] = 1, |
| [PchSerialIoIndexUART2] = 1, |
| }" |
| |
| # TSN GBE related UPDs |
| register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" |
| register "PchTsnGbeSgmiiEnable" = "1" |
| |
| # FIVR related settings |
| register "fivr" = "{ |
| .fivr_config_en = true, |
| .vcc_low_high_us = 50, |
| }" |
| |
| # Disable L1 prefetcher |
| register "L1_prefetcher_disable" = "true" |
| |
| # Enable real-time tuning |
| register "realtime_tuning_enable" = "true" |
| |
| device domain 0 on |
| device pci 00.0 on end # Host Bridge |
| device pci 02.0 on end # Integrated Graphics Device |
| |
| device pci 14.0 on end # USB3.1 xHCI |
| |
| device pci 15.0 off end # I2C0 |
| device pci 15.1 on # I2C1 |
| # Enable external RTC chip |
| chip drivers/i2c/rv3028c7 |
| register "bus_speed" = "I2C_SPEED_STANDARD" |
| register "set_user_date" = "1" |
| register "user_year" = "04" |
| register "user_month" = "07" |
| register "user_day" = "01" |
| register "user_weekday" = "4" |
| register "bckup_sw_mode" = "BACKUP_SW_LEVEL" |
| register "cap_charge" = "CHARGE_OFF" |
| device i2c 0x52 on end # RTC RV3028-C7 |
| end |
| end |
| |
| device pci 16.0 hidden end # Management Engine Interface 1 |
| |
| device pci 17.0 on end # SATA |
| |
| device pci 19.0 on end # I2C4 |
| device pci 19.2 on end # UART2 |
| |
| device pci 1a.0 on end # eMMC |
| device pci 1a.1 on end # SD |
| |
| device pci 1c.0 on end # RP1 (pcie0 single VC) |
| device pci 1c.1 on end # RP2 (pcie0 single VC) |
| device pci 1c.2 on end # RP3 (pcie0 single VC) |
| device pci 1c.3 on end # RP4 (pcie0 single VC) |
| device pci 1c.4 on end # RP5 (pcie1 multi VC) |
| |
| device pci 1e.0 on end # UART0 |
| device pci 1e.1 on end # UART1 |
| |
| device pci 1f.0 on end # eSPI Interface |
| device pci 1f.2 hidden end # Power Management Controller |
| device pci 1f.4 on end # SMBus |
| device pci 1f.5 on end # PCH SPI (flash & TPM) |
| end |
| end |