tree: Remove blank lines before '}' and after '{'
Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/device/mmio.c b/src/device/mmio.c
index b62805a..ec9acfa 100644
--- a/src/device/mmio.c
+++ b/src/device/mmio.c
@@ -40,5 +40,4 @@
val = 0;
j = 0;
}
-
}
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 8ead8a5..af3355d 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -1491,7 +1491,6 @@
prev = &bus->children;
for (dev = bus->children; dev; dev = dev->sibling) {
-
/*
* If static device is not PCI then enable it here and don't
* treat it as a leftover device.
@@ -1851,7 +1850,6 @@
slot = dev->path.pci.devfn >> 3;
for (; dev ; dev = dev->sibling) {
-
if (dev->path.pci.devfn >> 3 != slot)
break;
diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c
index c9630bb..44782d8 100644
--- a/src/device/resource_allocator_v4.c
+++ b/src/device/resource_allocator_v4.c
@@ -140,7 +140,6 @@
print_bridge_res(bridge, bridge_res, print_depth, "");
while ((child = largest_resource(bus, &child_res, type_mask, type_match))) {
-
/* Size 0 resources can be skipped. */
if (!child_res->size)
continue;
@@ -260,7 +259,6 @@
return;
for (child = domain->downstream->children; child; child = child->sibling) {
-
/* Skip if this is not a bridge or has no children under it. */
if (!dev_has_children(child))
continue;
@@ -400,7 +398,6 @@
setup_resource_ranges(domain, type, &ranges);
while ((dev = largest_resource(domain->downstream, &res, type_mask, type))) {
-
if (!res->size)
continue;
@@ -557,7 +554,6 @@
return;
for (child = root->downstream->children; child; child = child->sibling) {
-
if (child->path.type != DEVICE_PATH_DOMAIN)
continue;
diff --git a/src/drivers/efi/efivars.c b/src/drivers/efi/efivars.c
index e7eabf4..a759070 100644
--- a/src/drivers/efi/efivars.c
+++ b/src/drivers/efi/efivars.c
@@ -26,7 +26,6 @@
printk(log_level, "GUID: %08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x",
g->Data1, g->Data2, g->Data3, g->Data4[0], g->Data4[1], g->Data4[2],
g->Data4[3], g->Data4[4], g->Data4[5], g->Data4[6], g->Data4[7]);
-
}
static bool compare_guid(const EFI_GUID *a, const EFI_GUID *b)
@@ -164,7 +163,6 @@
printk(BIOS_SPEW, PREFIX "UEFI FV with size %lld found\n", fw_vol_hdr->FvLength);
return CB_SUCCESS;
-
}
static enum cb_err
diff --git a/src/drivers/i2c/ptn3460/chip.h b/src/drivers/i2c/ptn3460/chip.h
index 0ec26ca..bcc8789 100644
--- a/src/drivers/i2c/ptn3460/chip.h
+++ b/src/drivers/i2c/ptn3460/chip.h
@@ -4,7 +4,6 @@
#define __DRIVERS_I2C_PTN3460_CHIP_H__
struct drivers_i2c_ptn3460_config {
-
};
#endif /* __DRIVERS_I2C_PTN3460_CHIP_H__ */
diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c
index b58fbc8..5973d33 100644
--- a/src/drivers/i2c/tpm/cr50.c
+++ b/src/drivers/i2c/tpm/cr50.c
@@ -446,7 +446,6 @@
printk(BIOS_INFO, "Probing TPM I2C: ");
for (retries = 100; retries > 0; retries--) {
-
rc = cr50_i2c_read(TPM_DID_VID(0), (uint8_t *)did_vid, 4);
/* Exit once DID and VID verified */
diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c
index eb27984..71582c9 100644
--- a/src/drivers/i2c/tpm/tpm.c
+++ b/src/drivers/i2c/tpm/tpm.c
@@ -117,7 +117,6 @@
buffer, len);
if (rc == 0)
break; /* success, break to skip sleep */
-
}
break;
diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c
index 7522df1..8b2d56a 100644
--- a/src/drivers/intel/fsp1_1/hob.c
+++ b/src/drivers/intel/fsp1_1/hob.c
@@ -245,7 +245,6 @@
printk(BIOS_DEBUG, "%p: hob_list_ptr\n", hob_list_ptr);
for (current_hob = hob_list_ptr; !END_OF_HOB_LIST(current_hob);
current_hob = GET_NEXT_HOB(current_hob)) {
-
EFI_HOB_GENERIC_HEADER *current_header_ptr =
(EFI_HOB_GENERIC_HEADER *)current_hob;
diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c
index fd9cdf5..f1e07e4 100644
--- a/src/drivers/smmstore/store.c
+++ b/src/drivers/smmstore/store.c
@@ -97,7 +97,6 @@
static struct region_device rdev;
if (!done) {
-
done = 1;
if (fmap_locate_area_as_rdev_rw(SMMSTORE_REGION, &rdev)) {
diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c
index 8acbbc7..31651d1 100644
--- a/src/ec/starlabs/merlin/ite.c
+++ b/src/ec/starlabs/merlin/ite.c
@@ -48,7 +48,6 @@
if (CONFIG(EC_STARLABS_MIRROR_SUPPORT) &&
(CONFIG(DRIVERS_INTEL_USB4_RETIMER) || get_uint_option("mirror_flag", 0)) &&
(ec_version != CONFIG_EC_STARLABS_MIRROR_VERSION)) {
-
printk(BIOS_ERR, "ITE: EC version 0x%x doesn't match coreboot version 0x%x.\n",
ec_version, CONFIG_EC_STARLABS_MIRROR_VERSION);
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index d93ba01..d7b6126 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -387,7 +387,6 @@
rec->size = ALIGN_UP(sizeof(*rec) + len + 1, LB_ENTRY_ALIGN);
memcpy(rec->string, strings[i].string, len+1);
}
-
}
static void lb_record_version_timestamp(struct lb_header *header)
diff --git a/src/lib/edid.c b/src/lib/edid.c
index 06b9cee..c294a3f 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -1389,7 +1389,6 @@
out->mode_is_supported[j] = 1;
}
}
-
}
printk(BIOS_SPEW, "Standard timings supported:\n");
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index 7badfbc..fda6c62 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -316,7 +316,6 @@
static void bs_walk_state_machine(void)
{
-
while (1) {
struct boot_state *state;
boot_state_t next_id;
diff --git a/src/lib/memrange.c b/src/lib/memrange.c
index 9ae3e3e..316dce6 100644
--- a/src/lib/memrange.c
+++ b/src/lib/memrange.c
@@ -183,7 +183,6 @@
/* The new entry starts after this one. */
if (begin > cur->end)
continue;
-
}
/* Add new entry and merge with neighbors. */
@@ -389,7 +388,6 @@
return NULL;
memranges_each_entry(r, ranges) {
-
if (r->tag != tag)
continue;
diff --git a/src/lib/region_file.c b/src/lib/region_file.c
index f3e66bf..f77b9b0 100644
--- a/src/lib/region_file.c
+++ b/src/lib/region_file.c
@@ -242,7 +242,6 @@
int region_file_data(const struct region_file *f, struct region_device *rdev)
{
-
size_t offset;
size_t size;
diff --git a/src/lib/stack.c b/src/lib/stack.c
index 479ed93..6e563db 100644
--- a/src/lib/stack.c
+++ b/src/lib/stack.c
@@ -57,5 +57,4 @@
}
return 0;
-
}
diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c
index 3c43a74..d1ed7c7 100644
--- a/src/mainboard/intel/adlrvp/gpio.c
+++ b/src/mainboard/intel/adlrvp/gpio.c
@@ -7,7 +7,6 @@
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
-
/* GPIO A0-A6, A9-A10 default function is NF1 for eSPI interface when
eSPI is enabled */
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/hda_verb.c b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/hda_verb.c
index cbe8f0b..9c1759d 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/hda_verb.c
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/hda_verb.c
@@ -3,7 +3,6 @@
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
-
/*
* VerbTable: CFL Display Audio Codec
* Revision ID = 0xFF
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/hda_verb.c b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/hda_verb.c
index cbe8f0b..9c1759d 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/hda_verb.c
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/hda_verb.c
@@ -3,7 +3,6 @@
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
-
/*
* VerbTable: CFL Display Audio Codec
* Revision ID = 0xFF
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c
index 8a2b8f9..6b9b7ec 100644
--- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c
+++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c
@@ -6,7 +6,6 @@
#include <soc/romstage.h>
static const struct mb_cfg ehlcrb_lpddr4x_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
index eab0fe5..6a3ce3e 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
@@ -7,7 +7,6 @@
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
-
/* WWAN_WAKE_N */
PAD_CFG_GPI_SCI(GPP_A10, NONE, DEEP, LEVEL, INVERT),
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c
index bea9cd8..618e74e 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c
@@ -8,7 +8,6 @@
#include <soc/romstage.h>
static const struct mb_cfg jslrvp_ddr4_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},
@@ -51,7 +50,6 @@
};
static const struct mb_cfg jslrvp_lpddr4_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},
diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c
index feccc08..c182bd7 100644
--- a/src/mainboard/intel/kblrvp/ramstage.c
+++ b/src/mainboard/intel/kblrvp/ramstage.c
@@ -48,7 +48,6 @@
/* Port 0 Configuration */
i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_1_ADDR, IO_EXPANDER_P0CONF,
0x00);
-
}
BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, ioexpander_init, NULL);
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h
index 1ec4488..10c8a8f 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h
@@ -6,7 +6,6 @@
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
-
0x8086280B,
0x00000000,
0x00000005,
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h
index 8f2188c..6915638 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h
@@ -6,7 +6,6 @@
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
-
0x8086280B,
0x00000000,
0x00000005,
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h
index c86ecaf..493b187 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h
@@ -6,7 +6,6 @@
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
-
0x8086280B,
0x00000000,
0x00000005,
diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c
index 8674512..8c1407a 100644
--- a/src/mainboard/intel/kunimitsu/spd/spd_util.c
+++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c
@@ -55,7 +55,6 @@
} else {
memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
}
-
}
uintptr_t mainboard_get_spd_data(void)
diff --git a/src/mainboard/intel/mtlrvp/fw_config.c b/src/mainboard/intel/mtlrvp/fw_config.c
index d874228..eac854c 100644
--- a/src/mainboard/intel/mtlrvp/fw_config.c
+++ b/src/mainboard/intel/mtlrvp/fw_config.c
@@ -96,6 +96,5 @@
printk(BIOS_INFO, "Configure GPIOs for SoundWire audio (onboard codec).\n");
gpio_configure_pads(sndw_alc711_enable_pads, ARRAY_SIZE(i2s_enable_pads));
}
-
}
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
index ea05b89..459fdd1 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
@@ -5,7 +5,6 @@
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
-
/* UART0 RX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* UART0 TX */
diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c
index 0e7f88c..81db91e 100644
--- a/src/mainboard/intel/strago/gpio.c
+++ b/src/mainboard/intel/strago/gpio.c
@@ -241,6 +241,5 @@
struct soc_gpio_config *mainboard_get_gpios(void)
{
-
return &gpio_config;
}
diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c
index 22859f6..3070569 100644
--- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c
@@ -48,5 +48,4 @@
bool half_populated = false;
memcfg_init(mupd, mem_config, &spd_info, half_populated);
-
}
diff --git a/src/mainboard/protectli/vault_bsw/gpio.c b/src/mainboard/protectli/vault_bsw/gpio.c
index b748799..59e4421 100644
--- a/src/mainboard/protectli/vault_bsw/gpio.c
+++ b/src/mainboard/protectli/vault_bsw/gpio.c
@@ -232,6 +232,5 @@
struct soc_gpio_config *mainboard_get_gpios(void)
{
-
return &gpio_config;
}
diff --git a/src/mainboard/protectli/vault_cml/gpio.c b/src/mainboard/protectli/vault_cml/gpio.c
index 72faae9..940d3bd 100644
--- a/src/mainboard/protectli/vault_cml/gpio.c
+++ b/src/mainboard/protectli/vault_cml/gpio.c
@@ -7,7 +7,6 @@
/* Pad configuration was generated automatically using intelp2m utility */
static const struct pad_config gpio_table[] = {
-
/* ------- GPIO Community 0 ------- */
/* ------- GPIO Group GPP_A ------- */
diff --git a/src/mainboard/protectli/vault_ehl/gpio.h b/src/mainboard/protectli/vault_ehl/gpio.h
index 8aa1224..2f1c2ec 100644
--- a/src/mainboard/protectli/vault_ehl/gpio.h
+++ b/src/mainboard/protectli/vault_ehl/gpio.h
@@ -15,7 +15,6 @@
/* PAD configuration was generated automatically using intelp2m utility */
static const struct pad_config gpio_table[] = {
-
/* ------- GPIO Community 0 ------- */
/* ------- GPIO Group GPP_B ------- */
diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/gpio.c b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/gpio.c
index 20a89c6..e54f2aa 100644
--- a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/gpio.c
+++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/gpio.c
@@ -5,7 +5,6 @@
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
-
/* Community 0 - GpioGroup GPP_B */
PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c
index b055c4d..8088857 100644
--- a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c
+++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c
@@ -6,7 +6,6 @@
#include <soc/romstage.h>
static const struct mb_cfg fa_ehl_lpddr4x_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c
index 5cfacb8..4b80c66 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c
@@ -7,7 +7,6 @@
EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
more logical grouping. */
static const struct pad_config gpio_table[] = {
-
/* Southwest Community */
/* PCIE_WAKE[0:3]_N */
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c
index 78723c2..483a88c 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c
@@ -7,7 +7,6 @@
EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
more logical grouping. */
static const struct pad_config gpio_table[] = {
-
/* Southwest Community */
/* EXT_WAKE0_1V8# */
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
index e7b9bd0..cfab8ed 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
@@ -7,7 +7,6 @@
EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
more logical grouping. */
static const struct pad_config gpio_table[] = {
-
/* Southwest Community */
/* PCIE_WAKE[0:3]_N */
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c
index 593b2cd..d707b3a 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c
@@ -7,7 +7,6 @@
EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
more logical grouping. */
static const struct pad_config gpio_table[] = {
-
/* Southwest Community */
/* PCIE_WAKE[0:3]_N */
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c
index 5de6973..f97d1a8 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c
@@ -7,7 +7,6 @@
EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
more logical grouping. */
static const struct pad_config gpio_table[] = {
-
/* Southwest Community */
/* PCIE_WAKE[0:3]_N */
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c
index 7b7dad1..a800d30 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c
@@ -6,7 +6,6 @@
#include <soc/romstage.h>
static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c
index 20a89c6..e54f2aa 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c
@@ -5,7 +5,6 @@
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
-
/* Community 0 - GpioGroup GPP_B */
PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/memory.c
index 7b7dad1..a800d30 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/memory.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/memory.c
@@ -6,7 +6,6 @@
#include <soc/romstage.h>
static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c
index cb7b273..66b7f1d 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c
@@ -5,7 +5,6 @@
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
-
/* Community 0 - GpioGroup GPP_B */
PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/memory.c
index 7b7dad1..a800d30 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/memory.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/memory.c
@@ -6,7 +6,6 @@
#include <soc/romstage.h>
static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/memory.c
index f5638d5..a352f7b 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/memory.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/memory.c
@@ -6,7 +6,6 @@
#include <soc/romstage.h>
static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c
index a4ae8a5..a81f88e 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c
@@ -5,7 +5,6 @@
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
-
/* Community 0 - GpioGroup GPP_B */
PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c
index 7b7dad1..a800d30 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c
@@ -6,7 +6,6 @@
#include <soc/romstage.h>
static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 430eeef..1be9421 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -241,7 +241,6 @@
}
if (dev->path.type == DEVICE_PATH_PCI) {
-
if ((dev->upstream->secondary == 0x0) &&
(dev->path.pci.devfn == 0x0))
*root_level = depth;
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 892bfad..444ab16 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -340,7 +340,6 @@
if (value > 2)
die("Bad SPD value\n");
if (value == 2) {
-
pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently
value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
if (value < 0)
@@ -413,14 +412,12 @@
struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address);
if (sz.side1 > 0) {
-
value = smbus_read_byte(dimm_socket_address, SPD_NUM_ROWS);
die_on_spd_error(value);
sz.side1 += value & 0xf;
if (sz.side2 > 0) {
-
// Double-sided DIMM
if (value & 0xF0)
sz.side2 += value >> 4; // Asymmetric
@@ -496,7 +493,6 @@
// since we only support dual-channel.
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
-
uint16_t channel0_dimm = ctrl->channel0[i];
uint16_t channel1_dimm = ctrl->channel1[i];
uint8_t bDualChannel = 1;
@@ -565,7 +561,6 @@
// NOTE: unpopulated DIMMs cause read to fail
spd_value = smbus_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
-
printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
continue;
}
@@ -580,7 +575,6 @@
if (!are_spd_values_equal
(dual_channel_parameters[j], channel0_dimm,
channel1_dimm)) {
-
bDualChannel = 0;
break;
}
@@ -653,7 +647,6 @@
* Seems like rows 4-7 overlap with 0-3.
*/
for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
-
uint8_t dimm_end_64M_multiple = pci_read_config8(MCHDEV, DRB_ROW_0 + i);
if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
@@ -800,7 +793,6 @@
pci_write_config32(MCHDEV, DRB_ROW_4, 0);
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
-
uint16_t dimm_socket_address = ctrl->channel0[i];
struct dimm_size sz;
@@ -1020,7 +1012,6 @@
uint32_t dimm_compatible_cas_latencies;
for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
-
uint16_t dimm_socket_address;
if (!(dimm_mask & (1 << i)))
@@ -1098,7 +1089,6 @@
dram_timing |= DRT_CAS_2_0;
dram_read_timing |= 0x0222;
} else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
-
uint32_t dram_row_attributes =
pci_read_config32(MCHDEV, DRA);
@@ -1111,7 +1101,6 @@
&& (dram_row_attributes & 0xff00)
&& (dram_row_attributes & 0xff0000)
&& (dram_row_attributes & 0xff000000)) {
-
// All slots populated
dram_read_timing |= 0x0882;
} else {
@@ -1179,7 +1168,6 @@
*/
for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
-
uint32_t dimm_refresh_mode;
int value;
uint16_t dimm_socket_address;
@@ -1250,7 +1238,6 @@
uint32_t row_attributes = 0;
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
-
uint16_t dimm_socket_address = ctrl->channel0[i];
struct dimm_size page_size;
struct dimm_size sdram_width;
@@ -1300,7 +1287,6 @@
pci_write_config8(MCHDEV, 0x8e, 0xb0);
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
-
uint8_t socket_mask = 1 << i;
if (dimm_mask & socket_mask)
@@ -1702,7 +1688,6 @@
/* If this is a warm boot, some initialisation can be skipped */
if (!e7505_mch_is_ready()) {
-
/* The real MCH initialisation. */
timestamp_add_now(TS_INITRAM_START);
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 35ec41d..d036399 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -127,5 +127,4 @@
MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
-
}
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index 8d179aa..f3c107b 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -36,7 +36,6 @@
/* VTVC0BAR has to be set, enabled, and in 32-bit space */
if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) {
-
const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR,
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 48a0ba5..9e9f980 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -124,7 +124,6 @@
u32 val;
val = read32(res2mmio(gtt_res, reg, 0));
return val;
-
}
void gtt_write(u32 reg, u32 data)
diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c
index 5cee1b4..204e83b 100644
--- a/src/northbridge/intel/i440bx/memmap.c
+++ b/src/northbridge/intel/i440bx/memmap.c
@@ -59,5 +59,4 @@
top_of_ram = (uintptr_t)cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
MTRR_TYPE_WRBACK);
-
}
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index ec93563..54c1b36 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -755,7 +755,6 @@
/* This is 440BX! We do EDO too! */
if (value == SPD_MEMORY_TYPE_EDO
|| value == SPD_MEMORY_TYPE_SDRAM) {
-
if (value == SPD_MEMORY_TYPE_EDO) {
edo = 1;
} else if (value == SPD_MEMORY_TYPE_SDRAM) {
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index d61949f..eea2028 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -290,7 +290,6 @@
printk(BIOS_DEBUG, "timeout!\n");
else
printk(BIOS_DEBUG, "ok\n");
-
}
static void ich7_setup_dmi_rcrb(void)
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index d99a733..5cbd629 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -537,7 +537,6 @@
vga_sr_write(1, vga_sr_read(1) & ~0x20);
return 0;
-
}
/* compare the header of the vga edid header */
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 2613b81..a37754b 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -49,7 +49,6 @@
return sysinfo->spd_addresses[device];
else
return 0x50 + device;
-
}
static __attribute__((noinline)) void do_ram_command(u32 command)
@@ -226,7 +225,6 @@
/* Write back clears bit 2 */
pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
do_reset = true;
-
}
if (reg8 & (1 << 7)) {
@@ -289,7 +287,6 @@
*/
static void gather_common_timing(struct sys_info *sysinfo, struct timings *saved_timings)
{
-
int i, j;
u8 raw_spd[SPD_SIZE_MAX_DDR2];
u8 dimm_mask = 0;
@@ -2313,7 +2310,6 @@
static void sdram_thermal_management(void)
{
-
mchbar_write8(TCO1, 0);
mchbar_write8(TCO0, 0);
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index 7d497e6..024a263 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -83,7 +83,6 @@
reg32 |= medium;
}
mchbar_write32(RCVENMT, reg32);
-
}
static int normalize(int channel_offset, u8 *mediumcoarse, u8 *fine)
@@ -190,7 +189,6 @@
continue;
break;
-
}
printk(BIOS_DEBUG, "Could not find low strobe\n");
@@ -200,7 +198,6 @@
static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine,
struct sys_info *sysinfo)
{
-
int counter;
u32 rcvenmt;
diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c
index e6bc375..d8c8799 100644
--- a/src/northbridge/intel/ironlake/northbridge.c
+++ b/src/northbridge/intel/ironlake/northbridge.c
@@ -168,7 +168,6 @@
const struct device *const d0f0 = pcidev_on_root(0, 0);
if (d0f0)
pci_update_config32(d0f0, DEVEN, deven_mask, 0);
-
}
static struct device_operations mc_ops = {
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index b84461a..b262097 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -1552,7 +1552,6 @@
rank), 9)
+ (i == 1) * 11; // !!!!
}
-
}
static u32 get_etalon2(int flip, u32 addr)
@@ -2759,7 +2758,6 @@
timings);
totalrank++;
}
-
}
} else {
for (reg_178 = reg178_center - 12;
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 55d7046..967a59f 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -76,7 +76,6 @@
uintptr_t cbmem_top_chipset(void)
{
return ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB);
-
}
void smm_region(uintptr_t *start, size_t *size)
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 085292b..2b59b9e 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -377,7 +377,6 @@
/* Before reusing training data, assert that the CPU has not been replaced */
if (ctrl_cached && cpuid != ctrl_cached->cpu) {
-
/* It is not really worrying on a cold boot, but fatal when resuming from S3 */
printk(s3resume ? BIOS_ALERT : BIOS_NOTICE,
"CPUID %x differs from stored CPUID %x, CPU was replaced!\n",
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 3f5e290..f896541 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -64,7 +64,6 @@
valid_dimms = 0;
FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) {
-
const struct dimm_attr_ddr3_st *dimm = &dimms->dimm[channel][slot];
if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3)
continue;
@@ -1138,7 +1137,6 @@
int lane, i;
for (rcven_delta = -25; rcven_delta <= 25; rcven_delta++) {
-
FOR_ALL_LANES {
ctrl->timings[channel][slotrank].lanes[lane].rcven
= upperA[lane] + rcven_delta + QCLK_PI;
@@ -1358,7 +1356,6 @@
FOR_ALL_LANES {
ctrl->timings[channel][slotrank].lanes[lane].rcven -= QCLK_PI;
upperA[lane] -= QCLK_PI;
-
}
} else if (some_high) {
ctrl->timings[channel][slotrank].roundtrip_latency++;
@@ -1657,7 +1654,6 @@
fill_pattern1(ctrl, channel);
}
FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS {
-
/* Reset read and write WDB pointers */
mchbar_write32(IOSAV_DATA_CTL_ch(channel), 0x10001);
@@ -2501,7 +2497,6 @@
upper[channel][slotrank][lane] =
MIN(rn.end - ctrl->tx_dq_offset[i],
upper[channel][slotrank][lane]);
-
}
}
}
@@ -2621,7 +2616,6 @@
rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits;
for (bank = 0; bank < 8; bank++) {
for (row = 0; row < rowsize; row += 16) {
-
u8 gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD);
const struct iosav_ssq sequence[] = {
/*
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 82e3e82..cad86ba 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -295,7 +295,6 @@
case 800:
pei_data->max_ddr3_freq = 1600;
break;
-
}
/*
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index fbdc27a..ecae91b 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -274,7 +274,6 @@
/* If non-zero, it was set in the devicetree */
if (cfg->max_mem_clock_mhz) {
-
if (cfg->max_mem_clock_mhz >= 1066)
return TCK_1066MHZ;
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index b4366fb..3149074 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -147,7 +147,6 @@
dram_print_spd_ddr2(&decoded_dimm);
if (!(decoded_dimm.width & (0x08 | 0x10))) {
-
printk(BIOS_ERR, "DIMM%d Unsupported width: x%d. Disabling dimm\n",
dimm_idx, s->dimms[dimm_idx].width);
return CB_ERR;
@@ -523,7 +522,6 @@
}
printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, s->dimm_config[chan]);
}
-
}
static void checkreset_ddr2(int boot_path)
diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h
index 6743a10..34d64aa 100644
--- a/src/soc/nvidia/tegra/dc.h
+++ b/src/soc/nvidia/tegra/dc.h
@@ -247,7 +247,6 @@
/* Window A/B/C register 0x500 ~ 0x628 */
struct dc_winc_reg {
-
/* Address 0x500 */
u32 color_palette; /* _WINC_COLOR_PALETTE_0 */
diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c
index de98d65..cc14c2e 100644
--- a/src/soc/nvidia/tegra124/dp.c
+++ b/src/soc/nvidia/tegra124/dp.c
@@ -440,7 +440,6 @@
static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp,
struct tegra_dc_dp_link_config *cfg)
{
-
switch (cfg->link_bw){
case SOR_LINK_SPEED_G1_62:
if (cfg->max_link_bw > SOR_LINK_SPEED_G1_62)
diff --git a/src/soc/nvidia/tegra124/include/soc/sdram_param.h b/src/soc/nvidia/tegra124/include/soc/sdram_param.h
index b19ae5f..8c71d80 100644
--- a/src/soc/nvidia/tegra124/include/soc/sdram_param.h
+++ b/src/soc/nvidia/tegra124/include/soc/sdram_param.h
@@ -51,7 +51,6 @@
* Defines the SDRAM parameter structure
*/
struct sdram_params {
-
/* Specifies the type of memory device */
uint32_t MemoryType;
diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c
index 8246a09..2feea6b 100644
--- a/src/soc/nvidia/tegra124/sor.c
+++ b/src/soc/nvidia/tegra124/sor.c
@@ -722,7 +722,6 @@
tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1);
tegra_dc_sor_set_dp_mode(sor, link_cfg);
-
}
void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor)
diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c
index 249d787..b8238f3 100644
--- a/src/soc/nvidia/tegra210/addressmap.c
+++ b/src/soc/nvidia/tegra210/addressmap.c
@@ -38,7 +38,6 @@
static void carveout_from_regs(uintptr_t *base_mib, size_t *size_mib,
uint32_t bom, uint32_t bom_hi, uint32_t size)
{
-
/* All size regs of carveouts are in MiB. */
if (size == 0)
return;
diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c
index f6f955c..4eb6e62 100644
--- a/src/soc/nvidia/tegra210/dp.c
+++ b/src/soc/nvidia/tegra210/dp.c
@@ -452,7 +452,6 @@
static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp,
struct tegra_dc_dp_link_config *link_cfg)
{
-
switch (link_cfg->link_bw) {
case SOR_LINK_SPEED_G1_62:
if (link_cfg->max_link_bw > SOR_LINK_SPEED_G1_62)
@@ -1457,7 +1456,6 @@
static void tegra_dc_dp_check_sink(struct tegra_dc_dp_data *dp,
struct soc_nvidia_tegra210_config *config)
{
-
u8 max_retry = 3;
int delay_frame;
diff --git a/src/soc/nvidia/tegra210/include/soc/funitcfg.h b/src/soc/nvidia/tegra210/include/soc/funitcfg.h
index 493c9a0..99214f7 100644
--- a/src/soc/nvidia/tegra210/include/soc/funitcfg.h
+++ b/src/soc/nvidia/tegra210/include/soc/funitcfg.h
@@ -30,7 +30,6 @@
* currently the I2C is 0-based and SPI is 1-based in its indexing.
*/
enum {
-
I2C1_BUS = 0,
I2C2_BUS = 1,
I2C3_BUS = 2,
diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_param.h b/src/soc/nvidia/tegra210/include/soc/sdram_param.h
index f9d7c6b..22f3674 100644
--- a/src/soc/nvidia/tegra210/include/soc/sdram_param.h
+++ b/src/soc/nvidia/tegra210/include/soc/sdram_param.h
@@ -54,7 +54,6 @@
* Defines the SDRAM parameter structure
*/
struct sdram_params {
-
/* Specifies the type of memory device */
uint32_t MemoryType;
diff --git a/src/soc/nvidia/tegra210/mipi-phy.c b/src/soc/nvidia/tegra210/mipi-phy.c
index 48a908a..0e5897f 100644
--- a/src/soc/nvidia/tegra210/mipi-phy.c
+++ b/src/soc/nvidia/tegra210/mipi-phy.c
@@ -13,7 +13,6 @@
int mipi_dphy_set_timing(struct tegra_dsi *dsi)
{
-
u32 freq = (dsi->clk_rate * 2) / 1000000;
u32 thsdexit = (DSI_PHY_TIMING_DIV(120, (freq)));
diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c
index 702897f..e00c615 100644
--- a/src/soc/nvidia/tegra210/sdram.c
+++ b/src/soc/nvidia/tegra210/sdram.c
@@ -798,7 +798,6 @@
uint32_t val = 0;
if (param->MemoryType == NvBootMemoryType_LpDdr4) {
-
val = (param->EmcPinGpioEn << EMC_PIN_GPIOEN_SHIFT) |
(param->EmcPinGpio << EMC_PIN_GPIO_SHIFT);
write32(®s->pin, val);
@@ -835,7 +834,6 @@
die("Failed to program EMC pin.");
if (param->MemoryType != NvBootMemoryType_LpDdr4) {
-
/* Send NOP (trigger just needs to be non-zero) */
writebits(((1 << EMC_NOP_CMD_SHIFT) |
(param->EmcDevSelect << EMC_NOP_DEV_SELECTN_SHIFT)),
diff --git a/src/soc/nvidia/tegra210/sor.c b/src/soc/nvidia/tegra210/sor.c
index c24e0d6..9d6f94d2 100644
--- a/src/soc/nvidia/tegra210/sor.c
+++ b/src/soc/nvidia/tegra210/sor.c
@@ -716,7 +716,6 @@
tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1);
tegra_dc_sor_set_dp_mode(sor, link_cfg);
-
}
void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor)
diff --git a/src/soc/samsung/exynos5250/clock_init.c b/src/soc/samsung/exynos5250/clock_init.c
index 1c13466..12fc5c6 100644
--- a/src/soc/samsung/exynos5250/clock_init.c
+++ b/src/soc/samsung/exynos5250/clock_init.c
@@ -411,7 +411,6 @@
clrbits32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK |
CLK_DPHY1_MASK |
CLK_TZASC_DRBXR_MASK);
-
}
void clock_init_dp_clock(void)
diff --git a/src/soc/samsung/exynos5250/dp-reg.c b/src/soc/samsung/exynos5250/dp-reg.c
index b93a9b8..7e5494d 100644
--- a/src/soc/samsung/exynos5250/dp-reg.c
+++ b/src/soc/samsung/exynos5250/dp-reg.c
@@ -115,7 +115,6 @@
/* Power up PLL */
if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-
clrbits32(&base->dp_pll_ctl, DP_PLL_PD);
stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT);
diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c
index a187f6e..e716d58 100644
--- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c
@@ -186,7 +186,6 @@
}
if (mem->gate_leveling_enable) {
-
write32(&exynos_phy0_control->phy_con0, PHY_CON0_RESET_VAL);
write32(&exynos_phy1_control->phy_con0, PHY_CON0_RESET_VAL);
diff --git a/src/soc/samsung/exynos5420/dp.c b/src/soc/samsung/exynos5420/dp.c
index 13a8fef..f28c87d 100644
--- a/src/soc/samsung/exynos5420/dp.c
+++ b/src/soc/samsung/exynos5420/dp.c
@@ -142,7 +142,6 @@
exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
DPCD_TEST_EDID_CHECKSUM_WRITE);
}
-
}
return 0;
@@ -338,7 +337,6 @@
if (ret != EXYNOS_DP_SUCCESS) {
printk(BIOS_ERR, "DP write_to_dpcd failed\n");
return -1;
-
}
return ret;
diff --git a/src/soc/sifive/fu540/ux00ddr.h b/src/soc/sifive/fu540/ux00ddr.h
index aebf91a..ec0ef2c 100644
--- a/src/soc/sifive/fu540/ux00ddr.h
+++ b/src/soc/sifive/fu540/ux00ddr.h
@@ -110,7 +110,6 @@
_REG32(225<<2, ahbregaddr) = 0xFFFFFFFF;
_REG32(208<<2, ahbregaddr) |= (1 << AXI0_ADDRESS_RANGE_ENABLE);
_REG32(208<<2, ahbregaddr) |= (1 << PORT_ADDR_PROTECTION_EN_OFFSET);
-
}
static inline void ux00ddr_disableaxireadinterleave(size_t ahbregaddr) {
diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c
index d5766d8..355e9df 100644
--- a/src/southbridge/intel/common/pciehp.c
+++ b/src/southbridge/intel/common/pciehp.c
@@ -114,5 +114,4 @@
}
acpigen_pop_len();
acpigen_pop_len();
-
}
diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c
index 8b19b7d..1594e68 100644
--- a/src/southbridge/intel/common/smbus.c
+++ b/src/southbridge/intel/common/smbus.c
@@ -320,7 +320,6 @@
host_and_or(base, SMBHSTCTL, 0xff,
SMBHSTCNT_LAST_BYTE);
}
-
}
/* Engine internally completes the transaction
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 93185d4..068062b 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -913,7 +913,6 @@
static int spi_flash_programmer_probe(const struct spi_slave *spi,
struct spi_flash *flash)
{
-
if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
return spi_flash_generic_probe(spi, flash);
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index e78ba42..3477e3a 100644
--- a/src/southbridge/intel/i82371eb/fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
@@ -16,7 +16,6 @@
*/
void acpi_fill_fadt(acpi_fadt_t *fadt)
{
-
fadt->pm1a_evt_blk = DEFAULT_PMBASE;
fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL;
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 2333c76..31aeaf6 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -54,7 +54,6 @@
config->sata_mode = SATA_MODE_IDE_PLAIN;
printk(BIOS_DEBUG, "AHCI not supported, falling back to plain mode.\n");
}
-
}
if (config->sata_mode == SATA_MODE_AHCI) {
diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c
index a374068..e01edf2 100644
--- a/src/southbridge/intel/i82801ix/pcie.c
+++ b/src/southbridge/intel/i82801ix/pcie.c
@@ -52,7 +52,6 @@
/* Enable expresscard hotplug events. */
if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
-
pci_or_config32(dev, 0xd8, 1 << 30);
pci_write_config16(dev, 0x42, 0x142);
}
diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c
index 3ed9d60..0068fb1 100644
--- a/src/southbridge/intel/i82801jx/pcie.c
+++ b/src/southbridge/intel/i82801jx/pcie.c
@@ -52,7 +52,6 @@
/* Enable expresscard hotplug events. */
if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
-
pci_or_config32(dev, 0xd8, 1 << 30);
pci_write_config16(dev, 0x42, 0x142);
}
diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c
index 4ca8010..b04b8e3 100644
--- a/src/southbridge/intel/i82870/pcibridge.c
+++ b/src/southbridge/intel/i82870/pcibridge.c
@@ -20,7 +20,6 @@
pci_write_config32(dev, ACNF, dword);
byte = 0x08;
pci_write_config8(dev, MTT, byte);
-
}
static struct device_operations pcix_ops = {
.read_resources = pci_bus_read_resources,
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 7d31b3e..7f5e1fa 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -231,7 +231,6 @@
rp = root_port_number(dev);
if (!is_rp_enabled(rp)) {
-
/* Configure shared resource clock gating. */
if (rp == 1 || rp == 5 || (rp == 6 && is_lp))
pci_or_config8(dev, 0xe1, 0x3c);
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c
index f78f816..645e5f1 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.c
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c
@@ -142,7 +142,6 @@
static void rl5c476_read_resources(struct device *dev)
{
-
struct resource *resource;
/* For CF socket we need an extra memory window for
@@ -173,7 +172,6 @@
}
pci_dev_set_resources(dev);
-
}
static void rl5c476_set_subsystem(struct device *dev, unsigned int vendor,
diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c
index 55d37af..2257c26 100644
--- a/src/southbridge/ti/pci1x2x/pci1x2x.c
+++ b/src/southbridge/ti/pci1x2x/pci1x2x.c
@@ -10,7 +10,6 @@
static void ti_pci1x2y_init(struct device *dev)
{
-
printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
struct southbridge_ti_pci1x2x_config *conf = dev->chip_info;