| /* SPDX-License-Identifier: GPL-2.0-only */ |
| |
| /* |
| * This file is created based on Intel Alder Lake Processor CPU Datasheet |
| * Document number: 619501 |
| * Chapter number: 14 |
| */ |
| |
| #include <arch/cpu.h> |
| #include <console/console.h> |
| #include <device/pci.h> |
| #include <cpu/x86/lapic.h> |
| #include <cpu/x86/mp.h> |
| #include <cpu/x86/msr.h> |
| #include <cpu/intel/smm_reloc.h> |
| #include <cpu/intel/turbo.h> |
| #include <cpu/intel/common/common.h> |
| #include <fsp/api.h> |
| #include <intelblocks/cpulib.h> |
| #include <intelblocks/mp_init.h> |
| #include <intelblocks/msr.h> |
| #include <romstage_handoff.h> |
| #include <soc/cpu.h> |
| #include <soc/msr.h> |
| #include <soc/pci_devs.h> |
| #include <soc/soc_chip.h> |
| |
| static void soc_fsp_load(void) |
| { |
| fsps_load(romstage_handoff_is_resume()); |
| } |
| |
| static void configure_misc(void) |
| { |
| msr_t msr; |
| |
| config_t *conf = config_of_soc(); |
| |
| msr = rdmsr(IA32_MISC_ENABLE); |
| msr.lo |= (1 << 0); /* Fast String enable */ |
| msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
| wrmsr(IA32_MISC_ENABLE, msr); |
| |
| /* Set EIST status */ |
| cpu_set_eist(conf->eist_enable); |
| |
| /* Disable Thermal interrupts */ |
| msr.lo = 0; |
| msr.hi = 0; |
| wrmsr(IA32_THERM_INTERRUPT, msr); |
| |
| /* Enable package critical interrupt only */ |
| msr.lo = 1 << 4; |
| msr.hi = 0; |
| wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| |
| /* Enable PROCHOT */ |
| msr = rdmsr(MSR_POWER_CTL); |
| msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ |
| msr.lo |= (1 << 23); /* Lock it */ |
| wrmsr(MSR_POWER_CTL, msr); |
| } |
| |
| /* All CPUs including BSP will run the following function. */ |
| void soc_core_init(struct device *cpu) |
| { |
| /* Clear out pending MCEs */ |
| /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| * of these banks are core vs package scope. For now every CPU clears |
| * every bank. */ |
| mca_configure(); |
| |
| /* Enable the local CPU apics */ |
| enable_lapic_tpr(); |
| setup_lapic(); |
| |
| /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| configure_misc(); |
| |
| enable_pm_timer_emulation(); |
| |
| /* Enable Direct Cache Access */ |
| configure_dca_cap(); |
| |
| /* Set energy policy */ |
| set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| |
| /* Enable Turbo */ |
| enable_turbo(); |
| } |
| |
| static void per_cpu_smm_trigger(void) |
| { |
| /* Relocate the SMM handler. */ |
| smm_relocate(); |
| } |
| |
| static void post_mp_init(void) |
| { |
| /* Set Max Ratio */ |
| cpu_set_max_ratio(); |
| |
| /* |
| * Now that all APs have been relocated as well as the BSP let SMIs |
| * start flowing. |
| */ |
| global_smi_enable(); |
| } |
| |
| static const struct mp_ops mp_ops = { |
| /* |
| * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, |
| * that are set prior to ramstage. |
| * Real MTRRs programming are being done after resource allocation. |
| */ |
| .pre_mp_init = soc_fsp_load, |
| .get_cpu_count = get_cpu_count, |
| .get_smm_info = smm_info, |
| .get_microcode_info = get_microcode_info, |
| .pre_mp_smm_init = smm_initialize, |
| .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| .relocation_handler = smm_relocation_handler, |
| .post_mp_init = post_mp_init, |
| }; |
| |
| void soc_init_cpus(struct bus *cpu_bus) |
| { |
| if (mp_init_with_smm(cpu_bus, &mp_ops)) |
| printk(BIOS_ERR, "MP initialization failure.\n"); |
| |
| /* Thermal throttle activation offset */ |
| configure_tcc_thermal_target(); |
| } |