Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
2c423441c054d7a8c93cc814b9db5f8f7185bd0f
/
.
/
src
/
soc
/
intel
/
common
/
block
/
spi
/
Makefile.inc
blob: 1ac4c2175b6377b9d314de7fc80d34d1a319326a [
file
] [
log
] [
blame
]
ifeq
(
$
(
CONFIG_SOC_INTEL_COMMON_BLOCK_SPI
),
y
)
bootblock
-
y
+=
spi
.
c
verstage
-
y
+=
spi
.
c
romstage
-
y
+=
spi
.
c
ramstage
-
y
+=
spi
.
c
postcar
-
y
+=
spi
.
c
smm
-
$
(
CONFIG_SPI_FLASH_SMM
)
+=
spi
.
c
endif