blob: 7bd801a92645fe012c842ce9eaf80f261ed46174 [file] [log] [blame]
Eric Biederman8ca8d762003-04-22 19:02:15 +00001void sdram_no_memory(void)
2{
3 print_err("No memory!!\r\n");
4 while(1) {
5 hlt();
6 }
7}
8
9/* Setup SDRAM */
Eric Biederman548593a2003-07-12 01:46:53 +000010void sdram_initialize(const struct mem_controller *ctrl)
Eric Biederman8ca8d762003-04-22 19:02:15 +000011{
12 print_debug("Ram1\r\n");
13 /* Set the registers we can set once to reasonable values */
Eric Biederman548593a2003-07-12 01:46:53 +000014 sdram_set_registers(ctrl);
Eric Biederman8ca8d762003-04-22 19:02:15 +000015
16 print_debug("Ram2\r\n");
17 /* Now setup those things we can auto detect */
Eric Biederman548593a2003-07-12 01:46:53 +000018 sdram_set_spd_registers(ctrl);
Eric Biederman8ca8d762003-04-22 19:02:15 +000019
20 print_debug("Ram3\r\n");
21 /* Now that everything is setup enable the SDRAM.
22 * Some chipsets do the work for use while on others
23 * we need to it by hand.
24 */
Eric Biederman548593a2003-07-12 01:46:53 +000025 sdram_enable(ctrl);
Eric Biederman8ca8d762003-04-22 19:02:15 +000026
27 print_debug("Ram4\r\n");
Eric Biederman8ca8d762003-04-22 19:02:15 +000028}