| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| |
| config INTEL_DDI |
| bool |
| default n |
| help |
| helper functions for intel DDI operations |
| |
| config INTEL_EDID |
| bool |
| default n |
| |
| config INTEL_INT15 |
| bool |
| default n |
| |
| config INTEL_GMA_ACPI |
| bool |
| default n |
| |
| config INTEL_GMA_SSC_ALTERNATE_REF |
| bool |
| default n |
| help |
| Set when the SSC reference clock for LVDS runs at a different fre- |
| quency than the general display reference clock. |
| |
| To be set by northbridge or mainboard Kconfig. For most platforms, |
| there is no choice, i.e. for i945 and gm45 the SSC reference always |
| differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz |
| DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and newer, it's |
| the same frequency for SSC/non-SSC (120MHz). The only, currently |
| supported platform with a choice seems to be Pineview, where the |
| alternative is 100MHz vs. the default 96MHz. |
| |
| config INTEL_GMA_SWSMISCI |
| bool |
| default n |
| help |
| Select this option for Atom-based platforms which use the SWSMISCI |
| register (0xe0) rather than the SWSCI register (0xe8). |
| |
| config INTEL_GMA_LIBGFXINIT_EDID |
| bool |
| |
| config GFX_GMA_ANALOG_I2C_HDMI_B |
| bool |
| |
| config GFX_GMA_ANALOG_I2C_HDMI_C |
| bool |
| |
| config GFX_GMA_ANALOG_I2C_HDMI_D |
| bool |
| |
| config GFX_GMA |
| def_bool y |
| depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ |
| || NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \ |
| || NORTHBRIDGE_INTEL_HASWELL \ |
| || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ |
| || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \ |
| || SOC_INTEL_WHISKEYLAKE |
| depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID |
| select RAMSTAGE_LIBHWBASE |
| |
| config GFX_GMA_PANEL_1_ON_EDP |
| bool |
| depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT |
| default n if GFX_GMA_PANEL_1_ON_LVDS |
| default y |
| |
| config GFX_GMA_PANEL_1_ON_LVDS |
| bool |
| depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT |
| default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_NEHALEM |
| default n |
| |
| if GFX_GMA |
| |
| config GFX_GMA_DYN_CPU |
| def_bool y |
| help |
| Activates runtime CPU detection in libgfxinit. |
| |
| config GFX_GMA_GENERATION |
| string |
| default "Broxton" if SOC_INTEL_APOLLOLAKE |
| default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \ |
| SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE |
| default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL |
| default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE |
| default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X |
| |
| config GFX_GMA_PANEL_1_PORT |
| string |
| default "eDP" if GFX_GMA_PANEL_1_ON_EDP |
| default "LVDS" |
| |
| config GFX_GMA_PANEL_2_PORT |
| string |
| default "Disabled" |
| |
| config GFX_GMA_ANALOG_I2C_PORT |
| string |
| default "PCH_HDMI_B" if GFX_GMA_ANALOG_I2C_HDMI_B |
| default "PCH_HDMI_C" if GFX_GMA_ANALOG_I2C_HDMI_C |
| default "PCH_HDMI_D" if GFX_GMA_ANALOG_I2C_HDMI_D |
| default "PCH_DAC" |
| help |
| Boards with a DVI-I connector share the I2C pins for both analog and |
| digital displays. In that case, the EDID for a VGA display has to be |
| read over the I2C interface of the coupled digital port. |
| |
| endif |