| chip soc/intel/tigerlake |
| device cpu_cluster 0 on |
| device lapic 0 on end |
| end |
| |
| # GPE configuration |
| # Note that GPE events called out in ASL code rely on this |
| # route, i.e., if this route changes then the affected GPE |
| # offset bits also need to be changed. |
| # DW0 is used by: |
| # - GPP_B3 - TRACKPAD_INT_ODL |
| # - GPP_B4 - H1_AP_INT_ODL |
| # DW1 is used by: |
| # - GPP_D3 - WLAN_PCIE_WAKE_ODL |
| # DW2 is used by: |
| # - GPP_H16 - WWAN_HOST_WAKE |
| # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3. |
| register "pmc_gpe0_dw0" = "GPP_B" |
| register "pmc_gpe0_dw1" = "GPP_D" |
| register "pmc_gpe0_dw2" = "GPP_H" |
| |
| register "SerialIoI2cMode" = "{ |
| [PchSerialIoIndexI2C0] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| }" |
| |
| register "SerialIoGSpiMode" = "{ |
| [PchSerialIoIndexGSPI0] = PchSerialIoPci, |
| [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, |
| [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, |
| }" |
| |
| register "SerialIoGSpiCsMode" = "{ |
| [PchSerialIoIndexGSPI0] = 1, |
| [PchSerialIoIndexGSPI1] = 0, |
| [PchSerialIoIndexGSPI2] = 0, |
| }" |
| |
| register "SerialIoGSpiCsState" = "{ |
| [PchSerialIoIndexGSPI0] = 0, |
| [PchSerialIoIndexGSPI1] = 0, |
| [PchSerialIoIndexGSPI2] = 0, |
| }" |
| |
| register "SerialIoUartMode" = "{ |
| [PchSerialIoIndexUART0] = PchSerialIoDisabled, |
| [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| }" |
| |
| # Intel Common SoC Config |
| #+-------------------+---------------------------+ |
| #| Field | Value | |
| #+-------------------+---------------------------+ |
| #| GSPI0 | cr50 TPM. Early init is | |
| #| | required to set up a BAR | |
| #| | for TPM communication | |
| #| | before memory is up | |
| #+-------------------+---------------------------+ |
| register "common_soc_config" = "{ |
| .gspi[0] = { |
| .speed_mhz = 1, |
| .early_init = 1, |
| }, |
| }" |
| |
| device domain 0 on |
| device pci 00.0 off end # Host Bridge |
| device pci 02.0 off end # Integrated Graphics Device |
| device pci 04.0 off end # SA Thermal device |
| device pci 05.0 off end # IPU |
| device pci 09.0 off end # Intel Trace Hub |
| device pci 12.6 off end # GSPI 2 |
| device pci 14.0 off end # USB xHCI |
| device pci 14.1 off end # USB xDCI (OTG) |
| device pci 14.2 off end # PMC SRAM |
| device pci 14.3 off end # CNVi wifi |
| device pci 14.5 off end # SDCard |
| device pci 15.0 off end # I2C 0 |
| device pci 15.1 off end # I2C 1 |
| device pci 15.2 off end # I2C 2 |
| device pci 15.3 off end # I2C 3 |
| device pci 16.0 off end # HECI 1 |
| device pci 16.1 off end # HECI 2 |
| device pci 16.4 off end # HECI 3 |
| device pci 16.5 off end # HECI 4 |
| device pci 17.0 off end # SATA |
| device pci 19.0 off end # I2C 4 |
| device pci 19.1 off end # I2C 5 |
| device pci 19.2 off end # UART 2 |
| device pci 1a.0 off end # eMMC |
| device pci 1c.0 off end # PCI Express Root Port 1 |
| device pci 1c.1 off end # PCI Express Root Port 2 |
| device pci 1c.2 off end # PCI Express Root Port 3 |
| device pci 1c.3 off end # PCI Express Root Port 4 - WLAN |
| device pci 1c.4 off end # PCI Express Root Port 5 |
| device pci 1c.5 off end # PCI Express Root Port 6 |
| device pci 1c.6 off end # PCI Express Root Port 7 |
| device pci 1c.7 off end # PCI Express Root Port 8 |
| device pci 1e.0 off end # UART 0 |
| device pci 1e.1 off end # UART 1 |
| device pci 1e.2 on |
| chip drivers/spi/acpi |
| register "hid" = "ACPI_DT_NAMESPACE_HID" |
| register "compat_string" = ""google,cr50"" |
| register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)" |
| device spi 0 on end |
| end |
| end # GSPI 0 |
| device pci 1e.3 off end # GSPI 1 |
| device pci 1f.0 on |
| chip ec/google/chromeec |
| device pnp 0c09.0 on end |
| end |
| end # eSPI Interface |
| device pci 1f.1 off end # P2SB |
| device pci 1f.2 off end # Power Management Controller |
| device pci 1f.3 off end # Intel HDA/cAVS |
| device pci 1f.4 off end # SMBus |
| device pci 1f.5 off end # PCH SPI |
| device pci 1f.7 off end # Intel Trace Hub |
| end |
| end |