vboot: Separate vboot from chromeos
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use
of verified boot library without having to stick to CHROMEOS.
BUG=chrome-os-partner:55639
Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15867
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 3f14880..0745679 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -59,13 +59,13 @@
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
- select CHROMEOS_VBNV_CMOS
- select CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH
select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC
select SEPARATE_VERSTAGE
select VBOOT_OPROM_MATTERS
select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
select VBOOT_STARTS_IN_BOOTBLOCK
+ select VBOOT_VBNV_CMOS
+ select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
select VIRTUAL_DEV_SWITCH
config TPM_ON_FAST_SPI
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index cc4de88..5455ded 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -25,7 +25,7 @@
#include <soc/lpc.h>
#include <soc/pci_ids.h>
#include <soc/pm.h>
-#include <vendorcode/google/chromeos/chromeos.h>
+#include <vboot/vbnv.h>
#include "chip.h"
@@ -60,7 +60,7 @@
rtc_fail = !!(ps->gen_pmcon1 & RPS);
/* Ensure the date is set including century byte. */
cmos_check_update_date();
- if (IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS))
+ if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS))
init_vbnv_cmos(rtc_fail);
else
cmos_init(rtc_fail);
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index e23feb2..61aa637 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -27,7 +27,7 @@
#include <soc/pm.h>
#include <device/device.h>
#include <device/pci.h>
-#include <vendorcode/google/chromeos/vboot_common.h>
+#include <vboot/vboot_common.h>
static uintptr_t read_pmc_mmio_bar(void)
{
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 599a95c..d25ddcc 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -30,7 +30,7 @@
#include <soc/ramstage.h>
#include <soc/systemagent.h>
#include <soc/intel/broadwell/chip.h>
-#include <vendorcode/google/chromeos/chromeos.h>
+#include <vboot/vbnv.h>
#define GT_RETRY 1000
#define GT_CDCLK_337 0
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 7e57b23..20fa345 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -44,11 +44,8 @@
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <cpu/cpu.h>
-
-#if IS_ENABLED(CONFIG_CHROMEOS)
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <vendorcode/google/chromeos/vbnv_layout.h>
-#endif
+#include <vboot/vbnv.h>
+#include <vboot/vbnv_layout.h>
static void pch_enable_ioapic(struct device *dev)
{
@@ -175,14 +172,14 @@
enable_alt_smi(config->alt_gp_smi_en);
}
-#if IS_ENABLED(CONFIG_CHROMEOS) && IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
+#if IS_ENABLED(CONFIG_CHROMEOS) && IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)
/*
* Preserve Vboot NV data when clearing CMOS as it will
* have been re-initialized already by Vboot firmware init.
*/
static void pch_cmos_init_preserve(int reset)
{
- uint8_t vbnv[VBNV_BLOCK_SIZE];
+ uint8_t vbnv[VBOOT_VBNV_BLOCK_SIZE];
if (reset)
read_vbnv(vbnv);
@@ -207,7 +204,7 @@
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
}
-#if IS_ENABLED(CONFIG_CHROMEOS) && IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
+#if IS_ENABLED(CONFIG_CHROMEOS) && IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)
pch_cmos_init_preserve(rtc_failed);
#else
cmos_init(rtc_failed);
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 4c055ea..b86d002 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -53,12 +53,12 @@
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
- select CHROMEOS_VBNV_CMOS
- select CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH
select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC
select VBOOT_EC_SLOW_UPDATE
select VBOOT_OPROM_MATTERS
select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
+ select VBOOT_VBNV_CMOS
+ select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
select VIRTUAL_DEV_SWITCH
config BOOTBLOCK_CPU_INIT
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index 4bb597c..209d22c 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -16,6 +16,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <bootmode.h>
#include <chip.h>
#include <console/console.h>
#include <delay.h>
@@ -31,7 +32,7 @@
#include <soc/systemagent.h>
#include <stdlib.h>
#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
+#include <vboot/vbnv.h>
u32 map_oprom_vendev(u32 vendev)
{
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index 6b7a17b..a8ec7b6 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -35,10 +35,8 @@
#include <cpu/x86/smm.h>
#include <soc/pcr.h>
#include <soc/ramstage.h>
-#if IS_ENABLED(CONFIG_CHROMEOS)
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <vendorcode/google/chromeos/vbnv_layout.h>
-#endif
+#include <vboot/vbnv.h>
+#include <vboot/vbnv_layout.h>
static const struct reg_script pch_pmc_misc_init_script[] = {
/* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */
@@ -108,14 +106,14 @@
}
}
-#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
+#if IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)
/*
* Preserve Vboot NV data when clearing CMOS as it will
* have been re-initialized already by Vboot firmware init.
*/
static void pch_cmos_init_preserve(int reset)
{
- uint8_t vbnv[VBNV_BLOCK_SIZE];
+ uint8_t vbnv[VBOOT_VBNV_BLOCK_SIZE];
if (reset)
read_vbnv(vbnv);
@@ -143,7 +141,7 @@
/* Ensure the date is set including century byte. */
cmos_check_update_date();
-#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
+#if IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)
pch_cmos_init_preserve(rtc_failed);
#else
cmos_init(rtc_failed);
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
index 209beeb..cf75ccb 100644
--- a/src/soc/intel/skylake/romstage/power_state.c
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -30,7 +30,7 @@
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
-#include <vendorcode/google/chromeos/vboot_common.h>
+#include <vboot/vboot_common.h>
static struct chipset_power_state power_state CAR_GLOBAL;
diff --git a/src/soc/marvell/bg4cd/Kconfig b/src/soc/marvell/bg4cd/Kconfig
index 2e5b15c..cdd8597 100644
--- a/src/soc/marvell/bg4cd/Kconfig
+++ b/src/soc/marvell/bg4cd/Kconfig
@@ -17,7 +17,7 @@
bool
default n
select ARCH_BOOTBLOCK_ARMV7_M
- select BOOTBLOCK_CUSTOM if VBOOT_VERIFY_FIRMWARE
+ select BOOTBLOCK_CUSTOM if VBOOT
select ARCH_RAMSTAGE_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_VERSTAGE_ARMV7_M
diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc
index 717cb3b..86aa764 100644
--- a/src/soc/marvell/bg4cd/Makefile.inc
+++ b/src/soc/marvell/bg4cd/Makefile.inc
@@ -15,8 +15,8 @@
ifeq ($(CONFIG_SOC_MARVELL_BG4CD),y)
-bootblock-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += bootblock_asm.S
-bootblock-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += bootblock.c
+bootblock-$(CONFIG_VBOOT) += bootblock_asm.S
+bootblock-$(CONFIG_VBOOT) += bootblock.c
bootblock-y += cbmem.c
bootblock-y += i2c.c
diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig
index 605cea2..f738622 100644
--- a/src/soc/qualcomm/ipq40xx/Kconfig
+++ b/src/soc/qualcomm/ipq40xx/Kconfig
@@ -14,9 +14,9 @@
if SOC_QC_IPQ40XX
config CHROMEOS
- select CHROMEOS_VBNV_FLASH
- select SEPARATE_VERSTAGE
select RETURN_FROM_VERSTAGE
+ select SEPARATE_VERSTAGE
+ select VBOOT_VBNV_FLASH
config IPQ_QFN_PART
bool
diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig
index aeb59ff..7ba5df5 100644
--- a/src/soc/qualcomm/ipq806x/Kconfig
+++ b/src/soc/qualcomm/ipq806x/Kconfig
@@ -13,7 +13,7 @@
if SOC_QC_IPQ806X
config CHROMEOS
- select CHROMEOS_VBNV_FLASH
+ select VBOOT_VBNV_FLASH
select SEPARATE_VERSTAGE
select RETURN_FROM_VERSTAGE