| # SPDX-License-Identifier: GPL-2.0-only |
| |
| config SOC_AMD_CEZANNE |
| bool |
| help |
| AMD Cezanne support |
| |
| if SOC_AMD_CEZANNE |
| |
| config SOC_SPECIFIC_OPTIONS |
| def_bool y |
| select ACPI_SOC_NVS |
| select ARCH_BOOTBLOCK_X86_32 |
| select ARCH_VERSTAGE_X86_32 |
| select ARCH_ROMSTAGE_X86_32 |
| select ARCH_RAMSTAGE_X86_32 |
| select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
| select FSP_COMPRESS_FSP_M_LZMA |
| select FSP_COMPRESS_FSP_S_LZMA |
| select HAVE_ACPI_TABLES |
| select HAVE_CF9_RESET |
| select HAVE_SMI_HANDLER |
| select IDT_IN_EVERY_STAGE |
| select IOAPIC |
| select PARALLEL_MP |
| select PARALLEL_MP_AP_WORK |
| select PLATFORM_USES_FSP2_0 |
| select RESET_VECTOR_IN_RAM |
| select RTC |
| select SOC_AMD_COMMON |
| select SOC_AMD_COMMON_BLOCK_ACPI |
| select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
| select SOC_AMD_COMMON_BLOCK_AOAC |
| select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
| select SOC_AMD_COMMON_BLOCK_DATA_FABRIC |
| select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
| select SOC_AMD_COMMON_BLOCK_LPC |
| select SOC_AMD_COMMON_BLOCK_NONCAR |
| select SOC_AMD_COMMON_BLOCK_PCI |
| select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
| select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
| select SOC_AMD_COMMON_BLOCK_SMBUS |
| select SOC_AMD_COMMON_BLOCK_SMI |
| select SOC_AMD_COMMON_BLOCK_SMM |
| select SOC_AMD_COMMON_BLOCK_SPI |
| select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H |
| select SOC_AMD_COMMON_BLOCK_UART |
| select SOC_AMD_COMMON_BLOCK_UCODE |
| select SSE2 |
| select UDK_2017_BINDING |
| select X86_AMD_FIXED_MTRRS |
| select X86_AMD_INIT_SIPI |
| |
| config SOC_AMD_COMMON_BLOCK_UCODE_SIZE |
| default 5568 |
| |
| config CHIPSET_DEVICETREE |
| string |
| default "soc/amd/cezanne/chipset.cb" |
| |
| config EARLY_RESERVED_DRAM_BASE |
| hex |
| default 0x2000000 |
| help |
| This variable defines the base address of the DRAM which is reserved |
| for usage by coreboot in early stages (i.e. before ramstage is up). |
| This memory gets reserved in BIOS tables to ensure that the OS does |
| not use it, thus preventing corruption of OS memory in case of S3 |
| resume. |
| |
| config EARLYRAM_BSP_STACK_SIZE |
| hex |
| default 0x1000 |
| |
| config PSP_APOB_DRAM_ADDRESS |
| hex |
| default 0x2001000 |
| help |
| Location in DRAM where the PSP will copy the AGESA PSP Output |
| Block. |
| |
| config PRERAM_CBMEM_CONSOLE_SIZE |
| hex |
| default 0x1600 |
| help |
| Increase this value if preram cbmem console is getting truncated |
| |
| config C_ENV_BOOTBLOCK_SIZE |
| hex |
| default 0x10000 |
| help |
| Sets the size of the bootblock stage that should be loaded in DRAM. |
| This variable controls the DRAM allocation size in linker script |
| for bootblock stage. |
| |
| config ROMSTAGE_ADDR |
| hex |
| default 0x2040000 |
| help |
| Sets the address in DRAM where romstage should be loaded. |
| |
| config ROMSTAGE_SIZE |
| hex |
| default 0x80000 |
| help |
| Sets the size of DRAM allocation for romstage in linker script. |
| |
| config FSP_M_ADDR |
| hex |
| default 0x20C0000 |
| help |
| Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| performs relocation of FSP-M to this address. |
| |
| config FSP_M_SIZE |
| hex |
| default 0x80000 |
| help |
| Sets the size of DRAM allocation for FSP-M in linker script. |
| |
| config FSP_TEMP_RAM_SIZE |
| hex |
| default 0x40000 |
| help |
| The amount of coreboot-allocated heap and stack usage by the FSP. |
| |
| config VERSTAGE_ADDR |
| hex |
| depends on VBOOT_SEPARATE_VERSTAGE |
| default 0x2140000 |
| help |
| Sets the address in DRAM where verstage should be loaded if running |
| as a separate stage on x86. |
| |
| config VERSTAGE_SIZE |
| hex |
| depends on VBOOT_SEPARATE_VERSTAGE |
| default 0x80000 |
| help |
| Sets the size of DRAM allocation for verstage in linker script if |
| running as a separate stage on x86. |
| |
| config RAMBASE |
| hex |
| default 0x10000000 |
| |
| config RO_REGION_ONLY |
| string |
| depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A |
| default "apu/amdfw" |
| |
| config CPU_ADDR_BITS |
| int |
| default 48 |
| |
| config MMCONF_BASE_ADDRESS |
| default 0xF8000000 |
| |
| config MMCONF_BUS_NUMBER |
| default 64 |
| |
| config MAX_CPUS |
| int |
| default 16 |
| |
| config CONSOLE_UART_BASE_ADDRESS |
| depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| hex |
| default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| |
| config SMM_TSEG_SIZE |
| hex |
| default 0x800000 if HAVE_SMI_HANDLER |
| default 0x0 |
| |
| config SMM_RESERVED_SIZE |
| hex |
| default 0x180000 |
| |
| config SMM_MODULE_STACK_SIZE |
| hex |
| default 0x800 |
| |
| menu "PSP Configuration Options" |
| |
| config AMD_FWM_POSITION_INDEX |
| int "Firmware Directory Table location (0 to 5)" |
| range 0 5 |
| default 0 if BOARD_ROMSIZE_KB_512 |
| default 1 if BOARD_ROMSIZE_KB_1024 |
| default 2 if BOARD_ROMSIZE_KB_2048 |
| default 3 if BOARD_ROMSIZE_KB_4096 |
| default 4 if BOARD_ROMSIZE_KB_8192 |
| default 5 if BOARD_ROMSIZE_KB_16384 |
| help |
| Typically this is calculated by the ROM size, but there may |
| be situations where you want to put the firmware directory |
| table in a different location. |
| 0: 512 KB - 0xFFFA0000 |
| 1: 1 MB - 0xFFF20000 |
| 2: 2 MB - 0xFFE20000 |
| 3: 4 MB - 0xFFC20000 |
| 4: 8 MB - 0xFF820000 |
| 5: 16 MB - 0xFF020000 |
| |
| comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 0 |
| comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 1 |
| comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 2 |
| comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 3 |
| comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 4 |
| comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 5 |
| |
| config AMDFW_CONFIG_FILE |
| string |
| default "src/soc/amd/cezanne/fw.cfg" |
| |
| config PSP_LOAD_MP2_FW |
| bool |
| default n |
| help |
| Include the MP2 firmwares and configuration into the PSP build. |
| |
| If unsure, answer 'n' |
| |
| config PSP_UNLOCK_SECURE_DEBUG |
| bool "Unlock secure debug" |
| default y |
| help |
| Select this item to enable secure debug options in PSP. |
| |
| endmenu |
| |
| endif # SOC_AMD_CEZANNE |