sb/intel/common: Rename TCO timeout
Rename TCO1_TIMEOUT to TCO_TIMEOUT to match rest of the tree.
Change-Id: Ib136e9b2d0006eb4ceceb298b557644760d1185c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 3aef48a..8155479 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -466,7 +466,7 @@
#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
#define TCO1_STS 0x64
-#define TCO1_TIMEOUT (1 << 3)
+#define TCO_TIMEOUT (1 << 3)
#define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66
#define TCO2_STS_SECOND_TO (1 << 1)
diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h
index 168971e..5bf386f 100644
--- a/src/southbridge/intel/common/tco.h
+++ b/src/southbridge/intel/common/tco.h
@@ -13,7 +13,7 @@
#define PMBASE_TCO_OFFSET 0x60
#define TCO1_STS 0x04
-#define TCO1_TIMEOUT (1 << 3)
+#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
#define TCO2_STS_SECOND_TO (1 << 1)
#define TCO1_CNT 0x08
diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c
index a988691..e22dbfb 100644
--- a/src/southbridge/intel/common/watchdog.c
+++ b/src/southbridge/intel/common/watchdog.c
@@ -32,7 +32,7 @@
write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value);
/* Clear TCO timeout status. */
- write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT);
+ write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO_TIMEOUT);
write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO);
printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n");