| /* SPDX-License-Identifier: GPL-2.0-only */ |
| |
| #include <soc/dramc_ac_timing.h> |
| #include <soc/dramc_pi_api.h> |
| #include <soc/dramc_register.h> |
| #include <soc/gpio.h> |
| #include <string.h> |
| #include <timer.h> |
| |
| static const u8 mrr_o1_pinmux_mapping[PINMUX_MAX][CHANNEL_MAX][DQ_DATA_WIDTH] = { |
| [PINMUX_DSC] = { |
| [CHANNEL_A] = {0, 1, 7, 6, 4, 5, 2, 3, 9, 8, 11, 10, 14, 15, 13, 12}, |
| [CHANNEL_B] = {1, 0, 5, 6, 3, 2, 7, 4, 8, 9, 11, 10, 12, 14, 13, 15}, |
| }, |
| [PINMUX_LPBK] = { |
| }, |
| [PINMUX_EMCP] = { |
| [CHANNEL_A] = {1, 0, 3, 2, 4, 7, 6, 5, 8, 9, 10, 14, 11, 15, 13, 12}, |
| [CHANNEL_B] = {0, 1, 4, 7, 3, 5, 6, 2, 9, 8, 10, 12, 11, 14, 13, 15} |
| }, |
| }; |
| |
| static void set_rank_info_to_conf(const struct ddr_cali *cali) |
| { |
| u8 value = ((cali->emi_config->cona_val >> 17) & 0x1) ? 0 : 1; |
| |
| SET32_BITFIELDS(&ch[0].ao.sa_reserve, |
| SA_RESERVE_MODE_RK0, cali->cbt_mode[RANK_0], |
| SA_RESERVE_MODE_RK1, cali->cbt_mode[RANK_1], |
| SA_RESERVE_SINGLE_RANK, value); |
| } |
| |
| static void get_dram_pinmux_sel(struct ddr_cali *cali) |
| { |
| u32 value = (read32(&mtk_gpio->dram_pinmux_trapping) >> 19) & 0x1; |
| |
| if (value) |
| cali->pinmux_type = PINMUX_DSC; |
| else |
| cali->pinmux_type = PINMUX_EMCP; |
| } |
| |
| static void set_mrr_pinmux_mapping(const struct ddr_cali *cali) |
| { |
| const u8 *map; |
| u32 bc_bak = dramc_get_broadcast(); |
| |
| dramc_set_broadcast(DRAMC_BROADCAST_OFF); |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| map = mrr_o1_pinmux_mapping[get_pinmux_type(cali)][chn]; |
| SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux1, |
| MRR_BIT_MUX1_MRR_BIT0_SEL, map[0], |
| MRR_BIT_MUX1_MRR_BIT1_SEL, map[1], |
| MRR_BIT_MUX1_MRR_BIT2_SEL, map[2], |
| MRR_BIT_MUX1_MRR_BIT3_SEL, map[3]); |
| SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux2, |
| MRR_BIT_MUX2_MRR_BIT4_SEL, map[4], |
| MRR_BIT_MUX2_MRR_BIT5_SEL, map[5], |
| MRR_BIT_MUX2_MRR_BIT6_SEL, map[6], |
| MRR_BIT_MUX2_MRR_BIT7_SEL, map[7]); |
| SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux3, |
| MRR_BIT_MUX3_MRR_BIT8_SEL, map[8], |
| MRR_BIT_MUX3_MRR_BIT9_SEL, map[9], |
| MRR_BIT_MUX3_MRR_BIT10_SEL, map[10], |
| MRR_BIT_MUX3_MRR_BIT11_SEL, map[11]); |
| SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux4, |
| MRR_BIT_MUX4_MRR_BIT12_SEL, map[12], |
| MRR_BIT_MUX4_MRR_BIT13_SEL, map[13], |
| MRR_BIT_MUX4_MRR_BIT14_SEL, map[14], |
| MRR_BIT_MUX4_MRR_BIT15_SEL, map[15]); |
| } |
| dramc_set_broadcast(bc_bak); |
| } |
| |
| static void set_dqo1_pinmux_mapping(const struct ddr_cali *cali) |
| { |
| const u8 *map; |
| u32 bc_bak = dramc_get_broadcast(); |
| |
| dramc_set_broadcast(DRAMC_BROADCAST_OFF); |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| map = mrr_o1_pinmux_mapping[get_pinmux_type(cali)][chn]; |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_dq_se_pinmux_ctrl0, |
| MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0, map[0], |
| MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1, map[1], |
| MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2, map[2], |
| MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3, map[3], |
| MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4, map[4], |
| MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5, map[5], |
| MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6, map[6], |
| MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7, map[7]); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_dq_se_pinmux_ctrl1, |
| MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8, map[8], |
| MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9, map[9], |
| MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10, map[10], |
| MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11, map[11], |
| MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12, map[12], |
| MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13, map[13], |
| MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14, map[14], |
| MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15, map[15]); |
| } |
| |
| dramc_set_broadcast(bc_bak); |
| } |
| |
| void global_option_init(struct ddr_cali *cali) |
| { |
| set_rank_info_to_conf(cali); |
| get_dram_pinmux_sel(cali); |
| set_mrr_pinmux_mapping(cali); |
| set_dqo1_pinmux_mapping(cali); |
| } |
| |
| static void dramc_init_default_mr_value(const struct ddr_cali *cali) |
| { |
| struct mr_values *mr_value = cali->mr_value; |
| dram_freq_grp freq_group = cali->freq_group; |
| u8 highest_freq = get_highest_freq_group(); |
| |
| mr_value->mr01[FSP_0] = 0x26; |
| mr_value->mr01[FSP_1] = 0x56; |
| mr_value->mr02[FSP_0] = 0x1a; |
| mr_value->mr02[FSP_1] = 0x1a; |
| |
| mr_value->mr03[FSP_0] = 0x30 | 0x4; |
| mr_value->mr03[FSP_1] = 0x30 | 0x4 | 0x2; |
| |
| mr_value->mr04[RANK_0] = 0x3; |
| mr_value->mr04[RANK_1] = 0x3; |
| |
| mr_value->mr21[FSP_0] = 0x0; |
| mr_value->mr21[FSP_1] = 0x0; |
| mr_value->mr51[FSP_0] = 0x0; |
| mr_value->mr51[FSP_1] = 0x0; |
| |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) |
| for (u8 rk = 0; rk < RANK_MAX; rk++) { |
| mr_value->mr23[chn][rk] = 0x3f; |
| for (u8 fsp = 0; fsp < FSP_MAX; fsp++) { |
| mr_value->mr14[chn][rk][fsp] = (fsp == FSP_0) ? 0x5d : 0x18; |
| mr_value->mr12[chn][rk][fsp] = (fsp == FSP_0) ? 0x5d : 0x1b; |
| } |
| } |
| |
| mr_value->mr01[FSP_0] &= 0x8F; |
| mr_value->mr01[FSP_1] &= 0x8F; |
| |
| if (highest_freq == DDRFREQ_2133) { |
| mr_value->mr01[FSP_0] |= (0x7 << 4); |
| mr_value->mr01[FSP_1] |= (0x7 << 4); |
| } else { |
| mr_value->mr01[FSP_0] |= (0x5 << 4); |
| mr_value->mr01[FSP_1] |= (0x5 << 4); |
| } |
| |
| switch (freq_group) { |
| case DDRFREQ_400: |
| mr_value->mr02[FSP_0] = 0x12; |
| break; |
| case DDRFREQ_600: |
| case DDRFREQ_800: |
| mr_value->mr02[FSP_0] = 0x12; |
| break; |
| case DDRFREQ_933: |
| mr_value->mr02[FSP_0] = 0x1b; |
| break; |
| case DDRFREQ_1200: |
| mr_value->mr02[FSP_0] = 0x24; |
| break; |
| case DDRFREQ_1600: |
| mr_value->mr02[FSP_1] = 0x2d; |
| break; |
| case DDRFREQ_2133: |
| mr_value->mr02[FSP_1] = 0x3f; |
| break; |
| default: |
| die("Invalid DDR frequency group %u\n", freq_group); |
| return; |
| } |
| } |
| |
| static void sv_algorithm_assistance_lp4_800(void) |
| { |
| SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track, |
| SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x0e, |
| SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1, |
| SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0, |
| SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xff5, |
| SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x00b); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat, |
| MISC_SHU_RDAT_DATLAT, 0x0e, |
| MISC_SHU_RDAT_DATLAT_DSEL, 0x0e, |
| MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x0e); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, |
| MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1, |
| MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x1, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x0, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x0, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl, |
| MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x3, |
| MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1, |
| MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1, |
| MISC_SHU_RANKCTL_RANKINCTL_STB, 0x4, |
| MISC_SHU_RANKCTL_RANKINCTL, 0x4, |
| MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x4, |
| MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x6); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x4, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x4, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x4); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, |
| MISC_SHU_RK_DQSCTL_DQSINCTL, 0x6); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, |
| MISC_SHU_RK_DQSCTL_DQSINCTL, 0x6); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x6, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x8, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x0b); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x7, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x9, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x1f); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x6, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x8, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x0b); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x7, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x9, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x1f); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, |
| MISC_SHU_ODTCTRL_RODTEN, 0x1, |
| MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0, |
| MISC_SHU_ODTCTRL_RODT_LAT, 0x4, |
| MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0, |
| MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0, |
| MISC_SHU_ODTCTRL_FIXRODT, 0x0, |
| MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1, |
| MISC_SHU_ODTCTRL_RODTE2, 0x1, |
| MISC_SHU_ODTCTRL_RODTE, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, |
| SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0, |
| SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0, |
| SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, |
| SHU_B0_DQ7_R_DMRODTEN_B0, 0x1, |
| SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0, |
| SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0, |
| SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0, |
| SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0, |
| SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0, |
| SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1, |
| SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x1, |
| SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1, |
| SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, |
| SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0, |
| SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0, |
| SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, |
| SHU_B1_DQ7_R_DMRODTEN_B1, 0x1, |
| SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0, |
| SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0, |
| SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0, |
| SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0, |
| SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0, |
| SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1, |
| SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x1, |
| SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1, |
| SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl, |
| SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x1, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x1, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x2, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x2, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x1, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x1, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x2, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x2, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0, |
| SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0, |
| SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0, |
| SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x1, |
| SHU_RX_CG_SET0_READ_START_EXTEND2, 0x1, |
| SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1, |
| SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x5, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi, |
| SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x0b, |
| SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x06); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi, |
| SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x0b, |
| SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x06); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi, |
| SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x1f, |
| SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x07); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi, |
| SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x1f, |
| SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x07); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x0b, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x06, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x08); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x0b, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x06, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x08); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x1f, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x07, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x09); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x1f, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x07, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x09); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x18, |
| SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x18, |
| SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, |
| SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, |
| SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x18, |
| SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x18, |
| SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, |
| SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, |
| SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x18, |
| SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x18, |
| SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, |
| SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, |
| SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x18, |
| SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x18, |
| SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, |
| SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, |
| SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0, |
| SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1, |
| SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3, |
| SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x6, |
| SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2, |
| SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x5, |
| SHU_DCM_CTRL0_FASTWAKE2, 0x0, |
| SHU_DCM_CTRL0_FASTWAKE, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl, |
| SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3, |
| SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x0, |
| SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x3, |
| SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2, |
| SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x0, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x0, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl, |
| SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x2, |
| SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x2, |
| SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0, |
| SHU_SELPH_DQS0_TXDLY_DQS0, 0x4, |
| SHU_SELPH_DQS0_TXDLY_DQS1, 0x4, |
| SHU_SELPH_DQS0_TXDLY_DQS2, 0x1, |
| SHU_SELPH_DQS0_TXDLY_DQS3, 0x1, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x3, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x3, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0, |
| SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x3, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x3, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1, |
| SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x3, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x3, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2, |
| SHURK_SELPH_DQ2_DLY_DQ0, 0x1, |
| SHURK_SELPH_DQ2_DLY_DQ1, 0x1, |
| SHURK_SELPH_DQ2_DLY_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_DQ3, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x2, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x2, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3, |
| SHURK_SELPH_DQ3_DLY_DQM0, 0x1, |
| SHURK_SELPH_DQ3_DLY_DQM1, 0x1, |
| SHURK_SELPH_DQ3_DLY_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_DQM3, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x2, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x2, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0, |
| SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x3, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x3, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1, |
| SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x3, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x3, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2, |
| SHURK_SELPH_DQ2_DLY_DQ0, 0x1, |
| SHURK_SELPH_DQ2_DLY_DQ1, 0x1, |
| SHURK_SELPH_DQ2_DLY_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_DQ3, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x2, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x2, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3, |
| SHURK_SELPH_DQ3_DLY_DQM0, 0x1, |
| SHURK_SELPH_DQ3_DLY_DQM1, 0x1, |
| SHURK_SELPH_DQ3_DLY_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_DQM3, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x2, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x2, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x018, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x018); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x018, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x018); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x018, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x018); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x018, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x018); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x018, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x018); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x018, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x018); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi, |
| SHURK_PI_RK0_ARPI_DQ_B1, 0x18, |
| SHURK_PI_RK0_ARPI_DQ_B0, 0x18, |
| SHURK_PI_RK0_ARPI_DQM_B1, 0x18, |
| SHURK_PI_RK0_ARPI_DQM_B0, 0x18); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi, |
| SHURK_PI_RK0_ARPI_DQ_B1, 0x18, |
| SHURK_PI_RK0_ARPI_DQ_B0, 0x18, |
| SHURK_PI_RK0_ARPI_DQM_B1, 0x18, |
| SHURK_PI_RK0_ARPI_DQM_B0, 0x18); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0, |
| SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x30, |
| SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x30, |
| SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x30, |
| SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x30); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1, |
| SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x30, |
| SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x30, |
| SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x30, |
| SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x30); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3, |
| SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x30, |
| SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, |
| SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly0, |
| SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x0c, |
| SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x0c, |
| SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x0c, |
| SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x0c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly1, |
| SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x0c, |
| SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x0c, |
| SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x0c, |
| SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x0c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly3, |
| SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x0c, |
| SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, |
| SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly0, |
| SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x10, |
| SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x10, |
| SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x10, |
| SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x10); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly1, |
| SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x10, |
| SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x10, |
| SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x10, |
| SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x10); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly3, |
| SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x10, |
| SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, |
| SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0, |
| SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x20, |
| SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x20, |
| SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x20, |
| SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x20); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1, |
| SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x20, |
| SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x20, |
| SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x20, |
| SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x20); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3, |
| SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x20, |
| SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, |
| SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_tx_rankctl, |
| SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 0x1, |
| SHU_TX_RANKCTL_TXRANKINCTL, 0x1, |
| SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0, |
| SHU_AC_DERATING0_ACDERATEEN, 0x1, |
| SHU_AC_DERATING0_TRRD_DERATE, 0x2, |
| SHU_AC_DERATING0_TRCD_DERATE, 0x4); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1, |
| SHU_AC_DERATING1_TRPAB_DERATE, 0x3, |
| SHU_AC_DERATING1_TRP_DERATE, 0x2, |
| SHU_AC_DERATING1_TRAS_DERATE, 0x01, |
| SHU_AC_DERATING1_TRC_DERATE, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl, |
| SHU_SREF_CTRL_CKEHCMD, 0x3, |
| SHU_SREF_CTRL_SREF_CK_DLY, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0, |
| SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x32, |
| SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt, |
| SHU_ACTIM_XRT_XRTR2R, 0x05, |
| SHU_ACTIM_XRT_XRTR2W, 0x0a, |
| SHU_ACTIM_XRT_XRTW2R, 0x6, |
| SHU_ACTIM_XRT_XRTW2W, 0x09); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim0, |
| SHU_ACTIM0_TWTR, 0x0a, |
| SHU_ACTIM0_TWR, 0x0c, |
| SHU_ACTIM0_TRRD, 0x1, |
| SHU_ACTIM0_TRCD, 0x4, |
| SHU_ACTIM0_CKELCKCNT, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim1, |
| SHU_ACTIM1_TRPAB, 0x3, |
| SHU_ACTIM1_TMRWCKEL, 0x7, |
| SHU_ACTIM1_TRP, 0x2, |
| SHU_ACTIM1_TRAS, 0x01, |
| SHU_ACTIM1_TRC, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim2, |
| SHU_ACTIM2_TXP, 0x0, |
| SHU_ACTIM2_TMRRI, 0x07, |
| SHU_ACTIM2_TRTP, 0x3, |
| SHU_ACTIM2_TR2W, 0x0a, |
| SHU_ACTIM2_TFAW, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim3, |
| SHU_ACTIM3_TRFCPB, 0x1a, |
| SHU_ACTIM3_MANTMRR, 0x8, |
| SHU_ACTIM3_TR2MRR, 0x8, |
| SHU_ACTIM3_TRFC, 0x40, |
| SHU_ACTIM3_TWTR_L, 0x25); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim4, |
| SHU_ACTIM4_TXREFCNT, 0x04e, |
| SHU_ACTIM4_TMRR2MRW, 0x0f, |
| SHU_ACTIM4_TMRR2W, 0x0c, |
| SHU_ACTIM4_TZQCS, 0x10); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim5, |
| SHU_ACTIM5_TR2PD, 0x10, |
| SHU_ACTIM5_TWTPD, 0x0f, |
| SHU_ACTIM5_TPBR2PBR, 0x15, |
| SHU_ACTIM5_TPBR2ACT, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim6, |
| SHU_ACTIM6_TZQLAT2, 0x06, |
| SHU_ACTIM6_TMRD, 0x6, |
| SHU_ACTIM6_TMRW, 0x5, |
| SHU_ACTIM6_TW2MRW, 0x0d, |
| SHU_ACTIM6_TR2MRW, 0x11); |
| SET32_BITFIELDS(&ch[0].ao.shu_ckectrl, |
| SHU_CKECTRL_TPDE_05T, 0x0, |
| SHU_CKECTRL_TPDX_05T, 0x0, |
| SHU_CKECTRL_TPDE, 0x3, |
| SHU_CKECTRL_TPDX, 0x3, |
| SHU_CKECTRL_TCKEPRD, 0x2, |
| SHU_CKECTRL_TCKESRX, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_misc, |
| SHU_MISC_REQQUE_MAXCNT, 0x2, |
| SHU_MISC_DCMDLYREF, 0x7, |
| SHU_MISC_DAREFEN, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8, |
| SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x0031, |
| SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0, |
| SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1, |
| SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1, |
| SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8, |
| SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x0031, |
| SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0, |
| SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1, |
| SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1, |
| SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5, |
| SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e, |
| SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0, |
| SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00, |
| SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0, |
| SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0, |
| SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x7, |
| SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5, |
| SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e, |
| SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0, |
| SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00, |
| SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0, |
| SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0, |
| SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x7, |
| SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x75, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x75, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x75, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x75); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x75, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x75, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x75, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x75); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x75, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x75, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x75, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x75); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x75, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x75, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x75, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x75); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x75, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x75); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x17e, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x17e); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x74, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x74, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x74, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x74); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x74, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x74, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x74, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x74); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x74, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x74, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x74, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x74); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x74, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x74, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x74, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x74); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x74, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x74); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x17d, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x17d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x75, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x75, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x75, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x75); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x75, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x75, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x75, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x75); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x75, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x75, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x75, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x75); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x75, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x75, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x75, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x75); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x75, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x75); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x17e, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x17e); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x74, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x74, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x74, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x74); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x74, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x74, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x74, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x74); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x74, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x74, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x74, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x74); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x74, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x74, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x74, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x74); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x74, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x74); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x17d, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x17d); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, |
| B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1, |
| B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0, |
| B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0, |
| B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1, |
| B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0, |
| B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00, |
| B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0, |
| B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0, |
| B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0, |
| B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, |
| B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1, |
| B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0, |
| B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0, |
| B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1, |
| B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0, |
| B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00, |
| B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0, |
| B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0, |
| B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0, |
| B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4, |
| B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x03, |
| B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x03, |
| B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x35, |
| B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x35); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4, |
| B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x03, |
| B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x03, |
| B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x35, |
| B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x35); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, |
| B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e, |
| B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1, |
| B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, |
| B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e, |
| B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1, |
| B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0); |
| } |
| |
| static void sv_algorithm_assistance_lp4_1600(void) |
| { |
| SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track, |
| SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x09, |
| SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1, |
| SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0, |
| SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xfeb, |
| SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x015); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat, |
| MISC_SHU_RDAT_DATLAT, 0x09, |
| MISC_SHU_RDAT_DATLAT_DSEL, 0x09, |
| MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x09); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, |
| MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1, |
| MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x2, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x0, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x0, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl, |
| MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x0, |
| MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1, |
| MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1, |
| MISC_SHU_RANKCTL_RANKINCTL_STB, 0x1, |
| MISC_SHU_RANKCTL_RANKINCTL, 0x0, |
| MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x0, |
| MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x3); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x2, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x2, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x2); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, |
| MISC_SHU_RK_DQSCTL_DQSINCTL, 0x2); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, |
| MISC_SHU_RK_DQSCTL_DQSINCTL, 0x2); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x9, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0xd, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x0b); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0xc, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x0, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x11); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x9, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0xd, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x0b); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0xc, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x0, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x11); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, |
| MISC_SHU_ODTCTRL_RODTEN, 0x1, |
| MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0, |
| MISC_SHU_ODTCTRL_RODT_LAT, 0x1, |
| MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0, |
| MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0, |
| MISC_SHU_ODTCTRL_FIXRODT, 0x0, |
| MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1, |
| MISC_SHU_ODTCTRL_RODTE2, 0x1, |
| MISC_SHU_ODTCTRL_RODTE, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, |
| SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0, |
| SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0, |
| SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0, |
| SHU_B0_DQ7_R_DMRODTEN_B0, 0x1, |
| SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, |
| SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0, |
| SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0, |
| SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0, |
| SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0, |
| SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1, |
| SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x1, |
| SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1, |
| SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, |
| SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0, |
| SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0, |
| SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, |
| SHU_B1_DQ7_R_DMRODTEN_B1, 0x1, |
| SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0, |
| SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0, |
| SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0, |
| SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0, |
| SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0, |
| SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1, |
| SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x1, |
| SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1, |
| SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl, |
| SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x4, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x4, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x7, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x7, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x4, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x4, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x7, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x7, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0, |
| SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0, |
| SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0, |
| SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x0, |
| SHU_RX_CG_SET0_READ_START_EXTEND2, 0x0, |
| SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1, |
| SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x1, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi, |
| SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x0b, |
| SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x09); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi, |
| SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x0b, |
| SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x09); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi, |
| SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x11, |
| SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x0c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi, |
| SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x11, |
| SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x0c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x0b, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x09, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x0d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x0b, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x09, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x0d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x11, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x0c, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x10); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x11, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x0c, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x10); |
| SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[0].shu_r0_ca_cmd0, |
| SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0, |
| SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0, |
| SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00, |
| SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20, |
| SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00, |
| SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0, |
| SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x19, |
| SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x19, |
| SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, |
| SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, |
| SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x1f, |
| SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x1f, |
| SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, |
| SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, |
| SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[1].shu_r0_ca_cmd0, |
| SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0, |
| SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0, |
| SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00, |
| SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20, |
| SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00, |
| SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0, |
| SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x13, |
| SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x13, |
| SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, |
| SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, |
| SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x12, |
| SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x12, |
| SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, |
| SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, |
| SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0, |
| SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1, |
| SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3, |
| SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x5, |
| SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2, |
| SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x4, |
| SHU_DCM_CTRL0_FASTWAKE2, 0x0, |
| SHU_DCM_CTRL0_FASTWAKE, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl, |
| SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3, |
| SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x1, |
| SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x0, |
| SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2, |
| SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x1, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x1, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl, |
| SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x0, |
| SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x0, |
| SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0, |
| SHU_SELPH_DQS0_TXDLY_DQS0, 0x2, |
| SHU_SELPH_DQS0_TXDLY_DQS1, 0x2, |
| SHU_SELPH_DQS0_TXDLY_DQS2, 0x1, |
| SHU_SELPH_DQS0_TXDLY_DQS3, 0x1, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x1, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x1, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs1, |
| SHU_SELPH_DQS1_DLY_DQS0, 0x1, |
| SHU_SELPH_DQS1_DLY_DQS1, 0x1, |
| SHU_SELPH_DQS1_DLY_DQS2, 0x1, |
| SHU_SELPH_DQS1_DLY_DQS3, 0x1, |
| SHU_SELPH_DQS1_DLY_OEN_DQS0, 0x6, |
| SHU_SELPH_DQS1_DLY_OEN_DQS1, 0x6, |
| SHU_SELPH_DQS1_DLY_OEN_DQS2, 0x1, |
| SHU_SELPH_DQS1_DLY_OEN_DQS3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0, |
| SHURK_SELPH_DQ0_TXDLY_DQ0, 0x2, |
| SHURK_SELPH_DQ0_TXDLY_DQ1, 0x2, |
| SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1, |
| SHURK_SELPH_DQ1_TXDLY_DQM0, 0x2, |
| SHURK_SELPH_DQ1_TXDLY_DQM1, 0x2, |
| SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2, |
| SHURK_SELPH_DQ2_DLY_DQ0, 0x1, |
| SHURK_SELPH_DQ2_DLY_DQ1, 0x1, |
| SHURK_SELPH_DQ2_DLY_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_DQ3, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x6, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x6, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3, |
| SHURK_SELPH_DQ3_DLY_DQM0, 0x1, |
| SHURK_SELPH_DQ3_DLY_DQM1, 0x1, |
| SHURK_SELPH_DQ3_DLY_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_DQM3, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x6, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x6, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0, |
| SHURK_SELPH_DQ0_TXDLY_DQ0, 0x2, |
| SHURK_SELPH_DQ0_TXDLY_DQ1, 0x2, |
| SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1, |
| SHURK_SELPH_DQ1_TXDLY_DQM0, 0x2, |
| SHURK_SELPH_DQ1_TXDLY_DQM1, 0x2, |
| SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2, |
| SHURK_SELPH_DQ2_DLY_DQ0, 0x2, |
| SHURK_SELPH_DQ2_DLY_DQ1, 0x2, |
| SHURK_SELPH_DQ2_DLY_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_DQ3, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x7, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x7, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3, |
| SHURK_SELPH_DQ3_DLY_DQM0, 0x2, |
| SHURK_SELPH_DQ3_DLY_DQM1, 0x2, |
| SHURK_SELPH_DQ3_DLY_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_DQM3, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x7, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x7, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x019, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x01f); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x019, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x01f); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x019, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x01f); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x013, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x012); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x013, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x012); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x013, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x012); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi, |
| SHURK_PI_RK0_ARPI_DQ_B1, 0x1f, |
| SHURK_PI_RK0_ARPI_DQ_B0, 0x19, |
| SHURK_PI_RK0_ARPI_DQM_B1, 0x1f, |
| SHURK_PI_RK0_ARPI_DQM_B0, 0x19); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi, |
| SHURK_PI_RK0_ARPI_DQ_B1, 0x12, |
| SHURK_PI_RK0_ARPI_DQ_B0, 0x13, |
| SHURK_PI_RK0_ARPI_DQM_B1, 0x12, |
| SHURK_PI_RK0_ARPI_DQM_B0, 0x13); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0, |
| SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x3c, |
| SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x3c, |
| SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x3c, |
| SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x3c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1, |
| SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x3c, |
| SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x3c, |
| SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x3c, |
| SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x3c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3, |
| SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x3c, |
| SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, |
| SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0, |
| SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x08); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1, |
| SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x08); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3, |
| SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, |
| SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0, |
| SHU_AC_DERATING0_ACDERATEEN, 0x0, |
| SHU_AC_DERATING0_TRRD_DERATE, 0x1, |
| SHU_AC_DERATING0_TRCD_DERATE, 0x4); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1, |
| SHU_AC_DERATING1_TRPAB_DERATE, 0x3, |
| SHU_AC_DERATING1_TRP_DERATE, 0x2, |
| SHU_AC_DERATING1_TRAS_DERATE, 0x00, |
| SHU_AC_DERATING1_TRC_DERATE, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_derating_05t, |
| SHU_AC_DERATING_05T_TRC_05T_DERATE, 0x0, |
| SHU_AC_DERATING_05T_TRCD_05T_DERATE, 0x0, |
| SHU_AC_DERATING_05T_TRP_05T_DERATE, 0x1, |
| SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 0x1, |
| SHU_AC_DERATING_05T_TRAS_05T_DERATE, 0x1, |
| SHU_AC_DERATING_05T_TRRD_05T_DERATE, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl, |
| SHU_SREF_CTRL_CKEHCMD, 0x3, |
| SHU_SREF_CTRL_SREF_CK_DLY, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0, |
| SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x32, |
| SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, |
| SHU_AC_TIME_05T_TRC_05T, 0x0, |
| SHU_AC_TIME_05T_TRFCPB_05T, 0x0, |
| SHU_AC_TIME_05T_TRFC_05T, 0x0, |
| SHU_AC_TIME_05T_TPBR2PBR_05T, 0x0, |
| SHU_AC_TIME_05T_TXP_05T, 0x0, |
| SHU_AC_TIME_05T_TRTP_05T, 0x1, |
| SHU_AC_TIME_05T_TRCD_05T, 0x0, |
| SHU_AC_TIME_05T_TRP_05T, 0x1, |
| SHU_AC_TIME_05T_TRPAB_05T, 0x0, |
| SHU_AC_TIME_05T_TRAS_05T, 0x0, |
| SHU_AC_TIME_05T_TWR_M05T, 0x1, |
| SHU_AC_TIME_05T_TRRD_05T, 0x0, |
| SHU_AC_TIME_05T_TFAW_05T, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, |
| SHU_AC_TIME_05T_TCKEPRD_05T, 0x0, |
| SHU_AC_TIME_05T_TR2PD_05T, 0x0, |
| SHU_AC_TIME_05T_TWTPD_M05T, 0x1, |
| SHU_AC_TIME_05T_TMRRI_05T, 0x1, |
| SHU_AC_TIME_05T_TMRWCKEL_05T, 0x0, |
| SHU_AC_TIME_05T_BGTRRD_05T, 0x0, |
| SHU_AC_TIME_05T_BGTCCD_05T, 0x0, |
| SHU_AC_TIME_05T_BGTWTR_M05T, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, |
| SHU_AC_TIME_05T_TR2W_05T, 0x0, |
| SHU_AC_TIME_05T_TWTR_M05T, 0x1, |
| SHU_AC_TIME_05T_XRTR2W_05T, 0x0, |
| SHU_AC_TIME_05T_TMRD_05T, 0x1, |
| SHU_AC_TIME_05T_TMRW_05T, 0x1, |
| SHU_AC_TIME_05T_TMRR2MRW_05T, 0x1, |
| SHU_AC_TIME_05T_TW2MRW_05T, 0x1, |
| SHU_AC_TIME_05T_TR2MRW_05T, 0x0, |
| SHU_AC_TIME_05T_TPBR2ACT_05T, 0x1, |
| SHU_AC_TIME_05T_XRTW2R_M05T, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt, |
| SHU_ACTIM_XRT_XRTR2R, 0x03, |
| SHU_ACTIM_XRT_XRTR2W, 0x03, |
| SHU_ACTIM_XRT_XRTW2R, 0x3, |
| SHU_ACTIM_XRT_XRTW2W, 0x04); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim0, |
| SHU_ACTIM0_TWTR, 0x04, |
| SHU_ACTIM0_TWR, 0x07, |
| SHU_ACTIM0_TRRD, 0x1, |
| SHU_ACTIM0_TRCD, 0x4, |
| SHU_ACTIM0_CKELCKCNT, 0x2); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim1, |
| SHU_ACTIM1_TRPAB, 0x3, |
| SHU_ACTIM1_TMRWCKEL, 0x4, |
| SHU_ACTIM1_TRP, 0x2, |
| SHU_ACTIM1_TRAS, 0x00, |
| SHU_ACTIM1_TRC, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim2, |
| SHU_ACTIM2_TXP, 0x0, |
| SHU_ACTIM2_TMRRI, 0x05, |
| SHU_ACTIM2_TRTP, 0x0, |
| SHU_ACTIM2_TR2W, 0x03, |
| SHU_ACTIM2_TFAW, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim3, |
| SHU_ACTIM3_TRFCPB, 0x1a, |
| SHU_ACTIM3_MANTMRR, 0x4, |
| SHU_ACTIM3_TR2MRR, 0x4, |
| SHU_ACTIM3_TRFC, 0x40, |
| SHU_ACTIM3_TWTR_L, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim4, |
| SHU_ACTIM4_TXREFCNT, 0x04e, |
| SHU_ACTIM4_TMRR2MRW, 0x07, |
| SHU_ACTIM4_TMRR2W, 0x05, |
| SHU_ACTIM4_TZQCS, 0x10); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim5, |
| SHU_ACTIM5_TR2PD, 0x08, |
| SHU_ACTIM5_TWTPD, 0x09, |
| SHU_ACTIM5_TPBR2PBR, 0x0b, |
| SHU_ACTIM5_TPBR2ACT, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim6, |
| SHU_ACTIM6_TZQLAT2, 0x06, |
| SHU_ACTIM6_TMRD, 0x3, |
| SHU_ACTIM6_TMRW, 0x2, |
| SHU_ACTIM6_TW2MRW, 0x06, |
| SHU_ACTIM6_TR2MRW, 0x09); |
| SET32_BITFIELDS(&ch[0].ao.shu_ckectrl, |
| SHU_CKECTRL_TPDE_05T, 0x1, |
| SHU_CKECTRL_TPDX_05T, 0x0, |
| SHU_CKECTRL_TPDE, 0x1, |
| SHU_CKECTRL_TPDX, 0x1, |
| SHU_CKECTRL_TCKEPRD, 0x1, |
| SHU_CKECTRL_TCKESRX, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_misc, |
| SHU_MISC_REQQUE_MAXCNT, 0x2, |
| SHU_MISC_DCMDLYREF, 0x7, |
| SHU_MISC_DAREFEN, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8, |
| SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x0063, |
| SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0, |
| SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1, |
| SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1, |
| SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8, |
| SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x0063, |
| SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0, |
| SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1, |
| SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1, |
| SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5, |
| SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e, |
| SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0, |
| SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00, |
| SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0, |
| SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0, |
| SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x5, |
| SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5, |
| SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e, |
| SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0, |
| SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00, |
| SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0, |
| SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0, |
| SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x5, |
| SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x64, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x64, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x64, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x64); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x64, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x64, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x64, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x64); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x64, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x64, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x64, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x64); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x64, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x64, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x64, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x64); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x64, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x64); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x0da, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x0da); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x63, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x63, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x63, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x63); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x63, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x63, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x63, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x63); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x63, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x63, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x63, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x63); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x63, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x63, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x63, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x63); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x63, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x63); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x0d9, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x0d9); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x64, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x64, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x64, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x64); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x64, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x64, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x64, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x64); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x64, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x64, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x64, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x64); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x64, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x64, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x64, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x64); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x64, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x64); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0da, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0da); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x63, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x63, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x63, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x63); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x63, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x63, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x63, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x63); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x63, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x63, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x63, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x63); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x63, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x63, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x63, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x63); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x63, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x63); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0d9, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0d9); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, |
| B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1, |
| B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0, |
| B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0, |
| B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1, |
| B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0, |
| B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00, |
| B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0, |
| B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0, |
| B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0, |
| B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, |
| B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1, |
| B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0, |
| B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0, |
| B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1, |
| B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0, |
| B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00, |
| B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0, |
| B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0, |
| B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0, |
| B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4, |
| B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x6e, |
| B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x6e, |
| B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x24, |
| B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x24); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4, |
| B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x6e, |
| B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x6e, |
| B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x24, |
| B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x24); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, |
| B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e, |
| B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1, |
| B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, |
| B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e, |
| B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1, |
| B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0); |
| } |
| |
| static void sv_algorithm_assistance_lp4_3733(void) |
| { |
| SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track, |
| SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x0f, |
| SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1, |
| SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0, |
| SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xfd0, |
| SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x030); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat, |
| MISC_SHU_RDAT_DATLAT, 0x0f, |
| MISC_SHU_RDAT_DATLAT_DSEL, 0x0f, |
| MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x0f); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, |
| MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1, |
| MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x2, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x1, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x2, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl, |
| MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x4, |
| MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1, |
| MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1, |
| MISC_SHU_RANKCTL_RANKINCTL_STB, 0x6, |
| MISC_SHU_RANKCTL_RANKINCTL, 0x5, |
| MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x5, |
| MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x8); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x2, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x2, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x2); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, |
| MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, |
| MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x0, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x4, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x0f); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x7, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0xb, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x1c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x0, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x4, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x0f); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x7, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0xb, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x1c); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, |
| MISC_SHU_ODTCTRL_RODTEN, 0x1, |
| MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0, |
| MISC_SHU_ODTCTRL_RODT_LAT, 0x7, |
| MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0, |
| MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0, |
| MISC_SHU_ODTCTRL_FIXRODT, 0x0, |
| MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1, |
| MISC_SHU_ODTCTRL_RODTE2, 0x1, |
| MISC_SHU_ODTCTRL_RODTE, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, |
| SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0, |
| SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0, |
| SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, |
| SHU_B0_DQ7_R_DMRODTEN_B0, 0x1, |
| SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0, |
| SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0, |
| SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0, |
| SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0, |
| SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0, |
| SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1, |
| SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x1, |
| SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1, |
| SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, |
| SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0, |
| SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0, |
| SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, |
| SHU_B1_DQ7_R_DMRODTEN_B1, 0x1, |
| SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0, |
| SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0, |
| SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0, |
| SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0, |
| SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0, |
| SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1, |
| SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x1, |
| SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1, |
| SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl, |
| SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x3, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x3, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x2, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x2, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x1, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x3, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x3, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x2, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x2, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x1, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0, |
| SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0, |
| SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0, |
| SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x1, |
| SHU_RX_CG_SET0_READ_START_EXTEND2, 0x1, |
| SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1, |
| SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x6, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x2, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi, |
| SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x0f, |
| SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x10); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi, |
| SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x0f, |
| SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x10); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi, |
| SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x1c, |
| SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x17); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi, |
| SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x1c, |
| SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x17); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x0f, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x10, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x14); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x0f, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x10, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x14); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x1c, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x17, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x1b); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x1c, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x17, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x1b); |
| SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[0].shu_r0_ca_cmd0, |
| SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0, |
| SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0, |
| SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00, |
| SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20, |
| SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00, |
| SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0, |
| SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x11, |
| SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x11, |
| SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, |
| SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, |
| SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x12, |
| SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x12, |
| SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, |
| SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, |
| SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[1].shu_r0_ca_cmd0, |
| SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0, |
| SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0, |
| SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00, |
| SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20, |
| SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00, |
| SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0, |
| SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x16, |
| SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x16, |
| SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, |
| SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, |
| SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x21, |
| SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x21, |
| SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, |
| SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, |
| SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0, |
| SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1, |
| SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3, |
| SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x5, |
| SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2, |
| SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x4, |
| SHU_DCM_CTRL0_FASTWAKE2, 0x0, |
| SHU_DCM_CTRL0_FASTWAKE, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl, |
| SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3, |
| SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x3, |
| SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x2, |
| SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2, |
| SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x3, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x3, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl, |
| SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x3, |
| SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x3, |
| SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0, |
| SHU_SELPH_DQS0_TXDLY_DQS0, 0x4, |
| SHU_SELPH_DQS0_TXDLY_DQS1, 0x4, |
| SHU_SELPH_DQS0_TXDLY_DQS2, 0x1, |
| SHU_SELPH_DQS0_TXDLY_DQS3, 0x1, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x3, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x3, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs1, |
| SHU_SELPH_DQS1_DLY_DQS0, 0x1, |
| SHU_SELPH_DQS1_DLY_DQS1, 0x1, |
| SHU_SELPH_DQS1_DLY_DQS2, 0x1, |
| SHU_SELPH_DQS1_DLY_DQS3, 0x1, |
| SHU_SELPH_DQS1_DLY_OEN_DQS0, 0x6, |
| SHU_SELPH_DQS1_DLY_OEN_DQS1, 0x6, |
| SHU_SELPH_DQS1_DLY_OEN_DQS2, 0x1, |
| SHU_SELPH_DQS1_DLY_OEN_DQS3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0, |
| SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x3, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x3, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1, |
| SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x3, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x3, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2, |
| SHURK_SELPH_DQ2_DLY_DQ0, 0x2, |
| SHURK_SELPH_DQ2_DLY_DQ1, 0x2, |
| SHURK_SELPH_DQ2_DLY_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_DQ3, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x7, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x7, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3, |
| SHURK_SELPH_DQ3_DLY_DQM0, 0x2, |
| SHURK_SELPH_DQ3_DLY_DQM1, 0x2, |
| SHURK_SELPH_DQ3_DLY_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_DQM3, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x7, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x7, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0, |
| SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1, |
| SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2, |
| SHURK_SELPH_DQ2_DLY_DQ0, 0x3, |
| SHURK_SELPH_DQ2_DLY_DQ1, 0x3, |
| SHURK_SELPH_DQ2_DLY_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_DQ3, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x0, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x0, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3, |
| SHURK_SELPH_DQ3_DLY_DQM0, 0x3, |
| SHURK_SELPH_DQ3_DLY_DQM1, 0x3, |
| SHURK_SELPH_DQ3_DLY_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_DQM3, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x0, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x0, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x011, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x012); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x011, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x012); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x011, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x012); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x016, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x021); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x016, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x021); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x016, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x021); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi, |
| SHURK_PI_RK0_ARPI_DQ_B1, 0x12, |
| SHURK_PI_RK0_ARPI_DQ_B0, 0x11, |
| SHURK_PI_RK0_ARPI_DQM_B1, 0x12, |
| SHURK_PI_RK0_ARPI_DQM_B0, 0x11); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi, |
| SHURK_PI_RK0_ARPI_DQ_B1, 0x21, |
| SHURK_PI_RK0_ARPI_DQ_B0, 0x16, |
| SHURK_PI_RK0_ARPI_DQM_B1, 0x21, |
| SHURK_PI_RK0_ARPI_DQM_B0, 0x16); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0, |
| SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x08, |
| SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x08, |
| SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x08, |
| SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x08); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1, |
| SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x08, |
| SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x08, |
| SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x08, |
| SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x08); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3, |
| SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x08, |
| SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, |
| SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly0, |
| SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x04, |
| SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x04, |
| SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x04, |
| SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x04); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly1, |
| SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x04, |
| SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x04, |
| SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x04, |
| SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x04); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly3, |
| SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x04, |
| SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, |
| SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly0, |
| SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x34, |
| SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x34, |
| SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x34, |
| SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x34); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly1, |
| SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x34, |
| SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x34, |
| SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x34, |
| SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x34); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly3, |
| SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x34, |
| SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, |
| SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0, |
| SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x08); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1, |
| SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x08); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3, |
| SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, |
| SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_tx_rankctl, |
| SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 0x2, |
| SHU_TX_RANKCTL_TXRANKINCTL, 0x2, |
| SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0, |
| SHU_AC_DERATING0_ACDERATEEN, 0x0, |
| SHU_AC_DERATING0_TRRD_DERATE, 0x5, |
| SHU_AC_DERATING0_TRCD_DERATE, 0x9); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1, |
| SHU_AC_DERATING1_TRPAB_DERATE, 0x9, |
| SHU_AC_DERATING1_TRP_DERATE, 0x8, |
| SHU_AC_DERATING1_TRAS_DERATE, 0x0c, |
| SHU_AC_DERATING1_TRC_DERATE, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_derating_05t, |
| SHU_AC_DERATING_05T_TRC_05T_DERATE, 0x0, |
| SHU_AC_DERATING_05T_TRCD_05T_DERATE, 0x1, |
| SHU_AC_DERATING_05T_TRP_05T_DERATE, 0x0, |
| SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 0x1, |
| SHU_AC_DERATING_05T_TRAS_05T_DERATE, 0x0, |
| SHU_AC_DERATING_05T_TRRD_05T_DERATE, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl, |
| SHU_SREF_CTRL_CKEHCMD, 0x3, |
| SHU_SREF_CTRL_SREF_CK_DLY, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0, |
| SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x75, |
| SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, |
| SHU_AC_TIME_05T_TRC_05T, 0x0, |
| SHU_AC_TIME_05T_TRFCPB_05T, 0x0, |
| SHU_AC_TIME_05T_TRFC_05T, 0x1, |
| SHU_AC_TIME_05T_TPBR2PBR_05T, 0x0, |
| SHU_AC_TIME_05T_TXP_05T, 0x1, |
| SHU_AC_TIME_05T_TRTP_05T, 0x0, |
| SHU_AC_TIME_05T_TRCD_05T, 0x1, |
| SHU_AC_TIME_05T_TRP_05T, 0x0, |
| SHU_AC_TIME_05T_TRPAB_05T, 0x1, |
| SHU_AC_TIME_05T_TRAS_05T, 0x1, |
| SHU_AC_TIME_05T_TWR_M05T, 0x1, |
| SHU_AC_TIME_05T_TRRD_05T, 0x0, |
| SHU_AC_TIME_05T_TFAW_05T, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, |
| SHU_AC_TIME_05T_TCKEPRD_05T, 0x0, |
| SHU_AC_TIME_05T_TR2PD_05T, 0x0, |
| SHU_AC_TIME_05T_TWTPD_M05T, 0x1, |
| SHU_AC_TIME_05T_TMRRI_05T, 0x0, |
| SHU_AC_TIME_05T_TMRWCKEL_05T, 0x0, |
| SHU_AC_TIME_05T_BGTRRD_05T, 0x0, |
| SHU_AC_TIME_05T_BGTCCD_05T, 0x0, |
| SHU_AC_TIME_05T_BGTWTR_M05T, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, |
| SHU_AC_TIME_05T_TR2W_05T, 0x0, |
| SHU_AC_TIME_05T_TWTR_M05T, 0x0, |
| SHU_AC_TIME_05T_XRTR2W_05T, 0x0, |
| SHU_AC_TIME_05T_TMRD_05T, 0x1, |
| SHU_AC_TIME_05T_TMRW_05T, 0x0, |
| SHU_AC_TIME_05T_TMRR2MRW_05T, 0x1, |
| SHU_AC_TIME_05T_TW2MRW_05T, 0x0, |
| SHU_AC_TIME_05T_TR2MRW_05T, 0x1, |
| SHU_AC_TIME_05T_TPBR2ACT_05T, 0x1, |
| SHU_AC_TIME_05T_XRTW2R_M05T, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt, |
| SHU_ACTIM_XRT_XRTR2R, 0x03, |
| SHU_ACTIM_XRT_XRTR2W, 0x08, |
| SHU_ACTIM_XRT_XRTW2R, 0x1, |
| SHU_ACTIM_XRT_XRTW2W, 0x05); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim0, |
| SHU_ACTIM0_TWTR, 0x08, |
| SHU_ACTIM0_TWR, 0x0d, |
| SHU_ACTIM0_TRRD, 0x4, |
| SHU_ACTIM0_TRCD, 0x8, |
| SHU_ACTIM0_CKELCKCNT, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim1, |
| SHU_ACTIM1_TRPAB, 0x8, |
| SHU_ACTIM1_TMRWCKEL, 0x8, |
| SHU_ACTIM1_TRP, 0x7, |
| SHU_ACTIM1_TRAS, 0x0b, |
| SHU_ACTIM1_TRC, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim2, |
| SHU_ACTIM2_TXP, 0x0, |
| SHU_ACTIM2_TMRRI, 0x0c, |
| SHU_ACTIM2_TRTP, 0x2, |
| SHU_ACTIM2_TR2W, 0x09, |
| SHU_ACTIM2_TFAW, 0x0b); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim3, |
| SHU_ACTIM3_TRFCPB, 0x4d, |
| SHU_ACTIM3_MANTMRR, 0x4, |
| SHU_ACTIM3_TR2MRR, 0x4, |
| SHU_ACTIM3_TRFC, 0xa5, |
| SHU_ACTIM3_TWTR_L, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim4, |
| SHU_ACTIM4_TXREFCNT, 0x0b5, |
| SHU_ACTIM4_TMRR2MRW, 0x0d, |
| SHU_ACTIM4_TMRR2W, 0x0c, |
| SHU_ACTIM4_TZQCS, 0x28); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim5, |
| SHU_ACTIM5_TR2PD, 0x0e, |
| SHU_ACTIM5_TWTPD, 0x10, |
| SHU_ACTIM5_TPBR2PBR, 0x23, |
| SHU_ACTIM5_TPBR2ACT, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim6, |
| SHU_ACTIM6_TZQLAT2, 0x0e, |
| SHU_ACTIM6_TMRD, 0x7, |
| SHU_ACTIM6_TMRW, 0x5, |
| SHU_ACTIM6_TW2MRW, 0x0a, |
| SHU_ACTIM6_TR2MRW, 0x10); |
| SET32_BITFIELDS(&ch[0].ao.shu_ckectrl, |
| SHU_CKECTRL_TPDE_05T, 0x1, |
| SHU_CKECTRL_TPDX_05T, 0x0, |
| SHU_CKECTRL_TPDE, 0x1, |
| SHU_CKECTRL_TPDX, 0x1, |
| SHU_CKECTRL_TCKEPRD, 0x3, |
| SHU_CKECTRL_TCKESRX, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_misc, |
| SHU_MISC_REQQUE_MAXCNT, 0x2, |
| SHU_MISC_DCMDLYREF, 0x7, |
| SHU_MISC_DAREFEN, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8, |
| SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x00e7, |
| SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0, |
| SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1, |
| SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1, |
| SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8, |
| SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x00e7, |
| SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0, |
| SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1, |
| SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1, |
| SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5, |
| SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e, |
| SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0, |
| SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00, |
| SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0, |
| SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0, |
| SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x4, |
| SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5, |
| SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e, |
| SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0, |
| SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00, |
| SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0, |
| SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0, |
| SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x4, |
| SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x6d, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x6d, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x6d, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x6d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x6d, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x6d, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x6d, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x6d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x6d, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x6d, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x6d, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x6d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x6d, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x6d, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x6d, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x6d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x6d, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x6d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x061, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x061); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x6c, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x6c, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x6c, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x6c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x6c, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x6c, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x6c, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x6c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x6c, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x6c, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x6c, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x6c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x6c, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x6c, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x6c, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x6c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x6c, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x6c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x060, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x060); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x6d, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x6d, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x6d, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x6d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x6d, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x6d, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x6d, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x6d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x6d, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x6d, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x6d, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x6d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x6d, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x6d, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x6d, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x6d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x6d, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x6d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x061, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x061); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x6c, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x6c, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x6c, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x6c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x6c, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x6c, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x6c, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x6c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x6c, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x6c, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x6c, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x6c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x6c, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x6c, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x6c, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x6c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x6c, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x6c); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x060, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x060); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, |
| B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1, |
| B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0, |
| B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0, |
| B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1, |
| B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0, |
| B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00, |
| B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0, |
| B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0, |
| B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0, |
| B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, |
| B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1, |
| B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0, |
| B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0, |
| B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1, |
| B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0, |
| B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00, |
| B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0, |
| B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0, |
| B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0, |
| B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4, |
| B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x75, |
| B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x75, |
| B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x2d, |
| B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x2d); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4, |
| B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x75, |
| B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x75, |
| B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x2d, |
| B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x2d); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, |
| B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e, |
| B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1, |
| B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, |
| B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e, |
| B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1, |
| B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0); |
| } |
| |
| static void sv_algorithm_assistance_lp4_4266(void) |
| { |
| SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track, |
| SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x10, |
| SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1, |
| SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0, |
| SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xfcb, |
| SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x035); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat, |
| MISC_SHU_RDAT_DATLAT, 0x10, |
| MISC_SHU_RDAT_DATLAT_DSEL, 0x0f, |
| MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x0f); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, |
| MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1, |
| MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x2, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x1, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x2, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl, |
| MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x4, |
| MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1, |
| MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1, |
| MISC_SHU_RANKCTL_RANKINCTL_STB, 0x6, |
| MISC_SHU_RANKCTL_RANKINCTL, 0x5, |
| MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x5, |
| MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x8); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x2, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x2, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x2); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, |
| MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, |
| MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x1, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x5, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x01); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x9, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0xd, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1, |
| SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x08); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x1, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x5, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x01); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x9, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0xd, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1, |
| SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly, |
| SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x08); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, |
| MISC_SHU_ODTCTRL_RODTEN, 0x1, |
| MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0, |
| MISC_SHU_ODTCTRL_RODT_LAT, 0x7, |
| MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0, |
| MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0, |
| MISC_SHU_ODTCTRL_FIXRODT, 0x0, |
| MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1, |
| MISC_SHU_ODTCTRL_RODTE2, 0x1, |
| MISC_SHU_ODTCTRL_RODTE, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, |
| SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0, |
| SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0, |
| SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0, |
| SHU_B0_DQ7_R_DMRODTEN_B0, 0x1, |
| SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, |
| SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0, |
| SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0, |
| SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0, |
| SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0, |
| SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1, |
| SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x2, |
| SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1, |
| SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, |
| SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0, |
| SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0, |
| SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, |
| SHU_B1_DQ7_R_DMRODTEN_B1, 0x1, |
| SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0, |
| SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0, |
| SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0, |
| SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0, |
| SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0, |
| SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1, |
| SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x2, |
| SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1, |
| SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x4, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x4, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x4, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x4, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x1, |
| SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x4, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x4, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x4, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x4, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x1, |
| SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0, |
| SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0, |
| SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0, |
| SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x1, |
| SHU_RX_CG_SET0_READ_START_EXTEND2, 0x1, |
| SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1, |
| SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x6, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x2, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, |
| MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, |
| MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi, |
| SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x01, |
| SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x11); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi, |
| SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x01, |
| SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x11); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi, |
| SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x08, |
| SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x19); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi, |
| SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x08, |
| SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x19); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x01, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x11, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x15); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x01, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x11, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x15); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x08, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x19, |
| SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x1d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x08, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x19, |
| SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x1d); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x13, |
| SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x13, |
| SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, |
| SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, |
| SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x16, |
| SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x16, |
| SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, |
| SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, |
| SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, |
| SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x2b, |
| SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x2b, |
| SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x01, |
| SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, |
| SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, |
| SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x2b, |
| SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x2b, |
| SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x01, |
| SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, |
| SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0, |
| SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1, |
| SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3, |
| SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x5, |
| SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2, |
| SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x4, |
| SHU_DCM_CTRL0_FASTWAKE2, 0x0, |
| SHU_DCM_CTRL0_FASTWAKE, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl, |
| SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3, |
| SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x3, |
| SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x3, |
| SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2, |
| SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x4, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x4, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl, |
| SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x2, |
| SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x2, |
| SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0, |
| SHU_SELPH_DQS0_TXDLY_DQS0, 0x4, |
| SHU_SELPH_DQS0_TXDLY_DQS1, 0x4, |
| SHU_SELPH_DQS0_TXDLY_DQS2, 0x1, |
| SHU_SELPH_DQS0_TXDLY_DQS3, 0x1, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x4, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x4, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs1, |
| SHU_SELPH_DQS1_DLY_DQS0, 0x5, |
| SHU_SELPH_DQS1_DLY_DQS1, 0x5, |
| SHU_SELPH_DQS1_DLY_DQS2, 0x1, |
| SHU_SELPH_DQS1_DLY_DQS3, 0x1, |
| SHU_SELPH_DQS1_DLY_OEN_DQS0, 0x2, |
| SHU_SELPH_DQS1_DLY_OEN_DQS1, 0x2, |
| SHU_SELPH_DQS1_DLY_OEN_DQS2, 0x1, |
| SHU_SELPH_DQS1_DLY_OEN_DQS3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0, |
| SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1, |
| SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2, |
| SHURK_SELPH_DQ2_DLY_DQ0, 0x6, |
| SHURK_SELPH_DQ2_DLY_DQ1, 0x6, |
| SHURK_SELPH_DQ2_DLY_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_DQ3, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x3, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x3, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3, |
| SHURK_SELPH_DQ3_DLY_DQM0, 0x6, |
| SHURK_SELPH_DQ3_DLY_DQM1, 0x6, |
| SHURK_SELPH_DQ3_DLY_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_DQM3, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x3, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x3, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0, |
| SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x4, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1, |
| SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x4, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2, |
| SHURK_SELPH_DQ2_DLY_DQ0, 0x7, |
| SHURK_SELPH_DQ2_DLY_DQ1, 0x7, |
| SHURK_SELPH_DQ2_DLY_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_DQ3, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x4, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x4, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3, |
| SHURK_SELPH_DQ3_DLY_DQM0, 0x7, |
| SHURK_SELPH_DQ3_DLY_DQM1, 0x7, |
| SHURK_SELPH_DQ3_DLY_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_DQM3, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x4, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x4, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, |
| SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x013, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x016); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x013, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x016); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x013, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x016); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x02b, |
| SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x02b); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x02b, |
| SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x02b); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x02b, |
| SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x02b); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi, |
| SHURK_PI_RK0_ARPI_DQ_B1, 0x16, |
| SHURK_PI_RK0_ARPI_DQ_B0, 0x13, |
| SHURK_PI_RK0_ARPI_DQM_B1, 0x16, |
| SHURK_PI_RK0_ARPI_DQM_B0, 0x13); |
| SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi, |
| SHURK_PI_RK0_ARPI_DQ_B1, 0x2b, |
| SHURK_PI_RK0_ARPI_DQ_B0, 0x2b, |
| SHURK_PI_RK0_ARPI_DQM_B1, 0x2b, |
| SHURK_PI_RK0_ARPI_DQM_B0, 0x2b); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0, |
| SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x10, |
| SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x10, |
| SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x10, |
| SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x10); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1, |
| SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x10, |
| SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x10, |
| SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x10, |
| SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x10); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3, |
| SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x10, |
| SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, |
| SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly0, |
| SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x04, |
| SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x04, |
| SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x04, |
| SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x04); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly1, |
| SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x04, |
| SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x04, |
| SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x04, |
| SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x04); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly3, |
| SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x04, |
| SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, |
| SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly0, |
| SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x08, |
| SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x08, |
| SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x08, |
| SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x08); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly1, |
| SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x08, |
| SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x08, |
| SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x08, |
| SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x08); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly3, |
| SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x08, |
| SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, |
| SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0, |
| SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x08); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1, |
| SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x08); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3, |
| SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x08, |
| SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, |
| SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_tx_rankctl, |
| SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 0x1, |
| SHU_TX_RANKCTL_TXRANKINCTL, 0x1, |
| SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0, |
| SHU_AC_DERATING0_ACDERATEEN, 0x0, |
| SHU_AC_DERATING0_TRRD_DERATE, 0x5, |
| SHU_AC_DERATING0_TRCD_DERATE, 0xb); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1, |
| SHU_AC_DERATING1_TRPAB_DERATE, 0xb, |
| SHU_AC_DERATING1_TRP_DERATE, 0x9, |
| SHU_AC_DERATING1_TRAS_DERATE, 0x0f, |
| SHU_AC_DERATING1_TRC_DERATE, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_derating_05t, |
| SHU_AC_DERATING_05T_TRC_05T_DERATE, 0x0, |
| SHU_AC_DERATING_05T_TRCD_05T_DERATE, 0x0, |
| SHU_AC_DERATING_05T_TRP_05T_DERATE, 0x1, |
| SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 0x0, |
| SHU_AC_DERATING_05T_TRAS_05T_DERATE, 0x0, |
| SHU_AC_DERATING_05T_TRRD_05T_DERATE, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl, |
| SHU_SREF_CTRL_CKEHCMD, 0x3, |
| SHU_SREF_CTRL_SREF_CK_DLY, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0, |
| SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x86, |
| SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, |
| SHU_AC_TIME_05T_TRC_05T, 0x0, |
| SHU_AC_TIME_05T_TRFCPB_05T, 0x1, |
| SHU_AC_TIME_05T_TRFC_05T, 0x0, |
| SHU_AC_TIME_05T_TPBR2PBR_05T, 0x0, |
| SHU_AC_TIME_05T_TXP_05T, 0x0, |
| SHU_AC_TIME_05T_TRTP_05T, 0x1, |
| SHU_AC_TIME_05T_TRCD_05T, 0x0, |
| SHU_AC_TIME_05T_TRP_05T, 0x1, |
| SHU_AC_TIME_05T_TRPAB_05T, 0x0, |
| SHU_AC_TIME_05T_TRAS_05T, 0x0, |
| SHU_AC_TIME_05T_TWR_M05T, 0x0, |
| SHU_AC_TIME_05T_TRRD_05T, 0x0, |
| SHU_AC_TIME_05T_TFAW_05T, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, |
| SHU_AC_TIME_05T_TCKEPRD_05T, 0x0, |
| SHU_AC_TIME_05T_TR2PD_05T, 0x1, |
| SHU_AC_TIME_05T_TWTPD_M05T, 0x0, |
| SHU_AC_TIME_05T_TMRRI_05T, 0x0, |
| SHU_AC_TIME_05T_TMRWCKEL_05T, 0x1, |
| SHU_AC_TIME_05T_BGTRRD_05T, 0x0, |
| SHU_AC_TIME_05T_BGTCCD_05T, 0x0, |
| SHU_AC_TIME_05T_BGTWTR_M05T, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, |
| SHU_AC_TIME_05T_TR2W_05T, 0x0, |
| SHU_AC_TIME_05T_TWTR_M05T, 0x1, |
| SHU_AC_TIME_05T_XRTR2W_05T, 0x0, |
| SHU_AC_TIME_05T_TMRD_05T, 0x0, |
| SHU_AC_TIME_05T_TMRW_05T, 0x1, |
| SHU_AC_TIME_05T_TMRR2MRW_05T, 0x0, |
| SHU_AC_TIME_05T_TW2MRW_05T, 0x0, |
| SHU_AC_TIME_05T_TR2MRW_05T, 0x0, |
| SHU_AC_TIME_05T_TPBR2ACT_05T, 0x0, |
| SHU_AC_TIME_05T_XRTW2R_M05T, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt, |
| SHU_ACTIM_XRT_XRTR2R, 0x03, |
| SHU_ACTIM_XRT_XRTR2W, 0x08, |
| SHU_ACTIM_XRT_XRTW2R, 0x1, |
| SHU_ACTIM_XRT_XRTW2W, 0x05); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim0, |
| SHU_ACTIM0_TWTR, 0x0a, |
| SHU_ACTIM0_TWR, 0x0f, |
| SHU_ACTIM0_TRRD, 0x3, |
| SHU_ACTIM0_TRCD, 0xa, |
| SHU_ACTIM0_CKELCKCNT, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim1, |
| SHU_ACTIM1_TRPAB, 0xa, |
| SHU_ACTIM1_TMRWCKEL, 0x8, |
| SHU_ACTIM1_TRP, 0x8, |
| SHU_ACTIM1_TRAS, 0x0e, |
| SHU_ACTIM1_TRC, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim2, |
| SHU_ACTIM2_TXP, 0x1, |
| SHU_ACTIM2_TMRRI, 0x0e, |
| SHU_ACTIM2_TRTP, 0x2, |
| SHU_ACTIM2_TR2W, 0x09, |
| SHU_ACTIM2_TFAW, 0x08); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim3, |
| SHU_ACTIM3_TRFCPB, 0x59, |
| SHU_ACTIM3_MANTMRR, 0x4, |
| SHU_ACTIM3_TR2MRR, 0x4, |
| SHU_ACTIM3_TRFC, 0xbf, |
| SHU_ACTIM3_TWTR_L, 0x00); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim4, |
| SHU_ACTIM4_TXREFCNT, 0x0cf, |
| SHU_ACTIM4_TMRR2MRW, 0x0f, |
| SHU_ACTIM4_TMRR2W, 0x0b, |
| SHU_ACTIM4_TZQCS, 0x2e); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim5, |
| SHU_ACTIM5_TR2PD, 0x0f, |
| SHU_ACTIM5_TWTPD, 0x12, |
| SHU_ACTIM5_TPBR2PBR, 0x29, |
| SHU_ACTIM5_TPBR2ACT, 0x0); |
| SET32_BITFIELDS(&ch[0].ao.shu_actim6, |
| SHU_ACTIM6_TZQLAT2, 0x10, |
| SHU_ACTIM6_TMRD, 0x8, |
| SHU_ACTIM6_TMRW, 0x5, |
| SHU_ACTIM6_TW2MRW, 0x0b, |
| SHU_ACTIM6_TR2MRW, 0x12); |
| SET32_BITFIELDS(&ch[0].ao.shu_ckectrl, |
| SHU_CKECTRL_TPDE_05T, 0x1, |
| SHU_CKECTRL_TPDX_05T, 0x0, |
| SHU_CKECTRL_TPDE, 0x1, |
| SHU_CKECTRL_TPDX, 0x1, |
| SHU_CKECTRL_TCKEPRD, 0x3, |
| SHU_CKECTRL_TCKESRX, 0x3); |
| SET32_BITFIELDS(&ch[0].ao.shu_misc, |
| SHU_MISC_REQQUE_MAXCNT, 0x2, |
| SHU_MISC_DCMDLYREF, 0x7, |
| SHU_MISC_DAREFEN, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8, |
| SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x0100, |
| SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0, |
| SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1, |
| SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1, |
| SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0, |
| SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8, |
| SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x0100, |
| SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0, |
| SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1, |
| SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1, |
| SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0, |
| SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5, |
| SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e, |
| SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0, |
| SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00, |
| SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0, |
| SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0, |
| SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x3, |
| SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5, |
| SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e, |
| SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0, |
| SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00, |
| SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0, |
| SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0, |
| SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x3, |
| SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x54, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x54, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x54, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x54); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x54, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x54, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x54, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x54); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x54, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x54, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x54, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x54); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x54, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x54, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x54, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x54); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x54, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x54); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x04a, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x04a); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x46, |
| SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x46, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x46, |
| SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x46); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x46, |
| SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x46, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x46, |
| SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x46); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x46, |
| SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x46, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x46, |
| SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x46); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x46, |
| SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x46, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x46, |
| SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x46); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x46, |
| SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x46); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x038, |
| SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x038); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0xcd, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0xcd, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0xcd, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0xcd); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0xcd, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0xcd, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0xcd, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0xcd); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0xcd, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0xcd, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0xcd, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0xcd); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0xcd, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0xcd, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0xcd, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0xcd); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0xcd, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0xcd); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0bd, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0bd); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0xfe, |
| SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0xfe, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0xfe, |
| SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0xfe); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0xfe, |
| SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0xfe, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0xfe, |
| SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0xfe); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0xfe, |
| SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0xfe, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0xfe, |
| SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0xfe); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0xfe, |
| SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0xfe, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0xfe, |
| SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0xfe); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0xfe, |
| SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0xfe); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0f4, |
| SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0f4); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, |
| B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1, |
| B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0, |
| B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0, |
| B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1, |
| B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0, |
| B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00, |
| B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0, |
| B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0, |
| B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0, |
| B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, |
| B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1, |
| B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0, |
| B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0, |
| B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1, |
| B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0, |
| B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00, |
| B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0, |
| B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0, |
| B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0, |
| B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4, |
| B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x5a, |
| B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x5a, |
| B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x14, |
| B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x14); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4, |
| B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x53, |
| B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x53, |
| B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x0d, |
| B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x0d); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, |
| B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e, |
| B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0, |
| B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1, |
| B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, |
| B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e, |
| B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0, |
| B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1, |
| B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0); |
| } |
| |
| static u32 get_write_latency_by_mr(u8 mr_wl) |
| { |
| u32 write_latency; |
| |
| switch (mr_wl) { |
| case 0: |
| write_latency = 4; |
| break; |
| case 1: |
| write_latency = 6; |
| break; |
| case 2: |
| write_latency = 8; |
| break; |
| case 3: |
| write_latency = 10; |
| break; |
| case 4: |
| write_latency = 12; |
| break; |
| case 5: |
| write_latency = 14; |
| break; |
| case 6: |
| write_latency = 16; |
| break; |
| case 7: |
| write_latency = 18; |
| break; |
| default: |
| dramc_err("error: unexpected mr_wl: %x\n", mr_wl); |
| return 0; |
| } |
| |
| dramc_info("mr_wl: %x map to WriteLatency: %d\n", mr_wl, write_latency); |
| return write_latency; |
| } |
| |
| static void tx_path_algorithm(const struct ddr_cali *cali) |
| { |
| u8 write_latency, wl_mr; |
| const u8 ckr = 1; |
| u8 dqs_total_ui; |
| u8 dqs_oe_total_ui; |
| u8 dqs_mck, dqs_ui; |
| u8 dqs_oe_mck, dqs_oe_ui; |
| u8 shift; |
| const u8 tx_dq_oe_shift = 3; |
| |
| wl_mr = (cali->mr_value->mr02[get_fsp(cali)] & 0x3f) >> 3; |
| shift = get_mck2ui_div_shift(cali); |
| write_latency = get_write_latency_by_mr(wl_mr); |
| dqs_total_ui = write_latency * ckr * 2 + 1; |
| |
| dqs_oe_total_ui = dqs_total_ui - tx_dq_oe_shift; |
| dqs_ui = dqs_total_ui - ((dqs_total_ui >> shift) << shift); |
| dqs_mck = dqs_total_ui >> shift; |
| dqs_oe_ui = dqs_oe_total_ui - ((dqs_oe_total_ui >> shift) << shift); |
| dqs_oe_mck = dqs_oe_total_ui >> shift; |
| dramc_dbg("[TX_path_calculate] write_latency=%u, DQS_TotalUI=%u\n", |
| write_latency, dqs_total_ui); |
| dramc_dbg("[TX_path_calculate] DQS = (%u,%u) DQS_OE = (%u,%u)\n", |
| dqs_mck, dqs_ui, dqs_oe_mck, dqs_oe_ui); |
| |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| SET32_BITFIELDS(&ch[chn].ao.shu_selph_dqs0, |
| SHU_SELPH_DQS0_TXDLY_DQS0, dqs_mck, |
| SHU_SELPH_DQS0_TXDLY_DQS1, dqs_mck, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS0, dqs_oe_mck, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS1, dqs_oe_mck); |
| SET32_BITFIELDS(&ch[chn].ao.shu_selph_dqs1, |
| SHU_SELPH_DQS1_DLY_DQS0, dqs_ui, |
| SHU_SELPH_DQS1_DLY_DQS1, dqs_ui, |
| SHU_SELPH_DQS1_DLY_OEN_DQS0, dqs_oe_ui, |
| SHU_SELPH_DQS1_DLY_OEN_DQS1, dqs_oe_ui); |
| } |
| } |
| |
| static void replace_dv_init(const struct ddr_cali *cali) |
| { |
| bool is_4266; |
| u8 dq_hyst_sel, ca_hyst_sel; |
| u8 dq_cap_sel, ca_cap_sel; |
| u8 dq_bw_sel_b0 = 0, dq_bw_sel_b1 = 0, ca_bw_sel_ca = 0, clk_bw_sel_ca = 0; |
| |
| dram_freq_grp freq_group = cali->freq_group; |
| |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, |
| B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, |
| B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_rxdvs0, |
| B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0, 0, |
| B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0, 0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_rxdvs0, |
| B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1, 0, |
| B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1, 0); |
| |
| for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].rk[rk].rk_b0_rxdvs2, |
| RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0, 0, |
| RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0, 0, |
| RK_B0_RXDVS2_R_RK0_DVS_MODE_B0, 0); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].rk[rk].rk_b0_rxdvs2, |
| RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1, 0, |
| RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1, 0, |
| RK_B1_RXDVS2_R_RK0_DVS_MODE_B1, 0); |
| } |
| |
| SET32_BITFIELDS(&ch[0].ao.cbt_wlev_ctrl1, CBT_WLEV_CTRL1_CATRAINLAT, 0); |
| SET32_BITFIELDS(&ch[0].ao.swcmd_ctrl1, SWCMD_CTRL1_WRFIFO_MODE2, 0); |
| |
| u32 bc_bak = dramc_get_broadcast(); |
| dramc_set_broadcast(DRAMC_BROADCAST_OFF); |
| |
| switch (freq_group) { |
| case DDRFREQ_400: |
| case DDRFREQ_600: |
| case DDRFREQ_800: |
| case DDRFREQ_933: |
| dq_cap_sel = 0x18; |
| ca_cap_sel = 0x18; |
| break; |
| case DDRFREQ_1200: |
| dq_cap_sel = 0x14; |
| ca_cap_sel = 0x14; |
| break; |
| case DDRFREQ_1600: |
| dq_cap_sel = 0x4; |
| ca_cap_sel = 0x4; |
| break; |
| case DDRFREQ_2133: |
| dq_cap_sel = 0x2; |
| ca_cap_sel = 0x2; |
| break; |
| default: |
| die("Invalid DDR frequency group %u\n", freq_group); |
| return; |
| } |
| |
| if (freq_group <= DDRFREQ_933) { |
| dq_hyst_sel = 0x1; |
| ca_hyst_sel = 0x1; |
| } else { |
| dq_hyst_sel = 0x0; |
| ca_hyst_sel = 0x0; |
| } |
| |
| if (freq_group <= DDRFREQ_1200) |
| clk_bw_sel_ca = 1; |
| |
| is_4266 = freq_group >= DDRFREQ_2133; |
| if (is_4266) { |
| dq_bw_sel_b0 = 1; |
| dq_bw_sel_b1 = 1; |
| ca_bw_sel_ca = 1; |
| } |
| |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq6, |
| SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0, dq_hyst_sel, |
| SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0, dq_cap_sel); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq6, |
| SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1, dq_hyst_sel, |
| SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1, dq_cap_sel); |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd6, |
| SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA, ca_hyst_sel, |
| SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA, ca_cap_sel); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq2, |
| SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0, is_4266, |
| SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0, is_4266, |
| SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0, 0, |
| SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0, 0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq2, |
| SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1, is_4266, |
| SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1, is_4266, |
| SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1, 0, |
| SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1, 0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd2, |
| SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA, is_4266, |
| SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA, is_4266, |
| SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA, 0, |
| SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA, 0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rx_pipe_ctrl, |
| SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x0); |
| write32(&ch[chn].phy_ao.misc_dbg_irq_ctrl1, 0x0); |
| write32(&ch[chn].phy_ao.misc_dbg_irq_ctrl4, 0x0); |
| write32(&ch[chn].phy_ao.misc_dbg_irq_ctrl7, 0x0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl, |
| MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY, 0, |
| MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 2, |
| MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT, 0, |
| MISC_SHU_RX_CG_CTRL_RX_DCM_OPT, 0); |
| SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_MR4INT_LIMITEN, 0); |
| SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPEND_OPT1, 0); |
| SET32_BITFIELDS(&ch[chn].ao.refctrl3, REFCTRL3_REF_DERATING_EN, 0); |
| SET32_BITFIELDS(&ch[chn].ao.dramc_irq_en, |
| DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV, 0x3fff, |
| DRAMC_IRQ_EN_MR4INT_EN, 0x0); |
| SET32_BITFIELDS(&ch[chn].ao.shu_conf0, SHU_CONF0_PBREFEN, 0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.ca_tx_mck, |
| CA_TX_MCK_R_DMRESET_FRPHY_OPT, 0x1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, |
| MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE, 0x1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPBINARY, 0x1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq10, |
| SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0, 0x1, |
| SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0, 0x1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq10, |
| SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1, 0x1, |
| SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1, 0x1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq8, |
| SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 1, |
| SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 1, |
| SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 1, |
| SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 1, |
| SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 1, |
| SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 1, |
| SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 1, |
| SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 1, |
| SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 1, |
| SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 1, |
| SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq8, |
| SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 1, |
| SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 1, |
| SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 1, |
| SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 1, |
| SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 1, |
| SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 1, |
| SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 1, |
| SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 1, |
| SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 1, |
| SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 1, |
| SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dll2, |
| SHU_B0_DLL2_RG_ARDQ_REV_B0, 0x1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dll2, |
| SHU_B1_DLL2_RG_ARDQ_REV_B1, 0x1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll2, |
| SHU_CA_DLL2_RG_ARCMD_REV, 0x1); |
| SET32_BITFIELDS(&ch[chn].ao.dummy_rd, DUMMY_RD_DQSG_DMYRD_EN, 0); |
| SET32_BITFIELDS(&ch[chn].ao.dramc_dbg_sel1, |
| DRAMC_DBG_SEL1_DEBUG_SEL_0, 0x1e); |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl2, SWCMD_CTRL2_RTSWCMD_AGE, 0x20); |
| SET32_BITFIELDS(&ch[chn].ao.rtmrw_ctrl0, RTMRW_CTRL0_RTMRW_AGE, 0x20); |
| SET32_BITFIELDS(&ch[chn].ao.dllfrz_ctrl, |
| DLLFRZ_CTRL_DLLFRZ, 0, |
| DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT, 0); |
| SET32_BITFIELDS(&ch[chn].ao.mpc_ctrl, |
| MPC_CTRL_RTSWCMD_HPRI_EN, 1, |
| MPC_CTRL_RTMRW_HPRI_EN, 1); |
| SET32_BITFIELDS(&ch[chn].ao.hw_mrr_fun, |
| HW_MRR_FUN_R2MRRHPRICTL, 0, |
| HW_MRR_FUN_TR2MRR_ENA, 0); |
| SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, |
| ACTIMING_CTRL_REFNA_OPT, 1, |
| ACTIMING_CTRL_SEQCLKRUN3, 1); |
| SET32_BITFIELDS(&ch[chn].ao.ckectrl, CKECTRL_RUNTIMEMRRCKEFIX, 1); |
| SET32_BITFIELDS(&ch[chn].ao.dvfs_ctrl0, |
| DVFS_CTRL0_DVFS_SYNC_MASK, 0, |
| DVFS_CTRL0_R_DVFS_SREF_OPT, 1); |
| SET32_BITFIELDS(&ch[chn].ao.dvfs_timing_ctrl1, |
| DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT, 1); |
| SET32_BITFIELDS(&ch[chn].ao.hmr4, |
| HMR4_REFRCNT_OPT, 1, |
| HMR4_REFR_PERIOD_OPT, 0, |
| HMR4_SPDR_MR4_OPT, 1, |
| HMR4_HMR4_TOG_OPT, 0); |
| SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_SMRR_UPD_OLD, 0); |
| SET32_BITFIELDS(&ch[chn].ao.dramctrl, DRAMCTRL_SHORTQ_OPT, 1); |
| SET32_BITFIELDS(&ch[chn].ao.misctl0, |
| MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 1); |
| SET32_BITFIELDS(&ch[chn].ao.perfctl0, PERFCTL0_EBG_EN, 0); |
| SET32_BITFIELDS(&ch[chn].ao.clkar, |
| CLKAR_REQQUECLKRUN, 1, |
| CLKAR_REQQUE_PACG_DIS, 0x7fff); |
| SET32_BITFIELDS(&ch[chn].ao.refctrl0, |
| REFCTRL0_PBREF_BK_REFA_ENA, 0, |
| REFCTRL0_PBREF_BK_REFA_NUM, 0); |
| SET32_BITFIELDS(&ch[chn].ao.refctrl1, |
| REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA, 0); |
| SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPB2AB_IGZQCS, 0); |
| SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPENDINGINT_OPT1, 1); |
| SET32_BITFIELDS(&ch[chn].ao.ref_bounce1, |
| REF_BOUNCE1_REFRATE_DEBOUNCE_TH, 5); |
| SET32_BITFIELDS(&ch[chn].ao.refpend2, REFPEND2_MPENDREFCNT_TH8, 8); |
| SET32_BITFIELDS(&ch[chn].ao.scsmctrl, SCSMCTRL_SC_PG_MAN_DIS, 0); |
| SET32_BITFIELDS(&ch[chn].ao.scsmctrl_cg, |
| SCSMCTRL_CG_SCSM_CGAR, 1, |
| SCSMCTRL_CG_SCARB_SM_CGAR, 1); |
| SET32_BITFIELDS(&ch[chn].ao.rtswcmd_cnt, |
| RTSWCMD_CNT_RTSWCMD_CNT, 0x30); |
| SET32_BITFIELDS(&ch[chn].ao.dramc_irq_en, |
| DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV, 0x3fff); |
| SET32_BITFIELDS(&ch[chn].ao.shu_dcm_ctrl0, |
| SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 1); |
| SET32_BITFIELDS(&ch[chn].ao.shu_hmr4_dvfs_ctrl0, |
| SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x1ff, |
| SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0); |
| SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg, |
| SHU_HWSET_VRCG_VRCGDIS_PRDCNT, 11); |
| SET32_BITFIELDS(&ch[chn].ao.shu_misc, SHU_MISC_REQQUE_MAXCNT, 2); |
| SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dll_arpi4, |
| B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0, 1, |
| B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dll_arpi4, |
| B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1, 1, |
| B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.ca_dll_arpi4, |
| CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA, 1, |
| CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd11, |
| CA_CMD11_RG_RRESETB_DRVN, 0xa, |
| CA_CMD11_RG_RRESETB_DRVP, 0xa); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, |
| MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 0x1f); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl9, |
| MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF, 0, |
| MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF, 0, |
| MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN, 0, |
| MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF, 0, |
| MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF, 0, |
| MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN, 0, |
| MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF, 0, |
| MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF, 0, |
| MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN, 0, |
| MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN, 0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, |
| MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE, 1, |
| MISC_DVFSCTL2_RG_DLL_SHUFFLE, 0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl3, |
| MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 0x10, |
| MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE, 1, |
| MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI, 3, |
| MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 1, |
| MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_ddr_reserve, |
| MISC_DDR_RESERVE_WDT_CONF_ISO_CNT, 0xf); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, |
| MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT, 1, |
| MISC_IMP_CTRL1_IMP_ABN_LAT_CLR, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, |
| MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV, 1, |
| MISC_IMPCAL_IMPCAL_DRVUPDOPT, 1, |
| MISC_IMPCAL_IMPBINARY, 1, |
| MISC_IMPCAL_DQDRVSWUPD, 1, |
| MISC_IMPCAL_DRVCGWREF, 0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_dutyscan1, |
| MISC_DUTYSCAN1_EYESCAN_DQS_OPT, 1, |
| MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfs_emi_clk, |
| MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY, 0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl0, |
| MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT, 0, |
| MISC_CTRL0_IMPCAL_CDC_ECO_OPT, 1, |
| MISC_CTRL0_IMPCAL_LP_ECO_OPT, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl4, |
| MISC_CTRL4_R_OPT2_CG_CS, 0, |
| MISC_CTRL4_R_OPT2_CG_CLK, 0, |
| MISC_CTRL4_R_OPT2_CG_CMD, 0, |
| MISC_CTRL4_R_OPT2_CG_DQSIEN, 0, |
| MISC_CTRL4_R_OPT2_CG_DQ, 0, |
| MISC_CTRL4_R_OPT2_CG_DQS, 0, |
| MISC_CTRL4_R_OPT2_CG_DQM, 0, |
| MISC_CTRL4_R_OPT2_CG_MCK, 0, |
| MISC_CTRL4_R_OPT2_MPDIV_CG, 0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl6, |
| MISC_CTRL6_RG_ADA_MCK8X_EN_SHU_OPT, 1, |
| MISC_CTRL6_RG_PHDET_EN_SHU_OPT, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_rx_autok_cfg0, |
| MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq1, |
| SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0, 1, |
| SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0, 1, |
| SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq1, |
| SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1, 1, |
| SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1, 1, |
| SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq10, |
| SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0, 1, |
| SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0, 1, |
| SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq10, |
| SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1, 1, |
| SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1, 1, |
| SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq11, |
| SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0, dq_bw_sel_b0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq11, |
| SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1, dq_bw_sel_b1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd11, |
| SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA, ca_bw_sel_ca); |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd10, |
| SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA, clk_bw_sel_ca); |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd1, |
| SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA, 1, |
| SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd8, |
| SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 1, |
| SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 1, |
| SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 1, |
| SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 1, |
| SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 1, |
| SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 1, |
| SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 1, |
| SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12, |
| SHU_CA_CMD12_RG_RIMP_REV, 0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_impedamce_upd_dis1, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_ODTN_UPD_DIS, 1, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVN_UPD_DIS, 1, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVP_UPD_DIS, 1, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_ODTN_UPD_DIS, 1, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS, 1, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl, |
| MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY, 0, |
| MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 2, |
| MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT, 0, |
| MISC_SHU_RX_CG_CTRL_RX_DCM_OPT, 0); |
| } |
| |
| dramc_set_broadcast(bc_bak); |
| } |
| |
| static void rx_picg_setting(const struct ddr_cali *cali) |
| { |
| u8 talk_lat = (get_div_mode(cali) == DIV4_MODE) ? 1 : 0; |
| |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, |
| MISC_SHU_STBCAL_STBCALEN, 0); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, |
| MISC_SHU_STBCAL_STB_SELPHCALEN, 0); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal1, |
| MISC_STBCAL1_STBCNT_SHU_RST_EN, 1); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2, |
| MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN, 1); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, |
| MISC_SHU_STBCAL_DQSIEN_PICG_MODE, 1); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_gate_en_ctrl, |
| MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT, 1); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_buff_en_ctrl, |
| MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT, 1); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2, |
| MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN, 0); |
| for (u8 rk = 0; rk < cali->support_ranks; rk++) |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[rk].misc_shu_rk_dqsien_picg_ctrl, |
| MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT, talk_lat, |
| MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT, 0); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_buff_en_ctrl, |
| MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN, 0, |
| MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN, 0, |
| MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN, 0); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_gate_en_ctrl, |
| MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN, 0, |
| MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN, 0, |
| MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN, 0); |
| } |
| |
| static void dqs_stb_settings(void) |
| { |
| u32 dqsien_mode = 1; |
| |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, |
| MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE, dqsien_mode); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq10, |
| SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0, dqsien_mode); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq10, |
| SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1, dqsien_mode); |
| } |
| |
| static void rodt_settings(const struct ddr_cali *cali) |
| { |
| u8 vref_sel; |
| u8 odt_onoff = get_odt_state(cali); |
| if (get_odt_state(cali) == ODT_ON) |
| vref_sel = 0x2c; |
| else |
| vref_sel = 0x37; |
| |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, |
| B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1); |
| SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, |
| B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_vref, |
| SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0, !odt_onoff); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_vref, |
| SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1, !odt_onoff); |
| |
| for (u8 rk = 0; rk < cali->support_ranks; rk++) { |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[rk].shu_b0_phy_vref_sel, |
| RG_RX_ARDQ_VREF_SEL_LB_B0, vref_sel, |
| RG_RX_ARDQ_VREF_SEL_UB_B0, vref_sel); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[rk].shu_b0_phy_vref_sel, |
| RG_RX_ARDQ_VREF_SEL_LB_B1, vref_sel, |
| RG_RX_ARDQ_VREF_SEL_UB_B1, vref_sel); |
| } |
| |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_vref, |
| SHU_B0_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B0, 1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_vref, |
| SHU_B1_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B1, 1); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, MISC_SHU_ODTCTRL_RODTEN, 1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, SHU_B0_DQ7_R_DMRODTEN_B0, 1); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, SHU_B1_DQ7_R_DMRODTEN_B1, 1); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rodtenstb, |
| MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN, 1, |
| MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL, 1, |
| MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME, 0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13, |
| SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0, !odt_onoff); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13, |
| SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1, !odt_onoff); |
| SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13, |
| SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA, !odt_onoff); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13, |
| SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0, 0, |
| SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0, 0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14, |
| SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0, 0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13, |
| SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1, 0, |
| SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1, 0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14, |
| SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1, 0); |
| } |
| |
| void dramc_cmd_ui_delay_setting(u8 chn, u8 value) |
| { |
| SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca7, |
| SHU_SELPH_CA7_DLY_RA0, value, |
| SHU_SELPH_CA7_DLY_RA1, value, |
| SHU_SELPH_CA7_DLY_RA2, value, |
| SHU_SELPH_CA7_DLY_RA3, value, |
| SHU_SELPH_CA7_DLY_RA4, value, |
| SHU_SELPH_CA7_DLY_RA5, value, |
| SHU_SELPH_CA7_DLY_RA6, value); |
| SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca5, SHU_SELPH_CA5_DLY_CKE, value); |
| SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca6, SHU_SELPH_CA6_DLY_CKE1, value); |
| } |
| |
| void cbt_delay_ca_clk(u8 chn, u8 rank, s32 delay) |
| { |
| if (delay < 0) |
| /* Set CLK delay */ |
| SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rank].shu_r0_ca_cmd0, |
| SHU_R0_CA_CMD0_RG_ARPI_CMD, 0, |
| SHU_R0_CA_CMD0_RG_ARPI_CLK, -delay, |
| SHU_R0_CA_CMD0_RG_ARPI_CS, -delay); |
| else |
| /* Set CA output delay */ |
| SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rank].shu_r0_ca_cmd0, |
| SHU_R0_CA_CMD0_RG_ARPI_CMD, delay, |
| SHU_R0_CA_CMD0_RG_ARPI_CLK, 0, |
| SHU_R0_CA_CMD0_RG_ARPI_CS, 0); |
| } |
| |
| static void set_mck_8x_low_pwr_option(void) |
| { |
| const u32 mck_8x_mode = 1; |
| |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_lp_ctrl, |
| MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL, mck_8x_mode, |
| MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL, mck_8x_mode, |
| MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL, mck_8x_mode, |
| MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL, mck_8x_mode, |
| MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL, mck_8x_mode, |
| MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL, mck_8x_mode, |
| MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL, mck_8x_mode); |
| } |
| |
| static void update_initial_settings(const struct ddr_cali *cali) |
| { |
| const u8 ca_pi = 0, ca_ui = 1; |
| u8 fsp = get_fsp(cali); |
| dram_freq_grp freq_group = get_freq_group(cali); |
| u8 buf_en_head; |
| |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl3, MISC_CTRL3_ARPI_CG_CLK_OPT, 0); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl4, MISC_CTRL4_R_OPT2_CG_CLK, 0); |
| |
| replace_dv_init(cali); |
| |
| SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd14, |
| SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA, 0xc0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, |
| SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, |
| SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0); |
| SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, |
| SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, |
| SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0); |
| |
| rx_picg_setting(cali); |
| dramc_sw_impedance_save_register(cali); |
| dqs_stb_settings(); |
| rodt_settings(cali); |
| SET32_BITFIELDS(&ch[0].ao.shu_tx_set0, SHU_TX_SET0_DBIWR, 0x0); |
| |
| dramc_cmd_ui_delay_setting(CHANNEL_A, ca_ui); |
| SET32_BITFIELDS(&ch[0].ao.shu_selph_ca5, |
| SHU_SELPH_CA5_DLY_CS, 0x1, |
| SHU_SELPH_CA5_DLY_CS1, 0x1); |
| |
| for (u8 rk = 0; rk < cali->support_ranks; rk++) |
| cbt_delay_ca_clk(CHANNEL_A, rk, ca_pi); |
| |
| SET32_BITFIELDS(&ch[0].ao.refctrl1, REFCTRL1_REF_OVERHEAD_PBR2PB_ENA, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.misctl0, MISCTL0_REFP_ARBMASK_PBR2PBR_ENA, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.scheduler_com, SCHEDULER_COM_PBR2PBR_OPT, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.shu_tx_set0, SHU_TX_SET0_WPST1P5T, fsp); |
| SET32_BITFIELDS(&ch[0].ao.dummy_rd, |
| DUMMY_RD_DMYRD_REORDER_DIS, 0x1, |
| DUMMY_RD_SREF_DMYRD_EN, 0x1); |
| SET32_BITFIELDS(&ch[0].ao.dramctrl, |
| DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN, 0x0, |
| DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN, 0x1, |
| DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN, 0x1); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2, MISC_STBCAL2_DQSGCNT_BYP_REF, 1); |
| |
| if (freq_group <= DDRFREQ_800) |
| buf_en_head = 0; |
| else if (freq_group <= DDRFREQ_1200) |
| buf_en_head = 1; |
| else |
| buf_en_head = 2; |
| |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, |
| MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, buf_en_head); |
| |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMARPIDQ_SW, 1); |
| SET32_BITFIELDS(&ch[0].phy_ao.ca_tx_mck, |
| CA_TX_MCK_R_DMRESETB_DRVP_FRPHY, 0xa, |
| CA_TX_MCK_R_DMRESETB_DRVN_FRPHY, 0xa); |
| SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x3, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x3, |
| MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x3); |
| set_mck_8x_low_pwr_option(); |
| } |
| |
| static void dramc_setting(const struct ddr_cali *cali) |
| { |
| dram_freq_grp freq_group = cali->freq_group; |
| |
| dramc_set_broadcast(DRAMC_BROADCAST_ON); |
| switch (freq_group) { |
| case DDRFREQ_400: |
| sv_algorithm_assistance_lp4_800(); |
| break; |
| case DDRFREQ_600: |
| case DDRFREQ_800: |
| case DDRFREQ_933: |
| case DDRFREQ_1200: |
| sv_algorithm_assistance_lp4_1600(); |
| break; |
| case DDRFREQ_1600: |
| sv_algorithm_assistance_lp4_3733(); |
| break; |
| case DDRFREQ_2133: |
| sv_algorithm_assistance_lp4_4266(); |
| break; |
| default: |
| die("Invalid DDR frequency group %u\n", freq_group); |
| return; |
| } |
| |
| update_initial_settings(cali); |
| dramc_set_broadcast(DRAMC_BROADCAST_OFF); |
| } |
| |
| void cke_fix_onoff(const struct ddr_cali *cali, u8 chn, u8 rank, int option) |
| { |
| u8 cke_on = 0, cke_off = 0; |
| bool set_rank1 = (rank == RANK_MAX) && (cali->support_ranks == DUAL_RANK_DDR); |
| |
| if (option != CKE_DYNAMIC) { |
| cke_on = option; |
| cke_off = 1 - option; |
| } |
| |
| if (rank == RANK_0 || rank == RANK_MAX) { |
| SET32_BITFIELDS(&ch[chn].ao.ckectrl, |
| CKECTRL_CKEFIXOFF, cke_off, |
| CKECTRL_CKEFIXON, cke_on); |
| } |
| if (rank == RANK_1 || set_rank1) { |
| SET32_BITFIELDS(&ch[chn].ao.ckectrl, |
| CKECTRL_CKE1FIXOFF, cke_off, |
| CKECTRL_CKE1FIXON, cke_on); |
| } |
| } |
| |
| static void dramc_power_on_sequence(const struct ddr_cali *cali) |
| { |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, |
| MISC_CTRL1_R_DMDA_RRESETB_I, 0x0); |
| cke_fix_onoff(cali, chn, RANK_MAX, CKE_FIXOFF); |
| udelay(200); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, |
| MISC_CTRL1_R_DMDA_RRESETB_I, 0x1); |
| SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, |
| DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 1); |
| SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, |
| DRAMC_PD_CTRL_TCKFIXON, 1); |
| mdelay(2); |
| cke_fix_onoff(cali, chn, RANK_MAX, CKE_FIXON); |
| udelay(2); |
| SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, |
| DRAMC_PD_CTRL_TCKFIXON, 0); |
| SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, |
| DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0); |
| } |
| } |
| |
| static void dramc_zq_calibration(const struct ddr_cali *cali, u8 chn, u8 rank) |
| { |
| const u32 timeout = 100; |
| |
| struct reg_bak regs_bak[] = { |
| {&ch[chn].ao.swcmd_en}, |
| {&ch[chn].ao.swcmd_ctrl0}, |
| {&ch[chn].ao.dramc_pd_ctrl}, |
| {&ch[chn].ao.ckectrl}, |
| }; |
| |
| for (int i = 0; i < ARRAY_SIZE(regs_bak); i++) |
| regs_bak[i].value = read32(regs_bak[i].addr); |
| |
| SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 1); |
| SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_TCKFIXON, 1); |
| udelay(1); |
| cke_fix_onoff(cali, chn, rank, CKE_FIXON); |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_SWTRIG_ZQ_RK, rank); |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQCEN_SWTRIG, 1); |
| if (!wait_us(timeout, READ32_BITFIELD(&ch[chn].nao.spcmdresp3, |
| SPCMDRESP3_ZQC_SWTRIG_RESPONSE))) { |
| dramc_err("ZQCAL Start failed (time out)\n"); |
| return; |
| } |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQCEN_SWTRIG, 0); |
| |
| udelay(1); |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQLATEN_SWTRIG, 1); |
| if (!wait_us(timeout, READ32_BITFIELD(&ch[chn].nao.spcmdresp3, |
| SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE))) { |
| dramc_err("ZQCAL Latch failed (time out)\n"); |
| return; |
| } |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQLATEN_SWTRIG, 0); |
| |
| udelay(1); |
| for (int i = 0; i < ARRAY_SIZE(regs_bak); i++) |
| write32(regs_bak[i].addr, regs_bak[i].value); |
| } |
| |
| u8 dramc_mode_reg_read(u8 chn, u8 mr_idx) |
| { |
| const u32 timeout = 10000; |
| u8 value; |
| |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSMA, mr_idx); |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 1); |
| |
| /* Wait until MRW command fired */ |
| if (!wait_ms(timeout, READ32_BITFIELD(&ch[chn].nao.spcmdresp, |
| SPCMDRESP_MRR_RESPONSE))) { |
| dramc_err("Read mode register time out\n"); |
| return -1; |
| } |
| |
| value = READ32_BITFIELD(&ch[chn].nao.mrr_status, MRR_STATUS_MRR_SW_REG); |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 0); |
| dramc_dbg("Read MR%d = %#x\n", mr_idx, value); |
| |
| return value; |
| } |
| |
| u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx) |
| { |
| u8 value; |
| u8 rank_bak; |
| |
| rank_bak = READ32_BITFIELD(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK); |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank); |
| value = dramc_mode_reg_read(chn, mr_idx); |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank_bak); |
| |
| return value; |
| } |
| |
| void dramc_mode_reg_write_by_rank(const struct ddr_cali *cali, |
| u8 chn, u8 rank, u8 mr_idx, u8 value) |
| { |
| u32 bk_bak, ckectrl_bak; |
| dramc_info("MRW CH%d RK%d MR%d = %#x\n", chn, rank, mr_idx, value); |
| |
| bk_bak = READ32_BITFIELD(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK); |
| ckectrl_bak = read32(&ch[chn].ao.ckectrl); |
| |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank); |
| cke_fix_onoff(cali, chn, rank, CKE_FIXON); |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSMA, mr_idx); |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSOP, value); |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRWEN, 1); |
| while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRW_RESPONSE) == 0) |
| udelay(1); |
| |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRWEN, 0); |
| write32(&ch[chn].ao.ckectrl, ckectrl_bak); |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, bk_bak); |
| } |
| |
| void cbt_switch_freq(const struct ddr_cali *cali, cbt_freq freq) |
| { |
| static u8 _cur_freq = CBT_UNKNOWN_FREQ; |
| |
| /* if frequency is the same as before, do nothing */ |
| if (_cur_freq == freq) |
| return; |
| _cur_freq = freq; |
| |
| enable_dfs_hw_mode_clk(); |
| |
| if (freq == CBT_LOW_FREQ) |
| dramc_dfs_direct_jump_rg_mode(cali, DRAM_DFS_SHU1); |
| else |
| dramc_dfs_direct_jump_rg_mode(cali, DRAM_DFS_SHU0); |
| |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl, |
| MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 0, |
| MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0); |
| } |
| |
| static void dramc_mode_reg_init(const struct ddr_cali *cali) |
| { |
| u8 chn; |
| u8 set_mrsrk; |
| u8 operate_fsp = get_fsp(cali); |
| struct mr_values *mr_value = cali->mr_value; |
| |
| u32 bc_bak = dramc_get_broadcast(); |
| dramc_set_broadcast(DRAMC_BROADCAST_OFF); |
| dramc_power_on_sequence(cali); |
| |
| if (get_fsp(cali) == FSP_1) { |
| for (chn = 0; chn < CHANNEL_MAX; chn++) |
| SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, |
| CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1, |
| CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, |
| CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); |
| cbt_switch_freq(cali, CBT_LOW_FREQ); |
| for (chn = 0; chn < CHANNEL_MAX; chn++) |
| SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, |
| CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, |
| CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1, |
| CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); |
| } |
| |
| for (chn = 0; chn < CHANNEL_MAX; chn++) { |
| for (u8 rk = 0; rk < cali->support_ranks; rk++) { |
| dramc_dbg("ModeRegInit CH%u RK%u\n", chn, rk); |
| for (u8 fsp = FSP_0; fsp < FSP_MAX; fsp++) { |
| if (fsp == FSP_0) { |
| dramc_dbg("FSP0\n"); |
| mr_value->mr13[rk] = BIT(4) | BIT(3); |
| mr_value->mr22[fsp] = 0x38; |
| mr_value->mr11[fsp] = 0x0; |
| } else { |
| dramc_dbg("FSP1\n"); |
| mr_value->mr13[rk] |= 0x40; |
| |
| if (cali->cbt_mode[rk] == CBT_NORMAL_MODE) |
| mr_value->mr11[fsp] = 0x3 | 0x40; |
| else |
| mr_value->mr11[fsp] = 0x3 | 0x20; |
| |
| if (rk == RANK_0) |
| mr_value->mr22[fsp] = 0x4; |
| else |
| mr_value->mr22[fsp] = 0x2c; |
| } |
| |
| dramc_mode_reg_write_by_rank(cali, chn, rk, 13, |
| mr_value->mr13[rk]); |
| dramc_mode_reg_write_by_rank(cali, chn, rk, 12, |
| mr_value->mr12[chn][rk][fsp]); |
| dramc_mode_reg_write_by_rank(cali, chn, rk, 1, |
| mr_value->mr01[fsp]); |
| dramc_mode_reg_write_by_rank(cali, chn, rk, 2, |
| mr_value->mr02[fsp]); |
| dramc_mode_reg_write_by_rank(cali, chn, rk, 11, |
| mr_value->mr11[fsp]); |
| dramc_mode_reg_write_by_rank(cali, chn, rk, 21, |
| mr_value->mr21[fsp]); |
| dramc_mode_reg_write_by_rank(cali, chn, rk, 51, |
| mr_value->mr51[fsp]); |
| dramc_mode_reg_write_by_rank(cali, chn, rk, 22, |
| mr_value->mr22[fsp]); |
| dramc_mode_reg_write_by_rank(cali, chn, rk, 14, |
| mr_value->mr14[chn][rk][fsp]); |
| dramc_mode_reg_write_by_rank(cali, chn, rk, 3, |
| mr_value->mr03[fsp]); |
| dramc_mode_reg_write_by_rank(cali, chn, rk, 4, |
| mr_value->mr04[rk]); |
| dramc_mode_reg_write_by_rank(cali, chn, rk, 3, |
| mr_value->mr03[fsp]); |
| } |
| |
| dramc_zq_calibration(cali, chn, rk); |
| |
| if (operate_fsp == FSP_0) |
| mr_value->mr13[rk] &= 0x3f; |
| else |
| mr_value->mr13[rk] |= 0xc0; |
| } |
| |
| if (cali->support_ranks == DUAL_RANK_DDR) |
| set_mrsrk = 0x3; |
| else |
| set_mrsrk = RANK_0; |
| |
| dramc_mode_reg_write_by_rank(cali, chn, set_mrsrk, 13, mr_value->mr13[RANK_0]); |
| |
| SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr13, |
| SHU_HWSET_MR13_HWSET_MR13_OP, mr_value->mr13[RANK_0] | BIT(3), |
| SHU_HWSET_MR13_HWSET_MR13_MRSMA, 13); |
| SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg, |
| SHU_HWSET_VRCG_HWSET_VRCG_OP, mr_value->mr13[RANK_0] | BIT(3), |
| SHU_HWSET_VRCG_HWSET_VRCG_MRSMA, 13); |
| SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr2, |
| SHU_HWSET_MR2_HWSET_MR2_OP, mr_value->mr02[operate_fsp], |
| SHU_HWSET_MR2_HWSET_MR2_MRSMA, 2); |
| } |
| |
| if (operate_fsp == FSP_1) { |
| for (chn = 0; chn < CHANNEL_MAX; chn++) |
| SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, |
| CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1, |
| CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, |
| CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); |
| cbt_switch_freq(cali, CBT_HIGH_FREQ); |
| for (chn = 0; chn < CHANNEL_MAX; chn++) |
| SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, |
| CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, |
| CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1, |
| CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); |
| } |
| |
| for (chn = 0; chn < CHANNEL_MAX; chn++) |
| SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, RANK_0); |
| |
| dramc_set_broadcast(bc_bak); |
| } |
| |
| static void move_dramc_delay(const struct ddr_cali *cali, reg_transfer *ui, |
| reg_transfer *mck, s8 shift_ui) |
| { |
| s32 sum; |
| u8 ui_offset = ui->offset, ui_width = 4, mck_offset = mck->offset, mck_width = 3; |
| u32 *ui_reg = ui->addr, *mck_reg = mck->addr; |
| |
| u32 tmp_ui, tmp_mck, ui_mask, mck_mask; |
| u8 div_shift = get_mck2ui_div_shift(cali); |
| |
| ui_mask = BIT(ui_width) - 1; |
| mck_mask = BIT(mck_width) - 1; |
| tmp_ui = ((read32(ui_reg) >> ui_offset) & ui_mask) & ~(1 << div_shift); |
| tmp_mck = (read32(mck_reg) >> mck_offset) & mck_mask; |
| |
| sum = (tmp_mck << div_shift) + tmp_ui + shift_ui; |
| |
| if (sum < 0) { |
| tmp_ui = 0; |
| tmp_mck = 0; |
| } else { |
| tmp_mck = sum >> div_shift; |
| tmp_ui = sum - (tmp_mck << div_shift); |
| } |
| |
| clrsetbits32(ui_reg, ui_mask << ui_offset, tmp_ui << ui_offset); |
| clrsetbits32(mck_reg, mck_mask << mck_offset, tmp_mck << mck_offset); |
| } |
| |
| void shift_dq_ui(const struct ddr_cali *cali, u8 rk, s8 shift_ui) |
| { |
| u8 chn = cali->chn; |
| reg_transfer ui_regs[] = { |
| {&ch[chn].ao.shu_rk[rk].shurk_selph_dq3, 0}, |
| {&ch[chn].ao.shu_rk[rk].shurk_selph_dq3, 4}, |
| {&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, 0}, |
| {&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, 4} |
| }; |
| reg_transfer mck_regs[] = { |
| {&ch[chn].ao.shu_rk[rk].shurk_selph_dq1, 0}, |
| {&ch[chn].ao.shu_rk[rk].shurk_selph_dq1, 4}, |
| {&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, 0}, |
| {&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, 4} |
| }; |
| |
| for (int idx = 0; idx < ARRAY_SIZE(ui_regs); idx++) |
| move_dramc_delay(cali, &ui_regs[idx], &mck_regs[idx], shift_ui); |
| } |
| |
| static void ddr_update_ac_timing(const struct ddr_cali *cali) |
| { |
| u8 table_idx; |
| const struct ac_timing *ac_tim; |
| const dram_freq_grp freq_group = cali->freq_group; |
| |
| u8 rank_inctl, tx_dly, datlat_dsel; |
| const u8 root = 0; |
| u8 tx_rank_inctl; |
| const u8 tref_bw = 0; |
| u8 tfaw_05t, trrd_05t; |
| u16 xrtwtw, xtrtrt, xrtw2r, xrtr2w, tfaw; |
| u16 trtw, trtw_05t, tmrr2w, trrd; |
| u16 phs_inctl; |
| u32 rank_inctl_root; |
| |
| for (table_idx = 0; table_idx < AC_TIMING_NUMBER; table_idx++) |
| if (ac_timing_tbl[table_idx].freq_group == freq_group && |
| ac_timing_tbl[table_idx].div_mode == get_div_mode(cali) && |
| ac_timing_tbl[table_idx].cbt_mode == get_cbt_mode(cali)) { |
| dramc_dbg("Found matched AC timing table %u\n", table_idx); |
| break; |
| } |
| |
| if (table_idx == AC_TIMING_NUMBER) { |
| dramc_err("Error: no matched AC timing table found\n"); |
| return; |
| } |
| |
| ac_tim = &ac_timing_tbl[table_idx]; |
| |
| trtw = ac_tim->trtw_odt_on; |
| trtw_05t = ac_tim->trtw_odt_on_05T; |
| xrtw2r = ac_tim->xrtw2r_odt_on; |
| xrtr2w = ac_tim->xrtr2w_odt_on; |
| tfaw = ac_tim->tfaw_4266; |
| tfaw_05t = ac_tim->tfaw_4266_05T; |
| trrd = ac_tim->trrd_4266; |
| trrd_05t = ac_tim->trrd_4266_05T; |
| xtrtrt = ac_tim->xrtr2r_new_mode; |
| xrtwtw = ac_tim->xrtw2w_new_mode; |
| tmrr2w = ac_tim->tmrr2w_odt_on; |
| |
| if (READ32_BITFIELD(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl, |
| SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN)) |
| datlat_dsel = ac_tim->datlat; |
| else |
| datlat_dsel = ac_tim->datlat > 1 ? ac_tim->datlat - 1 : 0; |
| |
| if (ac_tim->dqsinctl >= 2) { |
| rank_inctl_root = ac_tim->dqsinctl - 2; |
| } else { |
| dramc_err("rank_inctl_root <2, need check\n"); |
| rank_inctl_root = 0; |
| } |
| phs_inctl = (ac_tim->dqsinctl == 0) ? 0 : (ac_tim->dqsinctl - 1); |
| |
| if (freq_group <= DDRFREQ_800) { |
| if (get_div_mode(cali) == DIV4_MODE) { |
| tx_rank_inctl = 1; |
| tx_dly = 2; |
| } else { |
| tx_rank_inctl = 0; |
| tx_dly = 1; |
| } |
| } else { |
| tx_rank_inctl = 1; |
| tx_dly = 2; |
| } |
| |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| SET32_BITFIELDS(&ch[chn].ao.shu_actim1, |
| SHU_ACTIM1_TRAS, ac_tim->tras, |
| SHU_ACTIM1_TRP, ac_tim->trp, |
| SHU_ACTIM1_TRPAB, ac_tim->trpab, |
| SHU_ACTIM1_TMRWCKEL, ac_tim->tmrwckel, |
| SHU_ACTIM1_TRC, ac_tim->trc); |
| SET32_BITFIELDS(&ch[chn].ao.shu_actim3, |
| SHU_ACTIM3_TRFC, ac_tim->trfc, |
| SHU_ACTIM3_TR2MRR, ac_tim->tr2mrr, |
| SHU_ACTIM3_TRFCPB, ac_tim->trfcpb); |
| SET32_BITFIELDS(&ch[chn].ao.shu_actim2, |
| SHU_ACTIM2_TXP, ac_tim->txp, |
| SHU_ACTIM2_TMRRI, ac_tim->tmrri, |
| SHU_ACTIM2_TFAW, tfaw, |
| SHU_ACTIM2_TR2W, trtw, |
| SHU_ACTIM2_TRTP, ac_tim->trtp); |
| SET32_BITFIELDS(&ch[chn].ao.shu_actim0, |
| SHU_ACTIM0_TRCD, ac_tim->trcd, |
| SHU_ACTIM0_TWR, ac_tim->twr, |
| SHU_ACTIM0_TRRD, trrd); |
| SET32_BITFIELDS(&ch[chn].ao.shu_actim5, |
| SHU_ACTIM5_TPBR2PBR, ac_tim->tpbr2pbr, |
| SHU_ACTIM5_TWTPD, ac_tim->twtpd, |
| SHU_ACTIM5_TPBR2ACT, ac_tim->tpbr2act); |
| SET32_BITFIELDS(&ch[chn].ao.shu_actim6, |
| SHU_ACTIM6_TR2MRW, ac_tim->tr2mrw, |
| SHU_ACTIM6_TW2MRW, ac_tim->tw2mrw, |
| SHU_ACTIM6_TMRD, ac_tim->tmrd, |
| SHU_ACTIM6_TZQLAT2, ac_tim->zqlat2, |
| SHU_ACTIM6_TMRW, ac_tim->tmrw); |
| SET32_BITFIELDS(&ch[chn].ao.shu_actim4, |
| SHU_ACTIM4_TMRR2MRW, ac_tim->tmrr2mrw, |
| SHU_ACTIM4_TMRR2W, tmrr2w, |
| SHU_ACTIM4_TZQCS, ac_tim->tzqcs, |
| SHU_ACTIM4_TXREFCNT, ac_tim->txrefcnt); |
| SET32_BITFIELDS(&ch[chn].ao.shu_ckectrl, SHU_CKECTRL_TCKEPRD, ac_tim->ckeprd); |
| SET32_BITFIELDS(&ch[chn].ao.shu_actim_xrt, |
| SHU_ACTIM_XRT_XRTW2W, xrtwtw, |
| SHU_ACTIM_XRT_XRTW2R, xrtw2r, |
| SHU_ACTIM_XRT_XRTR2W, xrtr2w, |
| SHU_ACTIM_XRT_XRTR2R, xtrtrt); |
| SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg, |
| SHU_HWSET_VRCG_VRCGDIS_PRDCNT, ac_tim->vrcgdis_prdcnt); |
| SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr2, |
| SHU_HWSET_MR2_HWSET_MR2_OP, ac_tim->hwset_mr2_op); |
| SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr13, |
| SHU_HWSET_MR13_HWSET_MR13_OP, ac_tim->hwset_mr13_op); |
| SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, |
| SHU_AC_TIME_05T_TWTR_M05T, ac_tim->twtr_05T, |
| SHU_AC_TIME_05T_TR2W_05T, trtw_05t, |
| SHU_AC_TIME_05T_TWTPD_M05T, ac_tim->twtpd_05T, |
| SHU_AC_TIME_05T_TFAW_05T, tfaw_05t, |
| SHU_AC_TIME_05T_TRRD_05T, trrd_05t, |
| SHU_AC_TIME_05T_TWR_M05T, ac_tim->twr_05T, |
| SHU_AC_TIME_05T_TRAS_05T, ac_tim->tras_05T, |
| SHU_AC_TIME_05T_TRPAB_05T, ac_tim->trpab_05T, |
| SHU_AC_TIME_05T_TRP_05T, ac_tim->trp_05T, |
| SHU_AC_TIME_05T_TRCD_05T, ac_tim->trcd_05T, |
| SHU_AC_TIME_05T_TRTP_05T, ac_tim->trtp_05T, |
| SHU_AC_TIME_05T_TXP_05T, ac_tim->txp_05T); |
| SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, |
| SHU_AC_TIME_05T_TRFC_05T, ac_tim->trfc_05T, |
| SHU_AC_TIME_05T_TRFCPB_05T, ac_tim->trfcpb_05T, |
| SHU_AC_TIME_05T_TPBR2PBR_05T, ac_tim->tpbr2pbr_05T, |
| SHU_AC_TIME_05T_TPBR2ACT_05T, ac_tim->tpbr2act_05T, |
| SHU_AC_TIME_05T_TR2MRW_05T, ac_tim->tr2mrw_05T, |
| SHU_AC_TIME_05T_TW2MRW_05T, ac_tim->tw2mrw_05T, |
| SHU_AC_TIME_05T_TMRR2MRW_05T, ac_tim->tmrr2mrw_05T, |
| SHU_AC_TIME_05T_TMRW_05T, ac_tim->tmrw_05T, |
| SHU_AC_TIME_05T_TMRD_05T, ac_tim->tmrd_05T, |
| SHU_AC_TIME_05T_TMRWCKEL_05T, ac_tim->tmrwckel_05T, |
| SHU_AC_TIME_05T_TMRRI_05T, ac_tim->tmrri_05T, |
| SHU_AC_TIME_05T_TRC_05T, ac_tim->trc_05T); |
| SET32_BITFIELDS(&ch[chn].ao.shu_actim0, SHU_ACTIM0_TWTR, ac_tim->twtr); |
| SET32_BITFIELDS(&ch[chn].ao.shu_ckectrl, |
| SHU_CKECTRL_TPDE, ac_tim->tpde, |
| SHU_CKECTRL_TPDX, ac_tim->tpdx, |
| SHU_CKECTRL_TPDE_05T, ac_tim->tpde_05T, |
| SHU_CKECTRL_TPDX_05T, ac_tim->tpdx_05T); |
| SET32_BITFIELDS(&ch[chn].ao.shu_actim5, SHU_ACTIM5_TR2PD, ac_tim->trtpd); |
| SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, |
| SHU_AC_TIME_05T_TR2PD_05T, ac_tim->trtpd_05T); |
| SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating0, |
| SHU_AC_DERATING0_TRCD_DERATE, ac_tim->trcd_derate, |
| SHU_AC_DERATING0_TRRD_DERATE, ac_tim->trrd_derate); |
| SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating1, |
| SHU_AC_DERATING1_TRC_DERATE, ac_tim->trc_derate, |
| SHU_AC_DERATING1_TRAS_DERATE, ac_tim->tras_derate, |
| SHU_AC_DERATING1_TRP_DERATE, ac_tim->trp_derate, |
| SHU_AC_DERATING1_TRPAB_DERATE, ac_tim->trpab_derate); |
| SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating_05t, |
| SHU_AC_DERATING_05T_TRRD_05T_DERATE, ac_tim->trrd_derate_05T, |
| SHU_AC_DERATING_05T_TRAS_05T_DERATE, ac_tim->tras_derate_05T, |
| SHU_AC_DERATING_05T_TRPAB_05T_DERATE, ac_tim->trpab_derate_05T, |
| SHU_AC_DERATING_05T_TRP_05T_DERATE, ac_tim->trp_derate_05T, |
| SHU_AC_DERATING_05T_TRCD_05T_DERATE, ac_tim->trcd_derate_05T, |
| SHU_AC_DERATING_05T_TRC_05T_DERATE, ac_tim->trc_derate_05T); |
| SET32_BITFIELDS(&ch[chn].ao.refctrl3, REFCTRL3_REF_DERATING_EN, 0xc0); |
| SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating0, |
| SHU_AC_DERATING0_ACDERATEEN, 0x1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, |
| MISC_SHU_RK_DQSCTL_DQSINCTL, ac_tim->dqsinctl); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, |
| MISC_SHU_RK_DQSCTL_DQSINCTL, ac_tim->dqsinctl); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_odtctrl, |
| MISC_SHU_ODTCTRL_RODT_LAT, ac_tim->dqsinctl); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, |
| MISC_SHU_RANKCTL_RANKINCTL_PHY, ac_tim->dqsinctl, |
| MISC_SHU_RANKCTL_RANKINCTL_ROOT1, rank_inctl_root, |
| MISC_SHU_RANKCTL_RANKINCTL, rank_inctl_root); |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rank_sel_stb, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, phs_inctl); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rdat, |
| MISC_SHU_RDAT_DATLAT, ac_tim->datlat, |
| MISC_SHU_RDAT_DATLAT_DSEL, datlat_dsel, |
| MISC_SHU_RDAT_DATLAT_DSEL_PHY, datlat_dsel); |
| SET32_BITFIELDS(&ch[chn].ao.shu_actiming_conf, |
| SHU_ACTIMING_CONF_REFBW_FR, tref_bw); |
| rank_inctl = READ32_BITFIELD(&ch[0].phy_ao.misc_shu_rankctl, |
| MISC_SHU_RANKCTL_RANKINCTL); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, |
| MISC_SHU_RANKCTL_RANKINCTL_RXDLY, rank_inctl); |
| SET32_BITFIELDS(&ch[chn].ao.shu_tx_rankctl, |
| SHU_TX_RANKCTL_TXRANKINCTL_ROOT, root, |
| SHU_TX_RANKCTL_TXRANKINCTL, tx_rank_inctl, |
| SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, tx_dly); |
| } |
| } |
| |
| static void set_cke2rank_independent(void) |
| { |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_CKE2RANK, 0); |
| SET32_BITFIELDS(&ch[chn].ao.ckectrl, |
| CKECTRL_CKE2RANK_OPT3, 0, |
| CKECTRL_CKE2RANK_OPT, 0, |
| CKECTRL_CKE2RANK_OPT2, 1, |
| CKECTRL_CKE2RANK_OPT5, 0, |
| CKECTRL_CKE2RANK_OPT6, 0, |
| CKECTRL_CKE2RANK_OPT7, 1, |
| CKECTRL_CKE2RANK_OPT8, 0, |
| CKECTRL_CKETIMER_SEL, 0, |
| CKECTRL_FASTWAKE_SEL, 1, |
| CKECTRL_CKEWAKE_SEL, 0); |
| SET32_BITFIELDS(&ch[chn].ao.shu_dcm_ctrl0, |
| SHU_DCM_CTRL0_FASTWAKE, 1, |
| SHU_DCM_CTRL0_FASTWAKE2, 1); |
| SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, ACTIMING_CTRL_CLKWITRFC, 0); |
| } |
| } |
| |
| static void dramc_hw_gating_onoff(bool is_on) |
| { |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, |
| MISC_DVFSCTL2_R_DVFS_OPTION, is_on, |
| MISC_DVFSCTL2_R_DVFS_PARK_N, is_on); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_stbcal2, |
| MISC_STBCAL2_STB_GERRSTOP, is_on); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_stbcal, |
| MISC_SHU_STBCAL_STBCALEN, is_on); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_stbcal, |
| MISC_SHU_STBCAL_STB_SELPHCALEN, is_on); |
| } |
| } |
| |
| static void dramc_reset_delay_chain_before_calibration(void) |
| { |
| u32 bc_bak = dramc_get_broadcast(); |
| dramc_set_broadcast(DRAMC_BROADCAST_OFF); |
| |
| for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| struct ddrphy_ao_regs *phy_ao = &ch[chn].phy_ao; |
| |
| SET32_BITFIELDS(&phy_ao->ca_rk[rk].shu_r0_ca_txdly0, |
| SHU_R0_CA_TXDLY0_TX_ARCA0_DLY, 0, |
| SHU_R0_CA_TXDLY0_TX_ARCA1_DLY, 0, |
| SHU_R0_CA_TXDLY0_TX_ARCA2_DLY, 0, |
| SHU_R0_CA_TXDLY0_TX_ARCA3_DLY, 0); |
| SET32_BITFIELDS(&phy_ao->ca_rk[rk].shu_r0_ca_txdly1, |
| SHU_R0_CA_TXDLY1_TX_ARCA4_DLY, 0, |
| SHU_R0_CA_TXDLY1_TX_ARCA5_DLY, 0, |
| SHU_R0_CA_TXDLY1_TX_ARCA6_DLY, 0, |
| SHU_R0_CA_TXDLY1_TX_ARCA7_DLY, 0); |
| SET32_BITFIELDS(&phy_ao->byte[0].rk[rk].shu_r0_b0_txdly0, |
| SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0, |
| SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0, |
| SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0, |
| SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0); |
| SET32_BITFIELDS(&phy_ao->byte[0].rk[rk].shu_r0_b0_txdly1, |
| SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0, |
| SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0, |
| SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0, |
| SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0); |
| SET32_BITFIELDS(&phy_ao->byte[1].rk[rk].shu_r0_b0_txdly0, |
| SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0, |
| SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0, |
| SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0, |
| SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0); |
| SET32_BITFIELDS(&phy_ao->byte[1].rk[rk].shu_r0_b0_txdly1, |
| SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0, |
| SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0, |
| SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0, |
| SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0); |
| SET32_BITFIELDS(&phy_ao->byte[0].rk[rk].shu_r0_b0_txdly3, |
| SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x0); |
| SET32_BITFIELDS(&phy_ao->byte[1].rk[rk].shu_r0_b0_txdly3, |
| SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x0); |
| } |
| } |
| |
| dramc_set_broadcast(bc_bak); |
| } |
| |
| static void dramc_init(const struct ddr_cali *cali) |
| { |
| dramc_setting(cali); |
| dramc_reset_delay_chain_before_calibration(); |
| dramc_8_phase_cal(cali); |
| dramc_duty_calibration(cali->params); |
| dramc_mode_reg_init(cali); |
| |
| ddr_update_ac_timing(cali); |
| } |
| |
| static void dramc_before_calibration(const struct ddr_cali *cali) |
| { |
| u8 ma_type = get_column_num(); |
| dram_freq_grp freq_group = cali->freq_group; |
| u8 dis_imp_hw = (freq_group > DDRFREQ_1200) ? 0 : 1; |
| |
| dramc_hw_gating_onoff(false); |
| |
| cke_fix_onoff(cali, CHANNEL_A, RANK_MAX, CKE_FIXON); |
| cke_fix_onoff(cali, CHANNEL_B, RANK_MAX, CKE_FIXON); |
| |
| set_cke2rank_independent(); |
| |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| SET32_BITFIELDS(&ch[chn].ao.shu_tx_set0, SHU_TX_SET0_DBIWR, 0x0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_impedamce_upd_dis1, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS, dis_imp_hw, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS, dis_imp_hw, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS, dis_imp_hw, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, dis_imp_hw, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, dis_imp_hw, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, dis_imp_hw, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS, dis_imp_hw, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS, dis_imp_hw, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS, dis_imp_hw, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS, dis_imp_hw, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS, dis_imp_hw, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS, dis_imp_hw, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, 1, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, 1, |
| MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, 1); |
| |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, |
| SHU_MISC_IMPCAL1_IMPCALCNT, dis_imp_hw ? 0x0 : 0x40); |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving1, |
| SHU_MISC_DRVING1_DIS_IMPCAL_HW, dis_imp_hw); |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving1, |
| SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK, dis_imp_hw); |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving2, |
| SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN, dis_imp_hw); |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12, |
| SHU_CA_CMD12_RG_RIMP_UNTERM_EN, dis_imp_hw); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl, |
| MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 0, |
| MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0); |
| SET32_BITFIELDS(&ch[chn].ao.shu_zq_set0, |
| SHU_ZQ_SET0_ZQCSCNT, 0x1ff, |
| SHU_ZQ_SET0_TZQLAT, 0x1b); |
| SET32_BITFIELDS(&ch[chn].ao.zq_set0, |
| ZQ_SET0_ZQCSDUAL, 1, |
| ZQ_SET0_ZQCSMASK_OPT, 0, |
| ZQ_SET0_ZQMASK_CGAR, 0, |
| ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0); |
| } |
| SET32_BITFIELDS(&ch[0].ao.zq_set0, ZQ_SET0_ZQCSMASK, 1); |
| SET32_BITFIELDS(&ch[1].ao.zq_set0, ZQ_SET0_ZQCSMASK, 0); |
| |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| SET32_BITFIELDS(&ch[chn].ao.zq_set0, ZQ_SET0_ZQCS_MASK_SEL, 0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq2, |
| SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 0); |
| SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq2, |
| SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 0); |
| SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl, |
| DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK, 0x0); |
| SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl, |
| DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING, 0); |
| SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 0x1); |
| SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, 0x1); |
| SET32_BITFIELDS(&ch[chn].ao.shu_matype, SHU_MATYPE_MATYPE, ma_type); |
| } |
| tx_path_algorithm(cali); |
| } |
| |
| void dfs_init_for_calibration(const struct ddr_cali *cali) |
| { |
| dramc_init_default_mr_value(cali); |
| dramc_init(cali); |
| dramc_before_calibration(cali); |
| } |
| |
| void tx_picg_setting(const struct ddr_cali *cali) |
| { |
| u32 dqs_oen_final, dq_oen_final; |
| u16 dqs_oen_2t[2], dqs_oen_05t[2], dqs_oen_delay[2]; |
| u16 dq_oen_2t[2], dq_oen_05t[2], dq_oen_delay[2]; |
| u16 comb_tx_sel[2]; |
| u16 shift_dqs_div[2], shift_dq_div[2]; |
| u16 comb_tx_picg_cnt; |
| u8 div_ratio; |
| |
| comb_tx_picg_cnt = 3; |
| if (get_div_mode(cali) == DIV8_MODE) { |
| shift_dqs_div[0] = 10; |
| shift_dqs_div[1] = 6; |
| shift_dq_div[0] = 8; |
| shift_dq_div[1] = 4; |
| div_ratio = 3; |
| } else { |
| shift_dqs_div[0] = 2; |
| shift_dqs_div[1] = 0; |
| shift_dq_div[0] = 0; |
| shift_dq_div[1] = 0; |
| div_ratio = 2; |
| } |
| |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| struct dramc_ao_regs *dramc_ao = &ch[chn].ao; |
| |
| dqs_oen_2t[0] = READ32_BITFIELD(&dramc_ao->shu_selph_dqs0, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS0); |
| dqs_oen_05t[0] = READ32_BITFIELD(&dramc_ao->shu_selph_dqs1, |
| SHU_SELPH_DQS1_DLY_OEN_DQS0); |
| dqs_oen_delay[0] = (dqs_oen_2t[0] << div_ratio) + dqs_oen_05t[0]; |
| dqs_oen_2t[1] = READ32_BITFIELD(&dramc_ao->shu_selph_dqs0, |
| SHU_SELPH_DQS0_TXDLY_OEN_DQS1); |
| dqs_oen_05t[1] = READ32_BITFIELD(&dramc_ao->shu_selph_dqs1, |
| SHU_SELPH_DQS1_DLY_OEN_DQS1); |
| dqs_oen_delay[1] = (dqs_oen_2t[1] << div_ratio) + dqs_oen_05t[1]; |
| |
| dqs_oen_final = MIN(dqs_oen_delay[0], dqs_oen_delay[1]) + 1; |
| |
| comb_tx_sel[0] = (dqs_oen_final > shift_dqs_div[0]) ? |
| ((dqs_oen_final - shift_dqs_div[0]) >> div_ratio) : 0; |
| |
| if (get_div_mode(cali) == DIV4_MODE) |
| comb_tx_sel[1] = 0; |
| else |
| comb_tx_sel[1] = (dqs_oen_final > shift_dqs_div[1]) ? |
| ((dqs_oen_final - shift_dqs_div[1]) >> div_ratio) : 0; |
| |
| SET32_BITFIELDS(&dramc_ao->shu_aphy_tx_picg_ctrl, |
| SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, comb_tx_sel[0], |
| SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, comb_tx_sel[1], |
| SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, comb_tx_picg_cnt); |
| for (int rk = RANK_0; rk < cali->support_ranks; rk++) { |
| dq_oen_2t[0] = READ32_BITFIELD(&dramc_ao->shu_rk[rk].shurk_selph_dq0, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ0); |
| dq_oen_05t[0] = READ32_BITFIELD(&dramc_ao->shu_rk[rk].shurk_selph_dq2, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ0); |
| dq_oen_delay[0] = (dq_oen_2t[0] << div_ratio) + dq_oen_05t[0]; |
| dq_oen_2t[1] = READ32_BITFIELD(&dramc_ao->shu_rk[rk].shurk_selph_dq0, |
| SHURK_SELPH_DQ0_TXDLY_OEN_DQ1); |
| dq_oen_05t[1] = READ32_BITFIELD(&dramc_ao->shu_rk[rk].shurk_selph_dq2, |
| SHURK_SELPH_DQ2_DLY_OEN_DQ1); |
| dq_oen_delay[1] = (dq_oen_2t[1] << div_ratio) + dq_oen_05t[1]; |
| |
| dq_oen_final = MIN(dq_oen_delay[0], dq_oen_delay[1]) + 1; |
| |
| comb_tx_sel[0] = (dq_oen_final > shift_dq_div[0]) ? |
| ((dq_oen_final - shift_dq_div[0]) >> div_ratio) : 0; |
| |
| if (get_div_mode(cali) == DIV4_MODE) |
| comb_tx_sel[1] = 0; |
| else |
| comb_tx_sel[1] = (dq_oen_final > shift_dq_div[1]) ? |
| ((dq_oen_final - shift_dq_div[1]) >> div_ratio) : 0; |
| |
| SET32_BITFIELDS(&dramc_ao->shu_rk[rk].shurk_aphy_tx_picg_ctrl, |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, comb_tx_sel[0], |
| SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, comb_tx_sel[1]); |
| } |
| } |
| } |
| |
| void xrtrtr_shu_setting(const struct ddr_cali *cali) |
| { |
| const dram_freq_grp freq_group = get_freq_group(cali); |
| u8 rk_sel_ui_minus = 0, rk_sel_mck_minus = 0; |
| |
| if (freq_group == DDRFREQ_400) |
| rk_sel_mck_minus = 1; |
| else if (freq_group >= DDRFREQ_1600) |
| rk_sel_ui_minus = 2; |
| |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) |
| SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rank_sel_stb, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, rk_sel_mck_minus, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, rk_sel_ui_minus, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, |
| SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1); |
| } |
| |
| void freq_jump_ratio_calculation(const struct ddr_cali *cali) |
| { |
| u32 src_freq, dst_freq, src_shu, dst_shu, jump_ratio_index; |
| u16 jump_ratio[DRAM_DFS_SHU_MAX] = {0}; |
| |
| jump_ratio_index = 0; |
| src_freq = get_frequency(cali); |
| src_shu = get_shu(cali); |
| |
| if (get_freq_group_by_shu_save(src_shu) != DDRFREQ_400) { |
| for (dst_shu = DRAM_DFS_SHU0; dst_shu < DRAM_DFS_SHU_MAX; dst_shu++) { |
| dst_freq = get_frequency_by_shu(dst_shu); |
| jump_ratio[jump_ratio_index] = |
| DIV_ROUND_CLOSEST(dst_freq * 32, src_freq); |
| |
| dramc_dbg("Jump ratio [%u]: %#x Freq %d -> %d, DDR%u -> DDR%u\n", |
| jump_ratio_index, jump_ratio[jump_ratio_index], |
| src_shu, dst_shu, src_freq << 1, dst_freq << 1); |
| jump_ratio_index++; |
| } |
| } |
| |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| SET32_BITFIELDS(&ch[chn].ao.shu_freq_ratio_set0, |
| SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0, jump_ratio[0], |
| SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1, jump_ratio[1], |
| SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2, jump_ratio[2], |
| SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3, jump_ratio[3]); |
| SET32_BITFIELDS(&ch[chn].ao.shu_freq_ratio_set1, |
| SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4, jump_ratio[4], |
| SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5, jump_ratio[5], |
| SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6, jump_ratio[6]); |
| } |
| } |
| |
| void dramc_hmr4_presetting(const struct ddr_cali *cali) |
| { |
| for (u8 chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) { |
| SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_REFR_PERIOD_OPT, 1); |
| SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_REFRCNT_OPT, 0); |
| SET32_BITFIELDS(&ch[chn].ao.shu_hmr4_dvfs_ctrl0, |
| SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x80); |
| |
| if (get_cbt_mode(cali) == CBT_BYTE_MODE1) |
| SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_HMR4_BYTEMODE_EN, 1); |
| else |
| SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_HMR4_BYTEMODE_EN, 0); |
| |
| SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFRATE_MON_CLR, 0); |
| SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFRATE_MON_CLR, 1); |
| SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFRATE_MON_CLR, 0); |
| } |
| } |
| |
| void dramc_enable_perbank_refresh(bool en) |
| { |
| if (en) { |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| SET32_BITFIELDS(&ch[chn].ao.refctrl0, |
| REFCTRL0_PBREF_BK_REFA_ENA, 1, |
| REFCTRL0_PBREF_BK_REFA_NUM, 2); |
| SET32_BITFIELDS(&ch[chn].ao.refctrl0, |
| REFCTRL0_KEEP_PBREF, 0, |
| REFCTRL0_KEEP_PBREF_OPT, 1); |
| SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPB2AB_IGZQCS, 1); |
| } |
| } |
| |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) |
| SET32_BITFIELDS(&ch[chn].ao.shu_conf0, SHU_CONF0_PBREFEN, en); |
| } |
| |
| void dramc_modified_refresh_mode(void) |
| { |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { |
| SET32_BITFIELDS(&ch[chn].ao.refpend1, |
| REFPEND1_MPENDREFCNT_TH0, 2, |
| REFPEND1_MPENDREFCNT_TH1, 2, |
| REFPEND1_MPENDREFCNT_TH2, 4, |
| REFPEND1_MPENDREFCNT_TH3, 5, |
| REFPEND1_MPENDREFCNT_TH4, 5, |
| REFPEND1_MPENDREFCNT_TH5, 3, |
| REFPEND1_MPENDREFCNT_TH6, 3, |
| REFPEND1_MPENDREFCNT_TH7, 3); |
| SET32_BITFIELDS(&ch[chn].ao.refctrl1, |
| REFCTRL1_REFPEND_OPT1, 1, |
| REFCTRL1_REFPEND_OPT2, 1); |
| SET32_BITFIELDS(&ch[chn].ao.shu_ref0, SHU_REF0_MPENDREF_CNT, 4); |
| } |
| } |
| |
| void dramc_cke_debounce(const struct ddr_cali *cali) |
| { |
| if (get_freq_group(cali) < DDRFREQ_2133) |
| return; |
| |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) |
| for (u8 rk = 0; rk < cali->support_ranks; rk++) |
| SET32_BITFIELDS(&ch[chn].ao.shu_rk[rk].shurk_cke_ctrl, |
| SHURK_CKE_CTRL_CKE_DBE_CNT, 15); |
| } |
| |
| void dramc_hw_dqsosc(const struct ddr_cali *cali, u8 chn) |
| { |
| SET32_BITFIELDS(&ch[chn].ao.tx_freq_ratio_old_mode0, |
| TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT, 1); |
| SET32_BITFIELDS(&ch[chn].ao.tx_tracking_set0, |
| TX_TRACKING_SET0_SHU_PRELOAD_TX_HW, 1, |
| TX_TRACKING_SET0_SHU_PRELOAD_TX_START, 0, |
| TX_TRACKING_SET0_SW_UP_TX_NOW_CASE, 0); |
| |
| SET32_BITFIELDS(&ch[chn].ao.mpc_ctrl, MPC_CTRL_MPC_BLOCKALE_OPT, 1); |
| SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMARPIDQ_SW, 0); |
| SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING, 1); |
| SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_ARUIDQ_SW, 1); |
| SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 0); |
| SET32_BITFIELDS(&ch[chn].ao.rk[0].rk_dqsosc, RK_DQSOSC_DQSOSCR_RK0EN, 1); |
| if (cali->support_ranks == DUAL_RANK_DDR) |
| SET32_BITFIELDS(&ch[chn].ao.rk[1].rk_dqsosc, RK_DQSOSC_DQSOSCR_RK0EN, 1); |
| SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_DRSCLR_RK0_EN, 1); |
| SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSC_CALEN, 1); |
| } |
| |
| void apply_write_dbi_power_improve(bool en) |
| { |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) |
| SET32_BITFIELDS(&ch[chn].ao.dbiwr_protect, |
| DBIWR_PROTECT_DBIWR_OPT_B1, 0, |
| DBIWR_PROTECT_DBIWR_OPT_B0, 0, |
| DBIWR_PROTECT_DBIWR_PINMUX_EN, 0, |
| DBIWR_PROTECT_DBIWR_IMP_EN, en); |
| } |
| |
| void dramc_write_dbi_onoff(u8 onoff) |
| { |
| for (u8 chn = 0; chn < CHANNEL_MAX; chn++) |
| SET32_BITFIELDS(&ch[chn].ao.shu_tx_set0, SHU_TX_SET0_DBIWR, onoff); |
| dramc_info("Dramc Write-DBI: %s\n", (onoff == DBI_ON) ? "on" : "off"); |
| } |