commit 26f97f9532933da3c1d72a7918c8a24457bbc1c0
author Martin Roth <martin@coreboot.org> Fri Oct 01 14:53:22 2021 -0600
committer Martin Roth <martinroth@google.com> Tue Oct 05 18:07:08 2021 +0000
tree 8c25279e58ef541fae197ec193f5642a9b21b2d4
parent 50863daef8ed75c0cb3dfd375e7622c898de5821

src/soc to src/superio: Fix spelling errors

These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/southbridge/intel/bd82x6x/lpc.c

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index b4f0c4c..dfebaf0 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -31,7 +31,7 @@
 typedef struct southbridge_intel_bd82x6x_config config_t;
 
 /**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
  *
  * @param dev PCI device with I/O APIC control registers
  */