src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 1f14c42..3b07a15 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -162,7 +162,7 @@
if (!res)
return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G.
+ // NOTE this will break as soon as the Azalia gets a bar above 4G.
// Is there anything we can do about it?
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index b4f0c4c..dfebaf0 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -31,7 +31,7 @@
typedef struct southbridge_intel_bd82x6x_config config_t;
/**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
*
* @param dev PCI device with I/O APIC control registers
*/
diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c
index 7507cd5..41fc4ee 100644
--- a/src/southbridge/intel/i82371eb/acpi_tables.c
+++ b/src/southbridge/intel/i82371eb/acpi_tables.c
@@ -29,7 +29,7 @@
int numcpus = determine_total_number_of_cores();
printk(BIOS_DEBUG, "Found %d CPU(s).\n", numcpus);
- /* without the outer scope, furhter ssdt addition will end up
+ /* without the outer scope, further ssdt addition will end up
* within the processor statement */
acpigen_write_scope("\\_SB");
for (cpu=0; cpu < numcpus; cpu++) {
diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index 988d741..5b9f8be 100644
--- a/src/southbridge/intel/i82371eb/smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -27,7 +27,7 @@
* bit25 (lid_pol): 1=invert lid polarity
* bit24 (sm_freeze): 1=freeze idle and standby timers
* bit16 (end of smi): 0=disable smi assertion (cleared by hw)
- * bits8-15,26: global standby timer inital count 127 * 4minutes
+ * bits8-15,26: global standby timer initial count 127 * 4minutes
* bit2 (thrm_pol): 1=active low THRM#
* bit0 (smi_en): 1=disable smi generation upon smi event
*/
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 6ff6064..321c605 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -32,7 +32,7 @@
}
/**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
*
* @param dev PCI device with I/O APIC control registers
*/
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index fde06b4..0473de6 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -190,7 +190,7 @@
if (!res)
return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G.
+ // NOTE this will break as soon as the Azalia gets a bar above 4G.
// Is there anything we can do about it?
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)(uintptr_t)base);
diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c
index ff890a2..90d784c 100644
--- a/src/southbridge/intel/i82801ix/azalia.c
+++ b/src/southbridge/intel/i82801ix/azalia.c
@@ -183,7 +183,7 @@
if (!res)
return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G.
+ // NOTE this will break as soon as the Azalia gets a bar above 4G.
// Is there anything we can do about it?
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c
index 5efbc9f..885c332 100644
--- a/src/southbridge/intel/i82801jx/azalia.c
+++ b/src/southbridge/intel/i82801jx/azalia.c
@@ -183,7 +183,7 @@
if (!res)
return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G.
+ // NOTE this will break as soon as the Azalia gets a bar above 4G.
// Is there anything we can do about it?
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index ef781b7..683715f 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -162,7 +162,7 @@
if (!res)
return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G.
+ // NOTE this will break as soon as the Azalia gets a bar above 4G.
// Is there anything we can do about it?
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 8cc9b42..c14c6a2 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -28,7 +28,7 @@
typedef struct southbridge_intel_ibexpeak_config config_t;
/**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
*
* @param dev PCI device with I/O APIC control registers
*/
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index f3c08d8..d0eb4b3 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -25,7 +25,7 @@
#define NMI_OFF 0
/**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
*
* @param dev PCI device with I/O APIC control registers
*/
diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c
index 82a8f8e..fb4490f 100644
--- a/src/southbridge/intel/lynxpoint/me_status.c
+++ b/src/southbridge/intel/lynxpoint/me_status.c
@@ -187,7 +187,7 @@
break;
default:
- printk(BIOS_DEBUG, "Unknown phase: 0x%02x sate: 0x%02x",
+ printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x",
hfs2->progress_code, hfs2->current_state);
}
printk(BIOS_DEBUG, "\n");
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 598c2dc..7d9fc6d 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -647,7 +647,7 @@
#define SPIBAR16(x) RCBA16((x) + SPIBAR_OFFSET)
#define SPIBAR32(x) RCBA32((x) + SPIBAR_OFFSET)
-/* Reigsters within the SPIBAR */
+/* Registers within the SPIBAR */
#define SSFC 0x91
#define FDOC 0xb0
#define FDOD 0xb4