commit 26f97f9532933da3c1d72a7918c8a24457bbc1c0
author Martin Roth <martin@coreboot.org> Fri Oct 01 14:53:22 2021 -0600
committer Martin Roth <martinroth@google.com> Tue Oct 05 18:07:08 2021 +0000
tree 8c25279e58ef541fae197ec193f5642a9b21b2d4
parent 50863daef8ed75c0cb3dfd375e7622c898de5821

src/soc to src/superio: Fix spelling errors

These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/nvidia/tegra210/sdram.c

diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c
index 8ffa0e5..702897f 100644
--- a/src/soc/nvidia/tegra210/sdram.c
+++ b/src/soc/nvidia/tegra210/sdram.c
@@ -155,7 +155,7 @@
 
 	/*
 	 * Program CMD mapping. Required before brick mapping, else
-	 * we can't gaurantee CK will be differential at all times.
+	 * we can't guarantee CK will be differential at all times.
 	 */
 	write32(&regs->fbio_cfg7, param->EmcFbioCfg7);
 
@@ -979,7 +979,7 @@
 
 	/* Enable EMC pipe clock gating */
 	write32(&regs->cfg_pipe_clk, param->EmcCfgPipeClk);
-	/* Depending on freqency, enable CMD/CLK fdpd */
+	/* Depending on frequency, enable CMD/CLK fdpd */
 	write32(&regs->fdpd_ctrl_cmd_no_ramp, param->EmcFdpdCtrlCmdNoRamp);
 }