src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig
index 4fcbaff..0244b47 100644
--- a/src/soc/nvidia/tegra210/Kconfig
+++ b/src/soc/nvidia/tegra210/Kconfig
@@ -79,7 +79,7 @@
default 0x70006300 if CONSOLE_SERIAL_TEGRA210_UARTD
default 0x70006400 if CONSOLE_SERIAL_TEGRA210_UARTE
help
- Map the UART names to the respective MMIO addres.
+ Map the UART names to the respective MMIO addresses.
config BOOTROM_SDRAM_INIT
bool "SoC BootROM does SDRAM init with full BCT"
diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc
index f76ab34..5846be9 100644
--- a/src/soc/nvidia/tegra210/Makefile.inc
+++ b/src/soc/nvidia/tegra210/Makefile.inc
@@ -137,7 +137,7 @@
tz_size=$(shell printf "%d" $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB))
ifeq ($(shell test $(tz_size) -lt $(req_tz_size) && echo 1), 1)
- $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be atleast as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB")
+ $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be at least as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB")
endif
# BL31 component is placed towards the end of 32-bit address space. This assumes
diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c
index 9c55242..a2b06b1 100644
--- a/src/soc/nvidia/tegra210/dp.c
+++ b/src/soc/nvidia/tegra210/dp.c
@@ -477,7 +477,7 @@
return (link_cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED;
}
-/* Calcuate if given cfg can meet the mode request. */
+/* Calculate if given cfg can meet the mode request. */
/* Return true if mode is possible, false otherwise. */
static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
const struct soc_nvidia_tegra210_config *config,
diff --git a/src/soc/nvidia/tegra210/include/soc/addressmap.h b/src/soc/nvidia/tegra210/include/soc/addressmap.h
index 31ed4f2..bd9a25c 100644
--- a/src/soc/nvidia/tegra210/include/soc/addressmap.h
+++ b/src/soc/nvidia/tegra210/include/soc/addressmap.h
@@ -94,7 +94,7 @@
/* Return total size of DRAM memory configured on the platform. */
int sdram_size_mb(void);
-/* Find memory below and above 4GiB boundary repsectively. All units 1MiB. */
+/* Find memory below and above 4GiB boundary respectively. All units 1MiB. */
void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib);
void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib);
diff --git a/src/soc/nvidia/tegra210/mipi_dsi.c b/src/soc/nvidia/tegra210/mipi_dsi.c
index cd1b822..067dc6d 100644
--- a/src/soc/nvidia/tegra210/mipi_dsi.c
+++ b/src/soc/nvidia/tegra210/mipi_dsi.c
@@ -193,7 +193,7 @@
/*
* DCS long write packets contain the word count in the header
* bytes 1 and 2 and have a payload containing the DCS command
- * byte folowed by word count minus one bytes.
+ * byte followed by word count minus one bytes.
*
* DCS short write packets encode the DCS command and up to
* one parameter in header bytes 1 and 2.
diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c
index 8ffa0e5..702897f 100644
--- a/src/soc/nvidia/tegra210/sdram.c
+++ b/src/soc/nvidia/tegra210/sdram.c
@@ -155,7 +155,7 @@
/*
* Program CMD mapping. Required before brick mapping, else
- * we can't gaurantee CK will be differential at all times.
+ * we can't guarantee CK will be differential at all times.
*/
write32(®s->fbio_cfg7, param->EmcFbioCfg7);
@@ -979,7 +979,7 @@
/* Enable EMC pipe clock gating */
write32(®s->cfg_pipe_clk, param->EmcCfgPipeClk);
- /* Depending on freqency, enable CMD/CLK fdpd */
+ /* Depending on frequency, enable CMD/CLK fdpd */
write32(®s->fdpd_ctrl_cmd_no_ramp, param->EmcFdpdCtrlCmdNoRamp);
}