soc/intel/baytrail: Align whitespace and comments
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
diff --git a/src/soc/intel/baytrail/acpi/device_nvs.asl b/src/soc/intel/baytrail/acpi/device_nvs.asl
index 31f18a0..3722856 100644
--- a/src/soc/intel/baytrail/acpi/device_nvs.asl
+++ b/src/soc/intel/baytrail/acpi/device_nvs.asl
@@ -2,67 +2,67 @@
/* Device Enabled in ACPI Mode */
-S0EN, 8, // SDMA Enable
-S1EN, 8, // I2C1 Enable
-S2EN, 8, // I2C2 Enable
-S3EN, 8, // I2C3 Enable
-S4EN, 8, // I2C4 Enable
-S5EN, 8, // I2C5 Enable
-S6EN, 8, // I2C6 Enable
-S7EN, 8, // I2C7 Enable
-S8EN, 8, // SDMA2 Enable
-S9EN, 8, // SPI Enable
-SAEN, 8, // PWM1 Enable
-SBEN, 8, // PWM2 Enable
-SCEN, 8, // UART2 Enable
-SDEN, 8, // UART2 Enable
-C0EN, 8, // MMC Enable
-C1EN, 8, // SDIO Enable
-C2EN, 8, // SD Card Enable
-LPEN, 8, // LPE Enable
+S0EN, 8, /* SDMA Enable */
+S1EN, 8, /* I2C1 Enable */
+S2EN, 8, /* I2C2 Enable */
+S3EN, 8, /* I2C3 Enable */
+S4EN, 8, /* I2C4 Enable */
+S5EN, 8, /* I2C5 Enable */
+S6EN, 8, /* I2C6 Enable */
+S7EN, 8, /* I2C7 Enable */
+S8EN, 8, /* SDMA2 Enable */
+S9EN, 8, /* SPI Enable */
+SAEN, 8, /* PWM1 Enable */
+SBEN, 8, /* PWM2 Enable */
+SCEN, 8, /* UART2 Enable */
+SDEN, 8, /* UART2 Enable */
+C0EN, 8, /* MMC Enable */
+C1EN, 8, /* SDIO Enable */
+C2EN, 8, /* SD Card Enable */
+LPEN, 8, /* LPE Enable */
/* BAR 0 */
-S0B0, 32, // SDMA BAR0
-S1B0, 32, // I2C1 BAR0
-S2B0, 32, // I2C2 BAR0
-S3B0, 32, // I2C3 BAR0
-S4B0, 32, // I2C4 BAR0
-S5B0, 32, // I2C5 BAR0
-S6B0, 32, // I2C6 BAR0
-S7B0, 32, // I2C7 BAR0
-S8B0, 32, // SDMA2 BAR0
-S9B0, 32, // SPI BAR0
-SAB0, 32, // PWM1 BAR0
-SBB0, 32, // PWM2 BAR0
-SCB0, 32, // UART1 BAR0
-SDB0, 32, // UART2 BAR0
-C0B0, 32, // MMC BAR0
-C1B0, 32, // SDIO BAR0
-C2B0, 32, // SD Card BAR0
-LPB0, 32, // LPE BAR0
+S0B0, 32, /* SDMA BAR0 */
+S1B0, 32, /* I2C1 BAR0 */
+S2B0, 32, /* I2C2 BAR0 */
+S3B0, 32, /* I2C3 BAR0 */
+S4B0, 32, /* I2C4 BAR0 */
+S5B0, 32, /* I2C5 BAR0 */
+S6B0, 32, /* I2C6 BAR0 */
+S7B0, 32, /* I2C7 BAR0 */
+S8B0, 32, /* SDMA2 BAR0 */
+S9B0, 32, /* SPI BAR0 */
+SAB0, 32, /* PWM1 BAR0 */
+SBB0, 32, /* PWM2 BAR0 */
+SCB0, 32, /* UART1 BAR0 */
+SDB0, 32, /* UART2 BAR0 */
+C0B0, 32, /* MMC BAR0 */
+C1B0, 32, /* SDIO BAR0 */
+C2B0, 32, /* SD Card BAR0 */
+LPB0, 32, /* LPE BAR0 */
/* BAR 1 */
-S0B1, 32, // SDMA BAR1
-S1B1, 32, // I2C1 BAR1
-S2B1, 32, // I2C2 BAR1
-S3B1, 32, // I2C3 BAR1
-S4B1, 32, // I2C4 BAR1
-S5B1, 32, // I2C5 BAR1
-S6B1, 32, // I2C6 BAR1
-S7B1, 32, // I2C7 BAR1
-S8B1, 32, // SDMA2 BAR1
-S9B1, 32, // SPI BAR1
-SAB1, 32, // PWM1 BAR1
-SBB1, 32, // PWM2 BAR1
-SCB1, 32, // UART1 BAR1
-SDB1, 32, // UART2 BAR1
-C0B1, 32, // MMC BAR1
-C1B1, 32, // SDIO BAR1
-C2B1, 32, // SD Card BAR1
-LPB1, 32, // LPE BAR1
+S0B1, 32, /* SDMA BAR1 */
+S1B1, 32, /* I2C1 BAR1 */
+S2B1, 32, /* I2C2 BAR1 */
+S3B1, 32, /* I2C3 BAR1 */
+S4B1, 32, /* I2C4 BAR1 */
+S5B1, 32, /* I2C5 BAR1 */
+S6B1, 32, /* I2C6 BAR1 */
+S7B1, 32, /* I2C7 BAR1 */
+S8B1, 32, /* SDMA2 BAR1 */
+S9B1, 32, /* SPI BAR1 */
+SAB1, 32, /* PWM1 BAR1 */
+SBB1, 32, /* PWM2 BAR1 */
+SCB1, 32, /* UART1 BAR1 */
+SDB1, 32, /* UART2 BAR1 */
+C0B1, 32, /* MMC BAR1 */
+C1B1, 32, /* SDIO BAR1 */
+C2B1, 32, /* SD Card BAR1 */
+LPB1, 32, /* LPE BAR1 */
/* Extra */
-LPFW, 32, // LPE BAR2 Firmware
+LPFW, 32, /* LPE BAR2 Firmware */
diff --git a/src/soc/intel/baytrail/acpi/dptf/dptf.asl b/src/soc/intel/baytrail/acpi/dptf/dptf.asl
index 68df275..66bfa45 100644
--- a/src/soc/intel/baytrail/acpi/dptf/dptf.asl
+++ b/src/soc/intel/baytrail/acpi/dptf/dptf.asl
@@ -26,7 +26,8 @@
}
}
- /* Arg0: Buffer containing UUID
+ /*
+ * Arg0: Buffer containing UUID
* Arg1: Integer containing Revision ID of buffer format
* Arg2: Integer containing count of entries in Arg3
* Arg3: Buffer containing list of DWORD capabilities
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index 6cb68ba..c472d06 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -2,56 +2,57 @@
/* Global Variables */
-Name(\PICM, 0) // IOAPIC/8259
+Name(\PICM, 0) /* IOAPIC/8259 */
-/* Global ACPI memory region. This region is used for passing information
+/*
+ * Global ACPI memory region. This region is used for passing information
* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
* Since we don't know where this will end up in memory at ACPI compile time,
* we have to fix it up in coreboot's ACPI creation phase.
*/
+External (NVSA)
-External(NVSA)
OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
- OSYS, 16, // 0x00 - Operating System
- SMIF, 8, // 0x02 - SMI function
- PRM0, 8, // 0x03 - SMI function parameter
- PRM1, 8, // 0x04 - SMI function parameter
- SCIF, 8, // 0x05 - SCI function
- PRM2, 8, // 0x06 - SCI function parameter
- PRM3, 8, // 0x07 - SCI function parameter
- LCKF, 8, // 0x08 - Global Lock function for EC
- PRM4, 8, // 0x09 - Lock function parameter
- PRM5, 8, // 0x0a - Lock function parameter
- P80D, 32, // 0x0b - Debug port (IO 0x80) value
- LIDS, 8, // 0x0f - LID state (open = 1)
- PWRS, 8, // 0x10 - Power State (AC = 1)
- PCNT, 8, // 0x11 - Processor count
- TPMP, 8, // 0x12 - TPM Present and Enabled
- TLVL, 8, // 0x13 - Throttle Level
- PPCM, 8, // 0x14 - Maximum P-state usable by OS
- PM1I, 32, // 0x15 - System Wake Source - PM1 Index
+ OSYS, 16, /* 0x00 - Operating System */
+ SMIF, 8, /* 0x02 - SMI function */
+ PRM0, 8, /* 0x03 - SMI function parameter */
+ PRM1, 8, /* 0x04 - SMI function parameter */
+ SCIF, 8, /* 0x05 - SCI function */
+ PRM2, 8, /* 0x06 - SCI function parameter */
+ PRM3, 8, /* 0x07 - SCI function parameter */
+ LCKF, 8, /* 0x08 - Global Lock function for EC */
+ PRM4, 8, /* 0x09 - Lock function parameter */
+ PRM5, 8, /* 0x0a - Lock function parameter */
+ P80D, 32, /* 0x0b - Debug port (IO 0x80) value */
+ LIDS, 8, /* 0x0f - LID state (open = 1) */
+ PWRS, 8, /* 0x10 - Power State (AC = 1) */
+ PCNT, 8, /* 0x11 - Processor count */
+ TPMP, 8, /* 0x12 - TPM Present and Enabled */
+ TLVL, 8, /* 0x13 - Throttle Level */
+ PPCM, 8, /* 0x14 - Maximum P-state usable by OS */
+ PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */
/* Device Config */
Offset (0x20),
- S5U0, 8, // 0x20 - Enable USB0 in S5
- S5U1, 8, // 0x21 - Enable USB1 in S5
- S3U0, 8, // 0x22 - Enable USB0 in S3
- S3U1, 8, // 0x23 - Enable USB1 in S3
- TACT, 8, // 0x24 - Thermal Active trip point
- TPSV, 8, // 0x25 - Thermal Passive trip point
- TCRT, 8, // 0x26 - Thermal Critical trip point
- DPTE, 8, // 0x27 - Enable DPTF
+ S5U0, 8, /* 0x20 - Enable USB0 in S5 */
+ S5U1, 8, /* 0x21 - Enable USB1 in S5 */
+ S3U0, 8, /* 0x22 - Enable USB0 in S3 */
+ S3U1, 8, /* 0x23 - Enable USB1 in S3 */
+ TACT, 8, /* 0x24 - Thermal Active trip point */
+ TPSV, 8, /* 0x25 - Thermal Passive trip point */
+ TCRT, 8, /* 0x26 - Thermal Critical trip point */
+ DPTE, 8, /* 0x27 - Enable DPTF */
/* Base addresses */
Offset (0x30),
- CMEM, 32, // 0x30 - CBMEM TOC
- TOLM, 32, // 0x34 - Top of Low Memory
- CBMC, 32, // 0x38 - coreboot mem console pointer
+ CMEM, 32, /* 0x30 - CBMEM TOC */
+ TOLM, 32, /* 0x34 - Top of Low Memory */
+ CBMC, 32, /* 0x38 - coreboot mem console pointer */
/* ChromeOS specific */
Offset (0x100),
diff --git a/src/soc/intel/baytrail/acpi/irqlinks.asl b/src/soc/intel/baytrail/acpi/irqlinks.asl
index 527aa58..ef3bdd4 100644
--- a/src/soc/intel/baytrail/acpi/irqlinks.asl
+++ b/src/soc/intel/baytrail/acpi/irqlinks.asl
@@ -5,20 +5,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 1)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTA)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLA, ResourceTemplate()
@@ -27,28 +27,28 @@
})
CreateWordField(RTLA, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTA
+ /* Set the bit from PRTA */
ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
Return (RTLA)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTA)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTA, 0x80)) {
@@ -64,20 +64,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 2)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTB)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLB, ResourceTemplate()
@@ -86,28 +86,28 @@
})
CreateWordField(RTLB, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTB
+ /* Set the bit from PRTB */
ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
Return (RTLB)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTB)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTB, 0x80)) {
@@ -123,20 +123,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 3)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTC)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLC, ResourceTemplate()
@@ -145,28 +145,28 @@
})
CreateWordField(RTLC, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTC
+ /* Set the bit from PRTC */
ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
Return (RTLC)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTC)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTC, 0x80)) {
@@ -182,20 +182,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 4)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTD)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLD, ResourceTemplate()
@@ -204,28 +204,28 @@
})
CreateWordField(RTLD, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTD
+ /* Set the bit from PRTD */
ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
Return (RTLD)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTD)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTD, 0x80)) {
@@ -241,20 +241,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 5)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTE)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLE, ResourceTemplate()
@@ -263,28 +263,28 @@
})
CreateWordField(RTLE, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTE
+ /* Set the bit from PRTE */
ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
Return (RTLE)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTE)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTE, 0x80)) {
@@ -300,20 +300,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 6)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTF)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLF, ResourceTemplate()
@@ -322,28 +322,28 @@
})
CreateWordField(RTLF, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTF
+ /* Set the bit from PRTF */
ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
Return (RTLF)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTF)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTF, 0x80)) {
@@ -359,20 +359,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 7)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTG)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLG, ResourceTemplate()
@@ -381,28 +381,28 @@
})
CreateWordField(RTLG, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTG
+ /* Set the bit from PRTG */
ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
Return (RTLG)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTG)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTG, 0x80)) {
@@ -418,20 +418,20 @@
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 8)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTH)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLH, ResourceTemplate()
@@ -440,28 +440,28 @@
})
CreateWordField(RTLH, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTH
+ /* Set the bit from PRTH */
ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
Return (RTLH)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTH)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTH, 0x80)) {
diff --git a/src/soc/intel/baytrail/acpi/irqroute.asl b/src/soc/intel/baytrail/acpi/irqroute.asl
index 69c7856..41c660f 100644
--- a/src/soc/intel/baytrail/acpi/irqroute.asl
+++ b/src/soc/intel/baytrail/acpi/irqroute.asl
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-// PCI Interrupt Routing
+/* PCI Interrupt Routing */
Method(_PRT)
{
If (PICM) {
diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl
index 02e1085..9b07ab8 100644
--- a/src/soc/intel/baytrail/acpi/lpc.asl
+++ b/src/soc/intel/baytrail/acpi/lpc.asl
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-// Intel LPC Bus Device - 0:1f.0
+/* Intel LPC Bus Device - 0:1f.0 */
Device (LPCB)
{
@@ -10,7 +10,7 @@
#include "acpi/ec.asl"
- Device (DMAC) // DMA Controller
+ Device (DMAC) /* DMA Controller */
{
Name(_HID, EISAID("PNP0200"))
Name(_CRS, ResourceTemplate()
@@ -23,7 +23,7 @@
})
}
- Device (FWH) // Firmware Hub
+ Device (FWH) /* Firmware Hub */
{
Name (_HID, EISAID("INT0800"))
Name (_CRS, ResourceTemplate()
@@ -37,9 +37,9 @@
Name (_HID, EISAID("PNP0103"))
Name (_CID, 0x010CD041)
- Method (_STA, 0) // Device Status
+ Method (_STA, 0) /* Device Status */
{
- Return (0xf) // Enable and show device
+ Return (0xf) /* Enable and show device */
}
Name(_CRS, ResourceTemplate()
@@ -48,7 +48,7 @@
})
}
- Device(PIC) // 8259 Interrupt Controller
+ Device(PIC) /* 8259 Interrupt Controller */
{
Name(_HID,EISAID("PNP0000"))
Name(_CRS, ResourceTemplate()
@@ -74,20 +74,20 @@
})
}
- Device(LDRC) // LPC device: Resource consumption
+ Device(LDRC) /* LPC device: Resource consumption */
{
Name (_HID, EISAID("PNP0C02"))
Name (_UID, 2)
Name (RBUF, ResourceTemplate()
{
- IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
- IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
- IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
+ IO (Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+ IO (Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+ IO (Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
})
Method (_CRS, 0, NotSerialized)
@@ -96,18 +96,20 @@
}
}
- Device (RTC) // Real Time Clock
+ Device (RTC) /* Real Time Clock */
{
Name (_HID, EISAID("PNP0B00"))
Name (_CRS, ResourceTemplate()
{
IO (Decode16, 0x70, 0x70, 1, 8)
-// Disable as Windows doesn't like it, and systems don't seem to use it.
-// IRQNoFlags() { 8 }
+/*
+ * Disable as Windows doesn't like it, and systems don't seem to use it.
+ * IRQNoFlags() { 8 }
+ */
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TIMR) /* Intel 8254 timer */
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
@@ -118,6 +120,6 @@
})
}
- // Include mainboard's superio.asl file.
+ /* Include mainboard's superio.asl file. */
#include "acpi/superio.asl"
}
diff --git a/src/soc/intel/baytrail/acpi/platform.asl b/src/soc/intel/baytrail/acpi/platform.asl
index 4991e36..67b515a 100644
--- a/src/soc/intel/baytrail/acpi/platform.asl
+++ b/src/soc/intel/baytrail/acpi/platform.asl
@@ -2,7 +2,8 @@
#include <southbridge/intel/common/acpi/platform.asl>
-/* The _PTS method (Prepare To Sleep) is called before the OS is
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
*/
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 9c5fa1a..e3997d7 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -5,16 +5,16 @@
Scope(\)
{
- // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
+ /* IO-Trap at 0x800. This is the ACPI->SMI communication interface. */
OperationRegion(IO_T, SystemIO, 0x800, 0x10)
Field(IO_T, ByteAcc, NoLock, Preserve)
{
Offset(0x8),
- TRP0, 8 // IO-Trap at 0x808
+ TRP0, 8 /* IO-Trap at 0x808 */
}
- // Intel Legacy Block
+ /* Intel Legacy Block */
OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Field (ILBS, AnyAcc, NoLock, Preserve)
{
@@ -30,8 +30,8 @@
}
}
-Name(_HID,EISAID("PNP0A08")) // PCIe
-Name(_CID,EISAID("PNP0A03")) // PCI
+Name(_HID,EISAID("PNP0A08")) /* PCIe */
+Name(_CID,EISAID("PNP0A03")) /* PCI */
Name(_BBN, 0)
@@ -152,12 +152,12 @@
Method (_CRS, 0, Serialized)
{
- // Update PCI resource area
+ /* Update PCI resource area */
CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
- // TOLM is BMBOUND accessible from IOSF so is saved in NVS
+ /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */
Store (\TOLM, PMIN)
Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
Add (Subtract (PMAX, PMIN), 1, PLEN)
@@ -182,7 +182,7 @@
Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
})
- // Current Resource Settings
+ /* Current Resource Settings */
Method (_CRS, 0, Serialized)
{
Return(PDRS)
@@ -227,13 +227,13 @@
}
}
-// LPC Bridge 0:1f.0
+/* LPC Bridge 0:1f.0 */
#include "lpc.asl"
-// USB XHCI 0:14.0
+/* USB XHCI 0:14.0 */
#include "xhci.asl"
-// IRQ routing for each PCI device
+/* IRQ routing for each PCI device */
#include "irqroute.asl"
// PCI Express Ports 0:1c.x
@@ -241,16 +241,16 @@
Scope (\_SB)
{
- // GPIO Devices
+ /* GPIO Devices */
#include "gpio.asl"
}
Scope (\_SB.PCI0)
{
- // LPSS Devices
+ /* LPSS Devices */
#include "lpss.asl"
- // SCC Devices
+ /* SCC Devices */
#include "scc.asl"
// LPE Device