mb/purism/librem_cnl: Configure SuperIO for Librem Mini v1/v2
Configure the SuperIO and logical devices in the device tree. This
overrides the power-on default state.
UART1 was already enabled, and if ENABLE_EC_UART1 was selected in
Kconfig, the LPC UART1 I/O range was also already enabled.
The RTC/BRAM interface was enabled (and the BRAM1 base was 0x360 by
default), but the LPC I/O range was not opened previously. Now it is
open and BRAM bank 1 is accessible.
Mouse/Keyboard are not wired to anything on this board and are now
disabled.
UART2, SMFI, power channel 1, and power channel 2 were enabled
previously, but their LPC I/O ranges were not opened and they were not
accessible to the OS. Fan control is performed by the EC on this board
so there is no change.
SWUC and power channels 3-5 were disabled by default, no change.
Change-Id: I58a5a427737f4a2caa64326c110eb53ec00b347d
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
diff --git a/src/mainboard/purism/librem_cnl/Kconfig.name b/src/mainboard/purism/librem_cnl/Kconfig.name
index ad22009..a575e44 100644
--- a/src/mainboard/purism/librem_cnl/Kconfig.name
+++ b/src/mainboard/purism/librem_cnl/Kconfig.name
@@ -2,11 +2,13 @@
bool "Librem Mini"
select BOARD_PURISM_BASEBOARD_LIBREM_CNL
select SOC_INTEL_WHISKEYLAKE
+ select SUPERIO_ITE_IT8528E
config BOARD_PURISM_LIBREM_MINI_V2
bool "Librem Mini v2"
select BOARD_PURISM_BASEBOARD_LIBREM_CNL
select SOC_INTEL_COMETLAKE_1
+ select SUPERIO_ITE_IT8528E
config BOARD_PURISM_LIBREM_14
bool "Librem 14"
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
index 9270313..cab254a 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
@@ -150,5 +150,29 @@
register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
+ device pci 1f.0 on # LPC Bridge
+ chip superio/ite/it8528e
+ device pnp 2e.1 on # UART1
+ io 0x60 = 0x3F8
+ irq 0x70 = 0x04
+ end
+ device pnp 2e.2 off end # UART2
+ device pnp 2e.4 off end # System Wake-Up Control (SWUC)
+ device pnp 2e.5 off end # KBC/Mouse
+ device pnp 2e.6 off end # KBC/Keyboard
+ device pnp 2e.a off end # Consumer IR
+ device pnp 2e.f off end # Shared Memory/Flash Interface (SMFI)
+ device pnp 2e.10 on # RTC-like Timer
+ io 0x62 = 0x360 # BRAM1 I/O base address
+ end
+ device pnp 2e.11 off end # Power Management I/F Channel 1 (PMC1)
+ device pnp 2e.12 off end # Power Management I/F Channel 2 (PMC2)
+ device pnp 2e.13 off end # Serial Peripheral Interface (SSPI)
+ device pnp 2e.14 off end # Platform Environment Control Interface (PECI)
+ device pnp 2e.17 off end # Power Management I/F Channel 3 (PMC3)
+ device pnp 2e.18 off end # Power Management I/F Channel 4 (PMC4)
+ device pnp 2e.19 off end # Power Management I/F Channel 5 (PMC5)
+ end
+ end
end
end