src/mainboard/via/vt8454c/Options.lb

##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
## MA 02110-1301 USA
##

uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses IRQ_SLOT_COUNT
uses HAVE_ACPI_TABLES
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses HAVE_LOW_TABLES

uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET

uses CONFIG_COMPRESS
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses PAYLOAD_SIZE

uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses CONFIG_CBFS

# compiler specifics
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY

# Console specifics
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS

uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_PCI_ROM_RUN
uses CONFIG_CONSOLE_VGA
uses CONFIG_MAX_PCI_BUSES 
uses CONFIG_SMP
uses CONFIG_IOAPIC

uses CONFIG_GDB_STUB

uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_PRINTK_IN_CAR

## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE  = 256*1024

default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xffef0000
#default DCACHE_RAM_BASE=0xffbf0000
#default DCACHE_RAM_BASE=0xfec00000
default DCACHE_RAM_SIZE=0x8000
default CONFIG_USE_PRINTK_IN_CAR=1

###
### Leave this to 0; VGA is handled by seperate code.
###
default CONFIG_PCI_ROM_RUN=0
default CONFIG_CONSOLE_VGA=0

##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1

##
## Use TSC for udelay.
##
default CONFIG_UDELAY_TSC=1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1

##
## Build code to reset the motherboard from linuxBIOS
##
default HAVE_HARD_RESET=1

##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=15

##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1

##
## Build code to load acpi tables
##
default HAVE_ACPI_TABLES=1

##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1

##
## Build code to fill in tables both in low and high memory
##
default HAVE_LOW_TABLES=1


##
## Build code to setup a generic IOAPIC
##
default CONFIG_SMP=1
default CONFIG_IOAPIC=1

###
### LinuxBIOS layout values
###

## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = ROM_IMAGE_SIZE

##
## Use a small 8K stack
##
default STACK_SIZE=0x2000

##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000

##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0

default _RAMBASE = 0x00004000

default CONFIG_ROM_PAYLOAD     = 1

##
## The default compiler
##
default CROSS_COMPILE=""
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"

##
## Set this to the max PCI bus number you 
## would ever use for PCI config IO.
## Setting this number very high will make 
## pci_locate_device take a long time when
## it can't find a device.
##
default CONFIG_MAX_PCI_BUSES = 0x80

##
## Disable the gdb stub by default
## 
default CONFIG_GDB_STUB=0

##
## The Serial Console
##

# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1

## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200

# Select the serial console base port
default TTYS0_BASE=0x3f8

# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3

##
## Select the coreboot loglevel
##
## EMERG      1   system is unusable               
## ALERT      2   action must be taken immediately 
## CRIT       3   critical conditions              
## ERR        4   error conditions                 
## WARNING    5   warning conditions               
## NOTICE     6   normal but significant condition 
## INFO       7   informational                    
## DEBUG      8   debug-level messages             
## SPEW       9   Way too many details             

## Request this level of debugging output
default  DEFAULT_CONSOLE_LOGLEVEL=5
## At a maximum only compile in this level of debugging
default  MAXIMUM_CONSOLE_LOGLEVEL=5

#
# CBFS
# 
default CONFIG_CBFS=1

end