| ## |
| ## Compute the location and size of where this firmware image |
| ## (coreboot plus bootloader) will live in the boot rom chip. |
| ## |
| default ROM_SIZE = 256 * 1024 |
| default ROM_SECTION_SIZE = ROM_IMAGE_SIZE |
| default ROM_SECTION_OFFSET = 0 |
| |
| ## |
| ## Compute the start location and size size of |
| ## The coreboot bootloader. |
| ## |
| default PAYLOAD_SIZE = ( ROM_SIZE - ROM_IMAGE_SIZE ) |
| default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) |
| |
| ## |
| ## Compute where this copy of coreboot will start in the boot rom |
| ## |
| default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) |
| |
| ## |
| ## Compute a range of ROM that can cached to speed up coreboot, |
| ## execution speed. |
| ## |
| ## XIP_ROM_SIZE must be a power of 2. |
| ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE |
| ## |
| default XIP_ROM_SIZE=32*1024 |
| default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) |
| |
| ## |
| ## Set all of the defaults for an x86 architecture |
| ## |
| |
| arch i386 end |
| |
| ## |
| ## Build the objects we have code for in this directory. |
| ## |
| |
| driver mainboard.o |
| if HAVE_PIRQ_TABLE object irq_tables.o end |
| #object reset.o |
| |
| ## |
| ## Romcc output |
| ## |
| makerule ./failover.E |
| depends "$(MAINBOARD)/failover.c ../romcc" |
| action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" |
| end |
| |
| makerule ./failover.inc |
| depends "$(MAINBOARD)/failover.c ../romcc" |
| action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" |
| end |
| |
| makerule ./auto.E |
| depends "$(MAINBOARD)/auto.c option_table.h ../romcc" |
| action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" |
| end |
| makerule ./auto.inc |
| depends "$(MAINBOARD)/auto.c option_table.h ../romcc" |
| action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" |
| end |
| |
| ## |
| ## Build our 16 bit and 32 bit coreboot entry code |
| ## |
| mainboardinit cpu/x86/16bit/entry16.inc |
| mainboardinit cpu/x86/32bit/entry32.inc |
| ldscript /cpu/x86/16bit/entry16.lds |
| ldscript /cpu/x86/32bit/entry32.lds |
| |
| ## |
| ## Build our reset vector (This is where coreboot is entered) |
| ## |
| mainboardinit cpu/x86/16bit/reset16.inc |
| ldscript /cpu/x86/16bit/reset16.lds |
| |
| ### Should this be in the northbridge code? |
| mainboardinit arch/i386/lib/cpu_reset.inc |
| |
| ## |
| ## Include an id string (For safe flashing) |
| ## |
| mainboardinit arch/i386/lib/id.inc |
| ldscript /arch/i386/lib/id.lds |
| |
| ### |
| ### O.k. We aren't just an intermediary anymore! |
| ### |
| |
| ## |
| ## Setup RAM |
| ## |
| mainboardinit cpu/x86/fpu/enable_fpu.inc |
| mainboardinit ./auto.inc |
| |
| ## |
| ## Include the secondary Configuration files |
| ## |
| dir /pc80 |
| config chip.h |
| |
| chip cpu/emulation/qemu-x86 |
| device pci_domain 0 on |
| device pci 0.0 on end |
| |
| chip southbridge/intel/i82371eb # southbridge |
| device pci 01.0 on end |
| device pci 01.1 on end |
| register "ide0_enable" = "1" |
| register "ide1_enable" = "1" |
| end |
| |
| # register "com1" = "{1}" |
| # register "com1" = "{1, 0, 0x3f8, 4}" |
| end |
| end |