| ## |
| ## Compute the location and size of where this firmware image |
| ## (coreboot plus bootloader) will live in the boot rom chip. |
| ## |
| if USE_FALLBACK_IMAGE |
| default ROM_SECTION_SIZE = FALLBACK_SIZE |
| default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) |
| else |
| if CONFIG_CBFS |
| default ROM_SECTION_SIZE = FALLBACK_SIZE |
| default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE ) |
| else |
| default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) |
| default ROM_SECTION_OFFSET = 0 |
| end |
| end |
| |
| ## |
| ## Compute the start location and size size of |
| ## The coreboot bootloader. |
| ## |
| default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) |
| default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) |
| |
| ## |
| ## Compute where this copy of coreboot will start in the boot rom |
| ## |
| default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) |
| |
| ## |
| ## Compute a range of ROM that can cached to speed up coreboot, |
| ## execution speed. |
| ## |
| ## XIP_ROM_SIZE must be a power of 2. |
| ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE |
| ## |
| default XIP_ROM_SIZE = 128 * 1024 |
| default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE ) |