southbridge/amd/sr5650: Add MCFG ACPI table support
As the southbridge largely controls the PCI[e] configuration space
this patch moves the resource allocation from the northbridge
to the southbridge when the extended configuration space region
is enabled.
Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12050
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index 07b4a02..d4355d6 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -34,6 +34,21 @@
extern void set_pcie_dereset(void);
extern void set_pcie_reset(void);
+struct resource * sr5650_retrieve_cpu_mmio_resource() {
+ device_t cpu;
+ struct resource *res;
+
+ for (cpu = all_devices; cpu; cpu = cpu->next) {
+ if (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)
+ continue;
+ res = probe_resource(cpu->bus->dev, 0xc0010058);
+ if (res)
+ return res;
+ }
+
+ return NULL;
+}
+
/* extension registers */
u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
{
@@ -796,6 +811,22 @@
free(root_level);
}
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ struct resource *res;
+ resource_t mmconf_base = EXT_CONF_BASE_ADDRESS;
+
+ if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
+ res = sr5650_retrieve_cpu_mmio_resource();
+ if (res)
+ mmconf_base = res->base;
+
+ current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f);
+ }
+
+ return current;
+}
+
static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current)
{
uint8_t *p;