nb/intel/pineview: Define and use MMCONF_BUS_NUMBER
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Change-Id: Ie967747b4bf559b5aedc67cbcd35bca51f5a692e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49760
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 0b31766..80b4611 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -42,7 +42,7 @@
{
u64 tom, touud;
u32 tomk, tolud, tseg_sizek;
- u32 pcie_config_base, pcie_config_size, cbmem_topk, delta_cbmem;
+ u32 cbmem_topk, delta_cbmem;
u16 index;
const u32 top32memk = 4 * (GiB / KiB);
@@ -115,13 +115,7 @@
(touud - top32memk) / KiB);
}
- if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) {
- printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x size=0x%x\n",
- pcie_config_base, pcie_config_size);
-
- fixed_mem_resource(dev, index++, pcie_config_base / KiB,
- pcie_config_size / KiB, IORESOURCE_RESERVE);
- }
+ mmconf_resource(dev, index++);
add_fixed_resources(dev, index);
}