southbridge/intel: Tidy up preprocessor and headers
Change-Id: I52a7b39566acd64ac21a345046675e05649a40f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34980
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index b91ab15..e56b32b 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -117,6 +117,5 @@
bool docking_supported;
};
-extern struct chip_operations southbridge_intel_lynxpoint_ops;
#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index e3d8f02..bc8d8a1 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -24,7 +24,7 @@
static u16 get_gpio_base(void)
{
-#if defined(__PRE_RAM__) || defined(__SMM__)
+#ifdef __SIMPLE_DEVICE__
return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
#else
return pci_read_config16(pcidev_on_root(0x1f, 0),
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 84032ca..28e3544 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -30,6 +30,7 @@
#include <cpu/x86/smm.h>
#include <cbmem.h>
#include <string.h>
+#include "chip.h"
#include "nvs.h"
#include "pch.h"
#include <arch/acpigen.h>
diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h
index 775b4ec..3b4bd51 100644
--- a/src/southbridge/intel/lynxpoint/me.h
+++ b/src/southbridge/intel/lynxpoint/me.h
@@ -326,17 +326,13 @@
/* Defined in me_status.c for both romstage and ramstage */
void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2);
-#ifdef __PRE_RAM__
void intel_early_me_status(void);
int intel_early_me_init(void);
int intel_early_me_uma_size(void);
int intel_early_me_init_done(u8 status);
-#endif
-#ifdef __SMM__
void intel_me_finalize_smm(void);
void intel_me8_finalize_smm(void);
-#endif
/*
* ME to BIOS Payload Datastructures and definitions. The ordering of the
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 09eeff2..8d86e68 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -35,6 +35,7 @@
#include <elog.h>
#include <halt.h>
+#include "chip.h"
#include "me.h"
#include "pch.h"
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 540a4d3..3f37887 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -88,13 +88,10 @@
#ifndef __ACPI__
-#if defined(__SMM__) && !defined(__ASSEMBLER__)
void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
void usb_ehci_disable(pci_devfn_t dev);
void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
void usb_xhci_route_all(void);
-#endif
-
/* State Machine configuration. */
#define RCBA_REG_SIZE_MASK 0x8000
@@ -135,7 +132,6 @@
u32 or_value;
};
-#if !defined(__ASSEMBLER__)
void pch_config_rcba(const struct rcba_config_instruction *rcba_config);
int pch_silicon_revision(void);
int pch_silicon_id(void);
@@ -169,30 +165,26 @@
void enable_gpe(u32 mask);
void disable_gpe(u32 mask);
-#if !defined(__PRE_RAM__) && !defined(__SMM__)
-#include <device/device.h>
-#include "chip.h"
void pch_enable(struct device *dev);
void pch_disable_devfn(struct device *dev);
u32 pch_iobp_read(u32 address);
void pch_iobp_write(u32 address, u32 data);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-#if CONFIG(ELOG)
void pch_log_state(void);
-#endif
void acpi_create_intel_hpet(acpi_hpet_t * hpet);
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
-#else
void enable_smbus(void);
-void enable_usb_bar(void);
+
+#if ENV_ROMSTAGE
int smbus_read_byte(unsigned device, unsigned address);
+#endif
+
+void enable_usb_bar(void);
int early_pch_init(const void *gpio_map,
const struct rcba_config_instruction *rcba_config);
void pch_enable_lpc(void);
void mainboard_config_superio(void);
-#endif /* !__PRE_RAM__ && !__SMM__ */
-#endif /* __ASSEMBLER__ */
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 2a8b44e..a3b2e09 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -26,6 +26,7 @@
#include <southbridge/intel/common/gpio.h>
#include <stddef.h>
#include <stdint.h>
+#include "chip.h"
#define MAX_NUM_ROOT_PORTS 8
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index fd611ea..aae48e7 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -21,6 +21,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <delay.h>
+#include "chip.h"
#include "pch.h"
typedef struct southbridge_intel_lynxpoint_config config_t;
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index 23d8125..b5ccfa6 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -22,6 +22,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <stdlib.h>
+#include "chip.h"
#include "pch.h"
#include "nvs.h"
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index ddba351..686e06a 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -21,6 +21,7 @@
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
+#include "chip.h"
#include "pch.h"
typedef struct southbridge_intel_lynxpoint_config config_t;