- Fix race condition in option_table.h generation by moving the include
statement to those files that actually need it. This significantly
reduces the number of dependencies, so it's no longer extremely ugly to
specify them manually (see the src/pc80/Makefile.inc portion)
- Add double include guards around option_table.h defines
- Also, drop the AMD DBM690T work around for the issue
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/arch/i386/Makefile.inc b/src/arch/i386/Makefile.inc
index ba64890..6e7864e 100644
--- a/src/arch/i386/Makefile.inc
+++ b/src/arch/i386/Makefile.inc
@@ -206,11 +206,11 @@
$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H)
@printf " CC $(subst $(obj)/,,$(@))\n"
- $(CC) -MMD $(CFLAGS) -I$(src) -I. -c $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
+ $(CC) -MMD $(CFLAGS) -I$(src) -I. -I$(obj) -c $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h
@printf " CC romstage.inc\n"
- $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -c -S $< -o $@
+ $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
@printf " POST romstage.inc\n"
diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c
index f13a62c..b1894ce 100644
--- a/src/cpu/amd/dualcore/dualcore.c
+++ b/src/cpu/amd/dualcore/dualcore.c
@@ -7,6 +7,9 @@
#include "cpu/amd/dualcore/dualcore_id.c"
#include <pc80/mc146818rtc.h>
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
static inline unsigned get_core_num_in_bsp(unsigned nodeid)
{
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index d6f6393..fa0f8b4 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -1,3 +1,7 @@
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
+
//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
#ifndef SET_FIDVID
#if CONFIG_K8_REV_F_SUPPORT == 0
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
index e065989..3e5c197 100644
--- a/src/cpu/amd/quadcore/quadcore.c
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -20,6 +20,9 @@
#include <console/console.h>
#include <pc80/mc146818rtc.h>
#include <northbridge/amd/amdht/ht_wrapper.c>
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
#ifndef SET_NB_CFG_54
#define SET_NB_CFG_54 1
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 0abb2a6..032e385 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -81,14 +81,6 @@
#define PC_CKS_RANGE_END 45
#define PC_CKS_LOC 46
-/* coreboot cmos checksum is usually only built over bytes 49..125
- * LB_CKS_RANGE_START, LB_CKS_RANGE_END and LB_CKS_LOC are defined
- * in option_table.h
- */
-#if CONFIG_HAVE_OPTION_TABLE
-#include <option_table.h>
-#endif
-
#ifndef UTIL_BUILD_OPTION_TABLE
#include <arch/io.h>
static inline unsigned char cmos_read(unsigned char addr)
diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig
index 224a0be..f9d6107 100644
--- a/src/mainboard/amd/dbm690t/Kconfig
+++ b/src/mainboard/amd/dbm690t/Kconfig
@@ -25,12 +25,6 @@
string
default amd/dbm690t
-# This is a temporary fix, and should be removed when the race condition for
-# building option_table.h is fixed.
-config WARNINGS_ARE_ERRORS
- bool
- default n
-
config DCACHE_RAM_BASE
hex
default 0xc8000
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 902e5c2..b3acece 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -43,6 +43,7 @@
#include "superio/winbond/w83627thg/w83627thg.h"
#include <pc80/mc146818rtc.h>
+#include "option_table.h"
#include <console/console.h>
#include <cpu/x86/bist.h>
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index ad787ca..f1f5bbc 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -69,6 +69,9 @@
#include <stdlib.h>
#include "arch/romcc_io.h"
#include <pc80/mc146818rtc.h>
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
#include "amdk8.h"
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index efb7738..a48a835 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -10,6 +10,9 @@
#include <reset.h>
#include "raminit.h"
#include "amdk8.h"
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
# error "CONFIG_RAMTOP must be a power of 2"
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index ff3eb39..916f04d 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -28,6 +28,9 @@
#include "raminit.h"
#include "amdk8_f.h"
#include <spd_ddr2.h>
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
#ifndef QRANK_DIMM_SUPPORT
#define QRANK_DIMM_SUPPORT 0
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 7f1b9d5..0ef73cc 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -23,6 +23,9 @@
#include <stdlib.h>
#include "raminit.h"
#include "e7520.h"
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
#define BAR 0x40000000
@@ -619,11 +622,13 @@
}
ecc = 2;
- if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
+#if CONFIG_HAVE_OPTION_TABLE
+ if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
ecc = 0; /* ECC off in CMOS so disable it */
print_debug("ECC off\n");
- }
- else {
+ } else
+#endif
+ {
print_debug("ECC on\n");
}
drc &= ~(3 << 20); /* clear the ecc bits */
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index be44434..a33b0c7 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -23,6 +23,9 @@
#include <stdlib.h>
#include "raminit.h"
#include "e7525.h"
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
#define BAR 0x40000000
@@ -619,11 +622,13 @@
}
ecc = 2;
+#if CONFIG_HAVE_OPTION_TABLE
if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
ecc = 0; /* ECC off in CMOS so disable it */
print_debug("ECC off\n");
- }
- else {
+ } else
+#endif
+ {
print_debug("ECC on\n");
}
drc &= ~(3 << 20); /* clear the ecc bits */
diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc
index b7890f5..fe7e8e8 100644
--- a/src/pc80/Makefile.inc
+++ b/src/pc80/Makefile.inc
@@ -8,3 +8,4 @@
subdirs-y += vga
$(obj)/pc80/mc146818rtc.o : $(OPTION_TABLE_H)
+$(obj)/pc80/mc146818rtc_early.initobj.o : $(OPTION_TABLE_H)
diff --git a/src/pc80/mc146818rtc.c b/src/pc80/mc146818rtc.c
index 23b834c..ce91325 100644
--- a/src/pc80/mc146818rtc.c
+++ b/src/pc80/mc146818rtc.c
@@ -2,6 +2,9 @@
#include <pc80/mc146818rtc.h>
#include <boot/coreboot_tables.h>
#include <string.h>
+#if CONFIG_USE_OPTION_TABLE
+#include "option_table.h"
+#endif
/* control registers - Moto names
*/
diff --git a/src/pc80/mc146818rtc_early.c b/src/pc80/mc146818rtc_early.c
index ed1f092..d09d6b9 100644
--- a/src/pc80/mc146818rtc_early.c
+++ b/src/pc80/mc146818rtc_early.c
@@ -1,5 +1,8 @@
#include <pc80/mc146818rtc.h>
#include <fallback.h>
+#if CONFIG_USE_OPTION_TABLE
+#include "option_table.h"
+#endif
#ifndef CONFIG_MAX_REBOOT_CNT
#error "CONFIG_MAX_REBOOT_CNT not defined"
diff --git a/src/pc80/serial.c b/src/pc80/serial.c
index 4a4ca68..5e2538e 100644
--- a/src/pc80/serial.c
+++ b/src/pc80/serial.c
@@ -1,6 +1,9 @@
#include <lib.h> /* Prototypes */
#include <arch/io.h>
#include "pc80/mc146818rtc.h"
+#if CONFIG_USE_OPTION_TABLE
+#include "option_table.h"
+#endif
/* Base Address */
#ifndef CONFIG_TTYS0_BASE
diff --git a/util/options/build_opt_tbl.c b/util/options/build_opt_tbl.c
index 2772031..1d218df 100644
--- a/util/options/build_opt_tbl.c
+++ b/util/options/build_opt_tbl.c
@@ -591,6 +591,10 @@
/* Walk through the entry records */
ptr = (struct lb_record *)(cmos_table + hdr->header_length);
end = (struct lb_record *)(cmos_table + hdr->size);
+ fprintf(fp, "/* This file is autogenerated.\n"
+ " * See mainboard's cmos.layout file.\n */\n\n"
+ "#ifndef __OPTION_TABLE_H\n#define __OPTION_TABLE_H\n\n");
+
for(;ptr < end; ptr = (struct lb_record *)(((char *)ptr) + ptr->size)) {
if (ptr->tag != LB_TAG_OPTION) {
continue;
@@ -620,6 +624,7 @@
unlink(tempfilename);
exit(1);
}
+ fprintf(fp, "\n#endif // __OPTION_TABLE_H\n");
fclose(fp);
UNLINK_IF_NECESSARY(header);