| # SPDX-License-Identifier: GPL-2.0-only |
| |
| config CPU_AMD_AGESA |
| bool |
| default n |
| select ARCH_X86 |
| select DRIVERS_AMD_PI |
| select TSC_SYNC_LFENCE |
| select UDELAY_LAPIC |
| select LAPIC_MONOTONIC_TIMER |
| select SPI_FLASH if HAVE_ACPI_RESUME |
| select SSE2 |
| select CACHE_MRC_SETTINGS |
| |
| if CPU_AMD_AGESA |
| |
| config UDELAY_LAPIC_FIXED_FSB |
| int |
| default 200 |
| |
| # TODO: Sync these with definitions in AGESA vendorcode. |
| # DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. |
| # DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. |
| |
| config DCACHE_RAM_BASE |
| hex |
| default 0x30000 |
| |
| config DCACHE_RAM_SIZE |
| hex |
| default 0x10000 |
| |
| config DCACHE_BSP_STACK_SIZE |
| hex |
| default 0x4000 |
| |
| config ENABLE_MRC_CACHE |
| bool "Use cached memory configuration" |
| default n |
| select SPI_FLASH |
| help |
| Try to restore memory training results |
| from non-volatile memory. |
| |
| endif # CPU_AMD_AGESA |