arch/x86/ioapic: use uintptr_t for IOAPIC base address
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC-
related functions to avoid needing type casts in the callers. This also
allows dropping the VIO_APIC_VADDR define and consistently use the
IO_APIC_ADDR define instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I912943e923ff092708e90138caa5e1daf269a69f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
index f6a4ac0..4a25f6b 100644
--- a/src/southbridge/intel/i82870/ioapic.c
+++ b/src/southbridge/intel/i82870/ioapic.c
@@ -6,6 +6,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <assert.h>
+#include <types.h>
#include "82870.h"
static void p64h2_ioapic_enable(struct device *dev)
@@ -27,17 +28,17 @@
*/
static void p64h2_ioapic_init(struct device *dev)
{
- uint32_t memoryBase;
+ uintptr_t memoryBase;
// Read the MBAR address for setting up the IOAPIC in memory space
// NOTE: this address was assigned during enumeration of the bus
- memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ memoryBase = (uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- register_new_ioapic((void *)memoryBase);
+ register_new_ioapic(memoryBase);
// Use Processor System Bus to deliver interrupts
- ioapic_set_boot_config((void *)memoryBase, true);
+ ioapic_set_boot_config(memoryBase, true);
}
static struct device_operations ioapic_ops = {