arch/x86/ioapic: use uintptr_t for IOAPIC base address
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC-
related functions to avoid needing type casts in the callers. This also
allows dropping the VIO_APIC_VADDR define and consistently use the
IO_APIC_ADDR define instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I912943e923ff092708e90138caa5e1daf269a69f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c
index 593f548..70e4985 100644
--- a/src/southbridge/amd/pi/hudson/sm.c
+++ b/src/southbridge/amd/pi/hudson/sm.c
@@ -28,7 +28,7 @@
static void sm_init(struct device *dev)
{
- register_new_ioapic_gsi0(VIO_APIC_VADDR);
+ register_new_ioapic_gsi0(IO_APIC_ADDR);
}
static int lsmbus_recv_byte(struct device *dev)
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 69c9d44..67d883a 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -41,9 +41,9 @@
PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
/* affirm full set of redirection table entries ("write once") */
- ioapic_lock_max_vectors(VIO_APIC_VADDR);
+ ioapic_lock_max_vectors(IO_APIC_ADDR);
- register_new_ioapic_gsi0(VIO_APIC_VADDR);
+ register_new_ioapic_gsi0(IO_APIC_ADDR);
}
static void pch_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index 9d03de0..692fd8b 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -61,8 +61,8 @@
pci_write_config16(dev, XBCS, reg16);
/* Set and verify the IOAPIC ID. */
- setup_ioapic(VIO_APIC_VADDR, ioapic_id);
- if (ioapic_id != get_ioapic_id(VIO_APIC_VADDR))
+ setup_ioapic(IO_APIC_ADDR, ioapic_id);
+ if (ioapic_id != get_ioapic_id(IO_APIC_ADDR))
die("IOAPIC error!\n");
}
}
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index d914335..c8b0760 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -39,9 +39,9 @@
pci_write_config32(dev, GEN_CNTL, reg32);
printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
- register_new_ioapic_gsi0(VIO_APIC_VADDR);
+ register_new_ioapic_gsi0(IO_APIC_ADDR);
- ioapic_set_boot_config(VIO_APIC_VADDR, true);
+ ioapic_set_boot_config(IO_APIC_ADDR, true);
}
static void i82801dx_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 28cde3e..a04b4b9 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -34,7 +34,7 @@
*/
static void i82801gx_enable_ioapic(struct device *dev)
{
- register_new_ioapic_gsi0(VIO_APIC_VADDR);
+ register_new_ioapic_gsi0(IO_APIC_ADDR);
}
static void i82801gx_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 91b7456..0adc1b9 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -34,9 +34,9 @@
RCBA8(0x31ff);
/* Lock maximum redirection entries (MRE), R/WO register. */
- ioapic_lock_max_vectors(VIO_APIC_VADDR);
+ ioapic_lock_max_vectors(IO_APIC_ADDR);
- register_new_ioapic_gsi0(VIO_APIC_VADDR);
+ register_new_ioapic_gsi0(IO_APIC_ADDR);
}
static void i82801ix_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index 7cff33a..0a3e26f 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -35,9 +35,9 @@
RCBA8(0x31ff);
/* Lock maximum redirection entries (MRE), R/WO register. */
- ioapic_lock_max_vectors(VIO_APIC_VADDR);
+ ioapic_lock_max_vectors(IO_APIC_ADDR);
- register_new_ioapic_gsi0(VIO_APIC_VADDR);
+ register_new_ioapic_gsi0(IO_APIC_ADDR);
}
static void i82801jx_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
index f6a4ac0..4a25f6b 100644
--- a/src/southbridge/intel/i82870/ioapic.c
+++ b/src/southbridge/intel/i82870/ioapic.c
@@ -6,6 +6,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <assert.h>
+#include <types.h>
#include "82870.h"
static void p64h2_ioapic_enable(struct device *dev)
@@ -27,17 +28,17 @@
*/
static void p64h2_ioapic_init(struct device *dev)
{
- uint32_t memoryBase;
+ uintptr_t memoryBase;
// Read the MBAR address for setting up the IOAPIC in memory space
// NOTE: this address was assigned during enumeration of the bus
- memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ memoryBase = (uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- register_new_ioapic((void *)memoryBase);
+ register_new_ioapic(memoryBase);
// Use Processor System Bus to deliver interrupts
- ioapic_set_boot_config((void *)memoryBase, true);
+ ioapic_set_boot_config(memoryBase, true);
}
static struct device_operations ioapic_ops = {
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 7d85883..93dc387 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -33,9 +33,9 @@
static void pch_enable_ioapic(struct device *dev)
{
/* affirm full set of redirection table entries ("write once") */
- ioapic_lock_max_vectors(VIO_APIC_VADDR);
+ ioapic_lock_max_vectors(IO_APIC_ADDR);
- register_new_ioapic_gsi0(VIO_APIC_VADDR);
+ register_new_ioapic_gsi0(IO_APIC_ADDR);
}
static void pch_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index e44d9a8..93b7423 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -38,11 +38,11 @@
/* affirm full set of redirection table entries ("write once") */
/* PCH-LP has 40 redirection entries */
if (pch_is_lp())
- ioapic_set_max_vectors(VIO_APIC_VADDR, 40);
+ ioapic_set_max_vectors(IO_APIC_ADDR, 40);
else
- ioapic_lock_max_vectors(VIO_APIC_VADDR);
+ ioapic_lock_max_vectors(IO_APIC_ADDR);
- register_new_ioapic_gsi0(VIO_APIC_VADDR);
+ register_new_ioapic_gsi0(IO_APIC_ADDR);
}
static void pch_enable_serial_irqs(struct device *dev)