blob: 837a5284226769833c7d6284c5cf02324fe3067b [file] [log] [blame]
/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
#include <fsp/api.h>
#include <soc/romstage.h>
#include <soc/meminit.h>
static const struct mb_cfg ddr5_mem_config = {
.type = MEM_TYPE_DDR5,
.rcomp = {
/* Baseboard uses only 100ohm Rcomp resistor */
.resistor = 100,
/* Baseboard Rcomp target values */
.targets = { 50, 30, 30, 30, 27 },
},
.ect = true, /* Early Command Training */
.UserBd = BOARD_TYPE_MOBILE,
.LpDdrDqDqsReTraining = 1,
.ddr_config = {
.dq_pins_interleaved = false,
}
};
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
const struct mb_cfg *mem_config = &ddr5_mem_config;
const bool half_populated = false;
const struct mem_spd dimm_module_spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = {
.addr_dimm[0] = 0x50,
.addr_dimm[1] = 0x51,
},
[1] = {
.addr_dimm[0] = 0x52,
.addr_dimm[1] = 0x53,
},
},
};
memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated);
}