| /** @file |
| |
| Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> |
| |
| Redistribution and use in source and binary forms, with or without modification, |
| are permitted provided that the following conditions are met: |
| |
| * Redistributions of source code must retain the above copyright notice, this |
| list of conditions and the following disclaimer. |
| * Redistributions in binary form must reproduce the above copyright notice, this |
| list of conditions and the following disclaimer in the documentation and/or |
| other materials provided with the distribution. |
| * Neither the name of Intel Corporation nor the names of its contributors may |
| be used to endorse or promote products derived from this software without |
| specific prior written permission. |
| |
| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| THE POSSIBILITY OF SUCH DAMAGE. |
| |
| This file is automatically generated. Please do NOT modify !!! |
| |
| **/ |
| |
| #ifndef __FSPMUPD_H__ |
| #define __FSPMUPD_H__ |
| |
| #include <FspUpd.h> |
| |
| #pragma pack(1) |
| |
| |
| #include <MemInfoHob.h> |
| |
| /// |
| /// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. |
| /// |
| typedef struct { |
| UINT8 Revision; ///< Chipset Init Info Revision |
| UINT8 Rsvd[3]; ///< Reserved |
| UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table |
| UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table |
| } CHIPSET_INIT_INFO; |
| |
| |
| /** Fsp M Configuration |
| **/ |
| typedef struct { |
| |
| /** Offset 0x0040 - Platform Reserved Memory Size |
| The minimum platform memory size required to pass control into DXE |
| **/ |
| UINT64 PlatformMemorySize; |
| |
| /** Offset 0x0048 - SPD Data Length |
| Length of SPD Data |
| 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes |
| **/ |
| UINT16 MemorySpdDataLen; |
| |
| /** Offset 0x004A - Reserved |
| **/ |
| UINT8 Reserved0; |
| |
| /** Offset 0x004B - Enable/Disable CrashLog Device 10 |
| Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog |
| $EN_DIS |
| **/ |
| UINT8 CpuCrashLogDevice; |
| |
| /** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr000; |
| |
| /** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr001; |
| |
| /** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr010; |
| |
| /** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr011; |
| |
| /** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr020; |
| |
| /** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr021; |
| |
| /** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr030; |
| |
| /** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr031; |
| |
| /** Offset 0x006C - Memory SPD Pointer Controller 1 Channel 0 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr100; |
| |
| /** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr101; |
| |
| /** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr110; |
| |
| /** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr111; |
| |
| /** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 2 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr120; |
| |
| /** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr121; |
| |
| /** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr130; |
| |
| /** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr131; |
| |
| /** Offset 0x008C - RcompResistor settings |
| Indicates RcompResistor settings: Board-dependent |
| **/ |
| UINT16 RcompResistor; |
| |
| /** Offset 0x008E - RcompTarget settings |
| RcompTarget settings: board-dependent |
| **/ |
| UINT16 RcompTarget[5]; |
| |
| /** Offset 0x0098 - Dqs Map CPU to DRAM MC 0 CH 0 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc0Ch0[2]; |
| |
| /** Offset 0x009A - Dqs Map CPU to DRAM MC 0 CH 1 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc0Ch1[2]; |
| |
| /** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 2 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc0Ch2[2]; |
| |
| /** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 3 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc0Ch3[2]; |
| |
| /** Offset 0x00A0 - Dqs Map CPU to DRAM MC 1 CH 0 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc1Ch0[2]; |
| |
| /** Offset 0x00A2 - Dqs Map CPU to DRAM MC 1 CH 1 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc1Ch1[2]; |
| |
| /** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 2 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc1Ch2[2]; |
| |
| /** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 3 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc1Ch3[2]; |
| |
| /** Offset 0x00A8 - Dq Map CPU to DRAM MC 0 CH 0 |
| Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc0Ch0[16]; |
| |
| /** Offset 0x00B8 - Dq Map CPU to DRAM MC 0 CH 1 |
| Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc0Ch1[16]; |
| |
| /** Offset 0x00C8 - Dq Map CPU to DRAM MC 0 CH 2 |
| Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc0Ch2[16]; |
| |
| /** Offset 0x00D8 - Dq Map CPU to DRAM MC 0 CH 3 |
| Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc0Ch3[16]; |
| |
| /** Offset 0x00E8 - Dq Map CPU to DRAM MC 1 CH 0 |
| Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc1Ch0[16]; |
| |
| /** Offset 0x00F8 - Dq Map CPU to DRAM MC 1 CH 1 |
| Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc1Ch1[16]; |
| |
| /** Offset 0x0108 - Dq Map CPU to DRAM MC 1 CH 2 |
| Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc1Ch2[16]; |
| |
| /** Offset 0x0118 - Dq Map CPU to DRAM MC 1 CH 3 |
| Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc1Ch3[16]; |
| |
| /** Offset 0x0128 - Dqs Pins Interleaved Setting |
| Indicates DqPinsInterleaved setting: board-dependent |
| $EN_DIS |
| **/ |
| UINT8 DqPinsInterleaved; |
| |
| /** Offset 0x0129 - Reserved |
| **/ |
| UINT8 Reserved1; |
| |
| /** Offset 0x012A - Reserved |
| **/ |
| UINT8 Reserved2; |
| |
| /** Offset 0x012B - Reserved |
| **/ |
| UINT8 Reserved3; |
| |
| /** Offset 0x012C - Reserved |
| **/ |
| UINT8 Reserved4; |
| |
| /** Offset 0x012D - Reserved |
| **/ |
| UINT8 Reserved5[3]; |
| |
| /** Offset 0x0130 - Tseg Size |
| Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build |
| 0x0400000:4MB, 0x01000000:16MB |
| **/ |
| UINT32 TsegSize; |
| |
| /** Offset 0x0134 - Reserved |
| **/ |
| UINT16 Reserved6; |
| |
| /** Offset 0x0136 - Reserved |
| **/ |
| UINT8 Reserved7; |
| |
| /** Offset 0x0137 - Enable SMBus |
| Enable/disable SMBus controller. |
| $EN_DIS |
| **/ |
| UINT8 SmbusEnable; |
| |
| /** Offset 0x0138 - Spd Address Tabl |
| Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used |
| if SPD Address is 00 |
| **/ |
| UINT8 SpdAddressTable[16]; |
| |
| /** Offset 0x0148 - Platform Debug Consent |
| Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks |
| s0ix\n |
| \n |
| Enabled(Low Power) does not support DCI OOB 4-wire and Tracehub is powergated by |
| default, s0ix is viable\n |
| \n |
| Manual:user needs to configure Advanced Debug Settings manually, aimed at advanced users |
| 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual |
| **/ |
| UINT8 PlatformDebugConsent; |
| |
| /** Offset 0x0149 - Reserved |
| **/ |
| UINT8 Reserved8; |
| |
| /** Offset 0x014A - Reserved |
| **/ |
| UINT8 Reserved9; |
| |
| /** Offset 0x014B - Reserved |
| **/ |
| UINT8 Reserved10; |
| |
| /** Offset 0x014C - Reserved |
| **/ |
| UINT8 Reserved11; |
| |
| /** Offset 0x014D - Reserved |
| **/ |
| UINT8 Reserved12; |
| |
| /** Offset 0x014E - Reserved |
| **/ |
| UINT8 Reserved13; |
| |
| /** Offset 0x014F - Reserved |
| **/ |
| UINT8 Reserved14; |
| |
| /** Offset 0x0150 - Reserved |
| **/ |
| UINT8 Reserved15; |
| |
| /** Offset 0x0151 - Reserved |
| **/ |
| UINT8 Reserved16; |
| |
| /** Offset 0x0152 - Reserved |
| **/ |
| UINT8 Reserved17; |
| |
| /** Offset 0x0153 - Reserved |
| **/ |
| UINT8 Reserved18; |
| |
| /** Offset 0x0154 - Reserved |
| **/ |
| UINT8 Reserved19; |
| |
| /** Offset 0x0155 - Reserved |
| **/ |
| UINT8 Reserved20; |
| |
| /** Offset 0x0156 - Reserved |
| **/ |
| UINT8 Reserved21; |
| |
| /** Offset 0x0157 - Reserved |
| **/ |
| UINT8 Reserved22; |
| |
| /** Offset 0x0158 - Reserved |
| **/ |
| UINT8 Reserved23[2]; |
| |
| /** Offset 0x015A - Reserved |
| **/ |
| UINT8 Reserved24[4]; |
| |
| /** Offset 0x015E - State of X2APIC_OPT_OUT bit in the DMAR table |
| 0=Disable/Clear, 1=Enable/Set |
| $EN_DIS |
| **/ |
| UINT8 X2ApicOptOut; |
| |
| /** Offset 0x015F - Reserved |
| **/ |
| UINT8 Reserved25; |
| |
| /** Offset 0x0160 - Base addresses for VT-d function MMIO access |
| Base addresses for VT-d MMIO access per VT-d engine |
| **/ |
| UINT32 VtdBaseAddress[9]; |
| |
| /** Offset 0x0184 - Disable VT-d |
| 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) |
| $EN_DIS |
| **/ |
| UINT8 VtdDisable; |
| |
| /** Offset 0x0185 - Reserved |
| **/ |
| UINT8 Reserved26; |
| |
| /** Offset 0x0186 - Reserved |
| **/ |
| UINT8 Reserved27; |
| |
| /** Offset 0x0187 - Internal Graphics Pre-allocated Memory |
| Size of memory preallocated for internal graphics. |
| 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, |
| 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, |
| 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB |
| **/ |
| UINT8 IgdDvmt50PreAlloc; |
| |
| /** Offset 0x0188 - Internal Graphics |
| Enable/disable internal graphics. |
| $EN_DIS |
| **/ |
| UINT8 InternalGfx; |
| |
| /** Offset 0x0189 - Board Type |
| MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile |
| Halo, 7=UP Server |
| 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server |
| **/ |
| UINT8 UserBd; |
| |
| /** Offset 0x018A - Reserved |
| **/ |
| UINT8 Reserved28; |
| |
| /** Offset 0x018B - Reserved |
| **/ |
| UINT8 Reserved29; |
| |
| /** Offset 0x018C - DDR Frequency Limit |
| Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, |
| 2133, 2400, 2667, 2933 and 0 for Auto. |
| 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto |
| **/ |
| UINT16 DdrFreqLimit; |
| |
| /** Offset 0x018E - SAGV |
| System Agent dynamic frequency support. |
| 0:Disabled, 1:Enabled |
| **/ |
| UINT8 SaGv; |
| |
| /** Offset 0x018F - Reserved |
| **/ |
| UINT8 Reserved30; |
| |
| /** Offset 0x0190 - Reserved |
| **/ |
| UINT8 Reserved31; |
| |
| /** Offset 0x0191 - Reserved |
| **/ |
| UINT8 Reserved32; |
| |
| /** Offset 0x0192 - Controller 0 Channel 0 DIMM Control |
| Enable / Disable DIMMs on Controller 0 Channel 0 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc0Ch0; |
| |
| /** Offset 0x0193 - Controller 0 Channel 1 DIMM Control |
| Enable / Disable DIMMs on Controller 0 Channel 1 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc0Ch1; |
| |
| /** Offset 0x0194 - Controller 0 Channel 2 DIMM Control |
| Enable / Disable DIMMs on Controller 0 Channel 2 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc0Ch2; |
| |
| /** Offset 0x0195 - Controller 0 Channel 3 DIMM Control |
| Enable / Disable DIMMs on Controller 0 Channel 3 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc0Ch3; |
| |
| /** Offset 0x0196 - Controller 1 Channel 0 DIMM Control |
| Enable / Disable DIMMs on Controller 1 Channel 0 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc1Ch0; |
| |
| /** Offset 0x0197 - Controller 1 Channel 1 DIMM Control |
| Enable / Disable DIMMs on Controller 1 Channel 1 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc1Ch1; |
| |
| /** Offset 0x0198 - Controller 1 Channel 2 DIMM Control |
| Enable / Disable DIMMs on Controller 1 Channel 2 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc1Ch2; |
| |
| /** Offset 0x0199 - Controller 1 Channel 3 DIMM Control |
| Enable / Disable DIMMs on Controller 1 Channel 3 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc1Ch3; |
| |
| /** Offset 0x019A - Reserved |
| **/ |
| UINT8 Reserved33; |
| |
| /** Offset 0x019B - Reserved |
| **/ |
| UINT8 Reserved34; |
| |
| /** Offset 0x019C - Reserved |
| **/ |
| UINT8 Reserved35; |
| |
| /** Offset 0x019D - Reserved |
| **/ |
| UINT8 Reserved36; |
| |
| /** Offset 0x019E - Memory Reference Clock |
| 100MHz, 133MHz. |
| 0:133MHz, 1:100MHz |
| **/ |
| UINT8 RefClk; |
| |
| /** Offset 0x019F - Reserved |
| **/ |
| UINT8 Reserved37; |
| |
| /** Offset 0x01A0 - Reserved |
| **/ |
| UINT16 Reserved38; |
| |
| /** Offset 0x01A2 - Reserved |
| **/ |
| UINT16 Reserved39; |
| |
| /** Offset 0x01A4 - Reserved |
| **/ |
| UINT16 Reserved40; |
| |
| /** Offset 0x01A6 - Reserved |
| **/ |
| UINT16 Reserved41; |
| |
| /** Offset 0x01A8 - Reserved |
| **/ |
| UINT8 Reserved42; |
| |
| /** Offset 0x01A9 - Reserved |
| **/ |
| UINT8 Reserved43; |
| |
| /** Offset 0x01AA - Reserved |
| **/ |
| UINT16 Reserved44; |
| |
| /** Offset 0x01AC - Reserved |
| **/ |
| UINT16 Reserved45; |
| |
| /** Offset 0x01AE - Reserved |
| **/ |
| UINT8 Reserved46; |
| |
| /** Offset 0x01AF - Reserved |
| **/ |
| UINT8 Reserved47; |
| |
| /** Offset 0x01B0 - Reserved |
| **/ |
| UINT16 Reserved48; |
| |
| /** Offset 0x01B2 - Reserved |
| **/ |
| UINT16 Reserved49; |
| |
| /** Offset 0x01B4 - Reserved |
| **/ |
| UINT8 Reserved50; |
| |
| /** Offset 0x01B5 - Reserved |
| **/ |
| UINT8 Reserved51; |
| |
| /** Offset 0x01B6 - Reserved |
| **/ |
| UINT8 Reserved52; |
| |
| /** Offset 0x01B7 - Reserved |
| **/ |
| UINT8 Reserved53; |
| |
| /** Offset 0x01B8 - Reserved |
| **/ |
| UINT16 Reserved54; |
| |
| /** Offset 0x01BA - Reserved |
| **/ |
| UINT16 Reserved55; |
| |
| /** Offset 0x01BC - Reserved |
| **/ |
| UINT16 Reserved56; |
| |
| /** Offset 0x01BE - Reserved |
| **/ |
| UINT8 Reserved57; |
| |
| /** Offset 0x01BF - Reserved |
| **/ |
| UINT8 Reserved58; |
| |
| /** Offset 0x01C0 - Reserved |
| **/ |
| UINT8 Reserved59; |
| |
| /** Offset 0x01C1 - Reserved |
| **/ |
| UINT8 Reserved60; |
| |
| /** Offset 0x01C2 - Reserved |
| **/ |
| UINT8 Reserved61; |
| |
| /** Offset 0x01C3 - Reserved |
| **/ |
| UINT8 Reserved62; |
| |
| /** Offset 0x01C4 - Enable Intel HD Audio (Azalia) |
| 0: Disable, 1: Enable (Default) Azalia controller |
| $EN_DIS |
| **/ |
| UINT8 PchHdaEnable; |
| |
| /** Offset 0x01C5 - Enable PCH ISH Controller |
| 0: Disable, 1: Enable (Default) ISH Controller |
| $EN_DIS |
| **/ |
| UINT8 PchIshEnable; |
| |
| /** Offset 0x01C6 - Reserved |
| **/ |
| UINT8 Reserved63[4]; |
| |
| /** Offset 0x01CA - Reserved |
| **/ |
| UINT16 Reserved64[4]; |
| |
| /** Offset 0x01D2 - Reserved |
| **/ |
| UINT8 Reserved65; |
| |
| /** Offset 0x01D3 - Reserved |
| **/ |
| UINT8 Reserved66; |
| |
| /** Offset 0x01D4 - Reserved |
| **/ |
| UINT8 Reserved67; |
| |
| /** Offset 0x01D5 - Reserved |
| **/ |
| UINT8 Reserved68; |
| |
| /** Offset 0x01D6 - Reserved |
| **/ |
| UINT16 Reserved69; |
| |
| /** Offset 0x01D8 - Reserved |
| **/ |
| UINT8 Reserved70; |
| |
| /** Offset 0x01D9 - Reserved |
| **/ |
| UINT8 Reserved71[3]; |
| |
| /** Offset 0x01DC - Reserved |
| **/ |
| UINT32 Reserved72; |
| |
| /** Offset 0x01E0 - Reserved |
| **/ |
| UINT32 Reserved73; |
| |
| /** Offset 0x01E4 - Reserved |
| **/ |
| UINT8 Reserved74; |
| |
| /** Offset 0x01E5 - Reserved |
| **/ |
| UINT8 Reserved75; |
| |
| /** Offset 0x01E6 - Reserved |
| **/ |
| UINT8 Reserved76; |
| |
| /** Offset 0x01E7 - Reserved |
| **/ |
| UINT8 Reserved77; |
| |
| /** Offset 0x01E8 - Reserved |
| **/ |
| UINT16 Reserved78; |
| |
| /** Offset 0x01EA - Reserved |
| **/ |
| UINT16 Reserved79; |
| |
| /** Offset 0x01EC - Reserved |
| **/ |
| UINT16 Reserved80; |
| |
| /** Offset 0x01EE - Reserved |
| **/ |
| UINT16 Reserved81; |
| |
| /** Offset 0x01F0 - Reserved |
| **/ |
| UINT8 Reserved82; |
| |
| /** Offset 0x01F1 - Reserved |
| **/ |
| UINT8 Reserved83; |
| |
| /** Offset 0x01F2 - Reserved |
| **/ |
| UINT8 Reserved84; |
| |
| /** Offset 0x01F3 - Enable/Disable SA IPU |
| Enable(Default): Enable SA IPU, Disable: Disable SA IPU |
| $EN_DIS |
| **/ |
| UINT8 SaIpuEnable; |
| |
| /** Offset 0x01F4 - IMGU CLKOUT Configuration |
| The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>. |
| $EN_DIS |
| **/ |
| UINT8 ImguClkOutEn[6]; |
| |
| /** Offset 0x01FA - Program GPIOs for LFP on DDI port-A device |
| 0=Disabled,1(Default)=eDP, 2=MIPI DSI |
| 0:Disabled, 1:eDP, 2:MIPI DSI |
| **/ |
| UINT8 DdiPortAConfig; |
| |
| /** Offset 0x01FB - Program GPIOs for LFP on DDI port-B device |
| 0(Default)=Disabled,1=eDP, 2=MIPI DSI |
| 0:Disabled, 1:eDP, 2:MIPI DSI |
| **/ |
| UINT8 DdiPortBConfig; |
| |
| /** Offset 0x01FC - Enable or disable HPD of DDI port A |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPortAHpd; |
| |
| /** Offset 0x01FD - Enable or disable HPD of DDI port B |
| 0=Disable, 1(Default)=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPortBHpd; |
| |
| /** Offset 0x01FE - Enable or disable HPD of DDI port C |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPortCHpd; |
| |
| /** Offset 0x01FF - Enable or disable HPD of DDI port 1 |
| 0=Disable, 1(Default)=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort1Hpd; |
| |
| /** Offset 0x0200 - Enable or disable HPD of DDI port 2 |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort2Hpd; |
| |
| /** Offset 0x0201 - Enable or disable HPD of DDI port 3 |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort3Hpd; |
| |
| /** Offset 0x0202 - Enable or disable HPD of DDI port 4 |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort4Hpd; |
| |
| /** Offset 0x0203 - Enable or disable DDC of DDI port A |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPortADdc; |
| |
| /** Offset 0x0204 - Enable or disable DDC of DDI port B |
| 0=Disable, 1(Default)=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPortBDdc; |
| |
| /** Offset 0x0205 - Enable or disable DDC of DDI port C |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPortCDdc; |
| |
| /** Offset 0x0206 - Enable DDC setting of DDI Port 1 |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort1Ddc; |
| |
| /** Offset 0x0207 - Enable DDC setting of DDI Port 2 |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort2Ddc; |
| |
| /** Offset 0x0208 - Enable DDC setting of DDI Port 3 |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort3Ddc; |
| |
| /** Offset 0x0209 - Enable DDC setting of DDI Port 4 |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort4Ddc; |
| |
| /** Offset 0x020A - Reserved |
| **/ |
| UINT8 Reserved85[6]; |
| |
| /** Offset 0x0210 - Reserved |
| **/ |
| UINT64 Reserved86; |
| |
| /** Offset 0x0218 - Reserved |
| **/ |
| UINT16 Reserved87; |
| |
| /** Offset 0x021A - Reserved |
| **/ |
| UINT8 Reserved88; |
| |
| /** Offset 0x021B - Reserved |
| **/ |
| UINT8 Reserved89; |
| |
| /** Offset 0x021C - Reserved |
| **/ |
| UINT8 Reserved90; |
| |
| /** Offset 0x021D - Reserved |
| **/ |
| UINT8 Reserved91[113]; |
| |
| /** Offset 0x028E - Reserved |
| **/ |
| UINT8 Reserved92; |
| |
| /** Offset 0x028F - Reserved |
| **/ |
| UINT8 Reserved93; |
| |
| /** Offset 0x0290 - Reserved |
| **/ |
| UINT8 Reserved94; |
| |
| /** Offset 0x0291 - Reserved |
| **/ |
| UINT8 Reserved95; |
| |
| /** Offset 0x0292 - DMI Gen3 Root port preset values per lane |
| Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane |
| **/ |
| UINT8 DmiGen3RootPortPreset[8]; |
| |
| /** Offset 0x029A - Reserved |
| **/ |
| UINT8 Reserved96[8]; |
| |
| /** Offset 0x02A2 - Reserved |
| **/ |
| UINT8 Reserved97[8]; |
| |
| /** Offset 0x02AA - Reserved |
| **/ |
| UINT8 Reserved98; |
| |
| /** Offset 0x02AB - Reserved |
| **/ |
| UINT8 Reserved99; |
| |
| /** Offset 0x02AC - Reserved |
| **/ |
| UINT8 Reserved100; |
| |
| /** Offset 0x02AD - Reserved |
| **/ |
| UINT8 Reserved101; |
| |
| /** Offset 0x02AE - Reserved |
| **/ |
| UINT8 Reserved102; |
| |
| /** Offset 0x02AF - Reserved |
| **/ |
| UINT8 Reserved103; |
| |
| /** Offset 0x02B0 - Reserved |
| **/ |
| UINT8 Reserved104[8]; |
| |
| /** Offset 0x02B8 - Reserved |
| **/ |
| UINT8 Reserved105[8]; |
| |
| /** Offset 0x02C0 - Reserved |
| **/ |
| UINT8 Reserved106[8]; |
| |
| /** Offset 0x02C8 - Reserved |
| **/ |
| UINT8 Reserved107[8]; |
| |
| /** Offset 0x02D0 - Reserved |
| **/ |
| UINT8 Reserved108; |
| |
| /** Offset 0x02D1 - Reserved |
| **/ |
| UINT8 Reserved109[8]; |
| |
| /** Offset 0x02D9 - Reserved |
| **/ |
| UINT8 Reserved110[8]; |
| |
| /** Offset 0x02E1 - Reserved |
| **/ |
| UINT8 Reserved111; |
| |
| /** Offset 0x02E2 - Reserved |
| **/ |
| UINT8 Reserved112[8]; |
| |
| /** Offset 0x02EA - Reserved |
| **/ |
| UINT8 Reserved113[8]; |
| |
| /** Offset 0x02F2 - Reserved |
| **/ |
| UINT8 Reserved114[8]; |
| |
| /** Offset 0x02FA - Reserved |
| **/ |
| UINT8 Reserved115[8]; |
| |
| /** Offset 0x0302 - Reserved |
| **/ |
| UINT8 Reserved116; |
| |
| /** Offset 0x0303 - Reserved |
| **/ |
| UINT8 Reserved117; |
| |
| /** Offset 0x0304 - Reserved |
| **/ |
| UINT8 Reserved118; |
| |
| /** Offset 0x0305 - Reserved |
| **/ |
| UINT8 Reserved119[8]; |
| |
| /** Offset 0x030D - Reserved |
| **/ |
| UINT8 Reserved120; |
| |
| /** Offset 0x030E - Reserved |
| **/ |
| UINT8 Reserved121; |
| |
| /** Offset 0x030F - Reserved |
| **/ |
| UINT8 Reserved122[8]; |
| |
| /** Offset 0x0317 - Reserved |
| **/ |
| UINT8 Reserved123[8]; |
| |
| /** Offset 0x031F - Reserved |
| **/ |
| UINT8 Reserved124; |
| |
| /** Offset 0x0320 - Reserved |
| **/ |
| UINT8 Reserved125[8]; |
| |
| /** Offset 0x0328 - Reserved |
| **/ |
| UINT8 Reserved126; |
| |
| /** Offset 0x0329 - Reserved |
| **/ |
| UINT8 Reserved127[3]; |
| |
| /** Offset 0x032C - Reserved |
| **/ |
| UINT32 Reserved128; |
| |
| /** Offset 0x0330 - Reserved |
| **/ |
| UINT32 Reserved129; |
| |
| /** Offset 0x0334 - Reserved |
| **/ |
| UINT32 Reserved130; |
| |
| /** Offset 0x0338 - Reserved |
| **/ |
| UINT32 Reserved131; |
| |
| /** Offset 0x033C - Reserved |
| **/ |
| UINT16 Reserved132; |
| |
| /** Offset 0x033E - Reserved |
| **/ |
| UINT16 Reserved133; |
| |
| /** Offset 0x0340 - Reserved |
| **/ |
| UINT32 Reserved134; |
| |
| /** Offset 0x0344 - Reserved |
| **/ |
| UINT32 Reserved135; |
| |
| /** Offset 0x0348 - Reserved |
| **/ |
| UINT32 Reserved136; |
| |
| /** Offset 0x034C - Reserved |
| **/ |
| UINT32 Reserved137; |
| |
| /** Offset 0x0350 - Reserved |
| **/ |
| UINT8 Reserved138; |
| |
| /** Offset 0x0351 - Reserved |
| **/ |
| UINT8 Reserved139; |
| |
| /** Offset 0x0352 - C6DRAM power gating feature |
| This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM |
| power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating |
| feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>. |
| $EN_DIS |
| **/ |
| UINT8 EnableC6Dram; |
| |
| /** Offset 0x0353 - Reserved |
| **/ |
| UINT8 Reserved140; |
| |
| /** Offset 0x0354 - Reserved |
| **/ |
| UINT8 Reserved141; |
| |
| /** Offset 0x0355 - Reserved |
| **/ |
| UINT8 Reserved142; |
| |
| /** Offset 0x0356 - Reserved |
| **/ |
| UINT8 Reserved143; |
| |
| /** Offset 0x0357 - Reserved |
| **/ |
| UINT8 Reserved144; |
| |
| /** Offset 0x0358 - Hyper Threading Enable/Disable |
| Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b> |
| $EN_DIS |
| **/ |
| UINT8 HyperThreading; |
| |
| /** Offset 0x0359 - Reserved |
| **/ |
| UINT8 Reserved145; |
| |
| /** Offset 0x035A - CPU ratio value |
| CPU ratio value. Valid Range 0 to 63 |
| **/ |
| UINT8 CpuRatio; |
| |
| /** Offset 0x035B - Reserved |
| **/ |
| UINT8 Reserved146; |
| |
| /** Offset 0x035C - Reserved |
| **/ |
| UINT8 Reserved147; |
| |
| /** Offset 0x035D - Processor Early Power On Configuration FCLK setting |
| <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- |
| 2: 400 MHz. - 3: Reserved |
| 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved |
| **/ |
| UINT8 FClkFrequency; |
| |
| /** Offset 0x035E - Enable or Disable VMX |
| Enable or Disable VMX; 0: Disable; <b>1: Enable</b>. |
| $EN_DIS |
| **/ |
| UINT8 VmxEnable; |
| |
| /** Offset 0x035F - Reserved |
| **/ |
| UINT8 Reserved148; |
| |
| /** Offset 0x0360 - Reserved |
| **/ |
| UINT8 Reserved149; |
| |
| /** Offset 0x0361 - Reserved |
| **/ |
| UINT8 Reserved150; |
| |
| /** Offset 0x0362 - Reserved |
| **/ |
| UINT16 Reserved151; |
| |
| /** Offset 0x0364 - Reserved |
| **/ |
| UINT16 Reserved152; |
| |
| /** Offset 0x0366 - Reserved |
| **/ |
| UINT16 Reserved153; |
| |
| /** Offset 0x0368 - Reserved |
| **/ |
| UINT8 Reserved154; |
| |
| /** Offset 0x0369 - Reserved |
| **/ |
| UINT8 Reserved155; |
| |
| /** Offset 0x036A - Reserved |
| **/ |
| UINT8 Reserved156; |
| |
| /** Offset 0x036B - Reserved |
| **/ |
| UINT8 Reserved157; |
| |
| /** Offset 0x036C - Reserved |
| **/ |
| UINT16 Reserved158; |
| |
| /** Offset 0x036E - Reserved |
| **/ |
| UINT16 Reserved159; |
| |
| /** Offset 0x0370 - Reserved |
| **/ |
| UINT16 Reserved160; |
| |
| /** Offset 0x0372 - Enable or Disable TME |
| Enable or Disable TME; <b>0: Disable</b>; 1: Enable. |
| $EN_DIS |
| **/ |
| UINT8 TmeEnable; |
| |
| /** Offset 0x0373 - Enable CPU CrashLog |
| Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>. |
| $EN_DIS |
| **/ |
| UINT8 CpuCrashLogEnable; |
| |
| /** Offset 0x0374 - Reserved |
| **/ |
| UINT8 Reserved161; |
| |
| /** Offset 0x0375 - Reserved |
| **/ |
| UINT8 Reserved162; |
| |
| /** Offset 0x0376 - Reserved |
| **/ |
| UINT8 Reserved163; |
| |
| /** Offset 0x0377 - Reserved |
| **/ |
| UINT8 Reserved164[1]; |
| |
| /** Offset 0x0378 - Reserved |
| **/ |
| UINT16 Reserved165[4]; |
| |
| /** Offset 0x0380 - Reserved |
| **/ |
| UINT8 Reserved166[4]; |
| |
| /** Offset 0x0384 - Reserved |
| **/ |
| UINT8 Reserved167; |
| |
| /** Offset 0x0385 - Reserved |
| **/ |
| UINT8 Reserved168; |
| |
| /** Offset 0x0386 - Reserved |
| **/ |
| UINT16 Reserved169[15]; |
| |
| /** Offset 0x03A4 - Reserved |
| **/ |
| UINT8 Reserved170[15]; |
| |
| /** Offset 0x03B3 - Reserved |
| **/ |
| UINT8 Reserved171[15]; |
| |
| /** Offset 0x03C2 - Reserved |
| **/ |
| UINT8 Reserved172; |
| |
| /** Offset 0x03C3 - Reserved |
| **/ |
| UINT8 Reserved173; |
| |
| /** Offset 0x03C4 - Reserved |
| **/ |
| UINT16 Reserved174[8]; |
| |
| /** Offset 0x03D4 - Reserved |
| **/ |
| UINT8 Reserved175[8]; |
| |
| /** Offset 0x03DC - Reserved |
| **/ |
| UINT8 Reserved176; |
| |
| /** Offset 0x03DD - Reserved |
| **/ |
| UINT8 Reserved177[8]; |
| |
| /** Offset 0x03E5 - Reserved |
| **/ |
| UINT8 Reserved178; |
| |
| /** Offset 0x03E6 - Reserved |
| **/ |
| UINT16 Reserved179; |
| |
| /** Offset 0x03E8 - Reserved |
| **/ |
| UINT8 Reserved180[4]; |
| |
| /** Offset 0x03EC - Reserved |
| **/ |
| UINT8 Reserved181; |
| |
| /** Offset 0x03ED - Reserved |
| **/ |
| UINT8 Reserved182; |
| |
| /** Offset 0x03EE - Reserved |
| **/ |
| UINT8 Reserved183; |
| |
| /** Offset 0x03EF - Reserved |
| **/ |
| UINT8 Reserved184; |
| |
| /** Offset 0x03F0 - Reserved |
| **/ |
| UINT8 Reserved185; |
| |
| /** Offset 0x03F1 - Reserved |
| **/ |
| UINT8 Reserved186; |
| |
| /** Offset 0x03F2 - Reserved |
| **/ |
| UINT16 Reserved187[15]; |
| |
| /** Offset 0x0410 - Reserved |
| **/ |
| UINT8 Reserved188[15]; |
| |
| /** Offset 0x041F - Reserved |
| **/ |
| UINT8 Reserved189[15]; |
| |
| /** Offset 0x042E - Reserved |
| **/ |
| UINT8 Reserved190; |
| |
| /** Offset 0x042F - Reserved |
| **/ |
| UINT8 Reserved191; |
| |
| /** Offset 0x0430 - Reserved |
| **/ |
| UINT8 Reserved192; |
| |
| /** Offset 0x0431 - Reserved |
| **/ |
| UINT8 Reserved193; |
| |
| /** Offset 0x0432 - Reserved |
| **/ |
| UINT8 Reserved194; |
| |
| /** Offset 0x0433 - Reserved |
| **/ |
| UINT8 Reserved195; |
| |
| /** Offset 0x0434 - GPIO Override |
| Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings |
| before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO |
| configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use |
| **/ |
| UINT8 GpioOverride; |
| |
| /** Offset 0x0435 - Reserved |
| **/ |
| UINT8 Reserved196[3]; |
| |
| /** Offset 0x0438 - Reserved |
| **/ |
| UINT32 Reserved197; |
| |
| /** Offset 0x043C - Reserved |
| **/ |
| UINT32 Reserved198; |
| |
| /** Offset 0x0440 - Reserved |
| **/ |
| UINT8 Reserved199; |
| |
| /** Offset 0x0441 - Reserved |
| **/ |
| UINT8 Reserved200[7]; |
| |
| /** Offset 0x0448 - Reserved |
| **/ |
| UINT64 Reserved201; |
| |
| /** Offset 0x0450 - Reserved |
| **/ |
| UINT8 Reserved202; |
| |
| /** Offset 0x0451 - Reserved |
| **/ |
| UINT8 Reserved203; |
| |
| /** Offset 0x0452 - Reserved |
| **/ |
| UINT16 Reserved204; |
| |
| /** Offset 0x0454 - Reserved |
| **/ |
| UINT8 Reserved205; |
| |
| /** Offset 0x0455 - Reserved |
| **/ |
| UINT8 Reserved206; |
| |
| /** Offset 0x0456 - Reserved |
| **/ |
| UINT16 Reserved207; |
| |
| /** Offset 0x0458 - Reserved |
| **/ |
| UINT16 Reserved208[15]; |
| |
| /** Offset 0x0476 - Reserved |
| **/ |
| UINT8 Reserved209[15]; |
| |
| /** Offset 0x0485 - Reserved |
| **/ |
| UINT8 Reserved210[15]; |
| |
| /** Offset 0x0494 - Reserved |
| **/ |
| UINT8 Reserved211; |
| |
| /** Offset 0x0495 - Reserved |
| **/ |
| UINT8 Reserved212; |
| |
| /** Offset 0x0496 - Reserved |
| **/ |
| UINT8 Reserved213; |
| |
| /** Offset 0x0497 - Reserved |
| **/ |
| UINT8 Reserved214; |
| |
| /** Offset 0x0498 - Reserved |
| **/ |
| UINT8 Reserved215; |
| |
| /** Offset 0x0499 - Reserved |
| **/ |
| UINT8 Reserved216[28]; |
| |
| /** Offset 0x04B5 - Reserved |
| **/ |
| UINT8 Reserved217; |
| |
| /** Offset 0x04B6 - Reserved |
| **/ |
| UINT8 Reserved218; |
| |
| /** Offset 0x04B7 - Reserved |
| **/ |
| UINT8 Reserved219; |
| |
| /** Offset 0x04B8 - Reserved |
| **/ |
| UINT16 Reserved220; |
| |
| /** Offset 0x04BA - Reserved |
| **/ |
| UINT16 Reserved221[5]; |
| |
| /** Offset 0x04C4 - Reserved |
| **/ |
| UINT16 Reserved222[5]; |
| |
| /** Offset 0x04CE - Reserved |
| **/ |
| UINT16 Reserved223[5]; |
| |
| /** Offset 0x04D8 - Reserved |
| **/ |
| UINT16 Reserved224[5]; |
| |
| /** Offset 0x04E2 - Reserved |
| **/ |
| UINT16 Reserved225[5]; |
| |
| /** Offset 0x04EC - Reserved |
| **/ |
| UINT16 Reserved226[5]; |
| |
| /** Offset 0x04F6 - Reserved |
| **/ |
| UINT8 Reserved227[5]; |
| |
| /** Offset 0x04FB - Reserved |
| **/ |
| UINT8 Reserved228[5]; |
| |
| /** Offset 0x0500 - Reserved |
| **/ |
| UINT16 Reserved229[5]; |
| |
| /** Offset 0x050A - Reserved |
| **/ |
| UINT16 Reserved230[5]; |
| |
| /** Offset 0x0514 - Reserved |
| **/ |
| UINT8 Reserved231[5]; |
| |
| /** Offset 0x0519 - Thermal Design Current enable/disable |
| PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1: |
| Enable.For all VR Indexes |
| **/ |
| UINT8 TdcEnable[5]; |
| |
| /** Offset 0x051E - Reserved |
| **/ |
| UINT8 Reserved232[2]; |
| |
| /** Offset 0x0520 - Thermal Design Current time window |
| PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. |
| Range 1ms to 448s |
| **/ |
| UINT32 TdcTimeWindow[5]; |
| |
| /** Offset 0x0534 - Reserved |
| **/ |
| UINT8 Reserved233[5]; |
| |
| /** Offset 0x0539 - Reserved |
| **/ |
| UINT8 Reserved234; |
| |
| /** Offset 0x053A - Reserved |
| **/ |
| UINT16 Reserved235; |
| |
| /** Offset 0x053C - Reserved |
| **/ |
| UINT8 Reserved236; |
| |
| /** Offset 0x053D - Reserved |
| **/ |
| UINT8 Reserved237; |
| |
| /** Offset 0x053E - Reserved |
| **/ |
| UINT8 Reserved238; |
| |
| /** Offset 0x053F - Reserved |
| **/ |
| UINT8 Reserved239; |
| |
| /** Offset 0x0540 - Reserved |
| **/ |
| UINT8 Reserved240; |
| |
| /** Offset 0x0541 - Reserved |
| **/ |
| UINT8 Reserved241[1]; |
| |
| /** Offset 0x0542 - Reserved |
| **/ |
| UINT16 Reserved242[5]; |
| |
| /** Offset 0x054C - Reserved |
| **/ |
| UINT8 Reserved243[5]; |
| |
| /** Offset 0x0551 - Reserved |
| **/ |
| UINT8 Reserved244[1]; |
| |
| /** Offset 0x0552 - Reserved |
| **/ |
| UINT16 Reserved245[5]; |
| |
| /** Offset 0x055C - Reserved |
| **/ |
| UINT16 Reserved246[5]; |
| |
| /** Offset 0x0566 - Reserved |
| **/ |
| UINT8 Reserved247[5]; |
| |
| /** Offset 0x056B - Reserved |
| **/ |
| UINT8 Reserved248[1]; |
| |
| /** Offset 0x056C - Reserved |
| **/ |
| UINT16 Reserved249[5]; |
| |
| /** Offset 0x0576 - Reserved |
| **/ |
| UINT16 Reserved250[5]; |
| |
| /** Offset 0x0580 - Reserved |
| **/ |
| UINT8 Reserved251[5]; |
| |
| /** Offset 0x0585 - Reserved |
| **/ |
| UINT8 Reserved252[5]; |
| |
| /** Offset 0x058A - Reserved |
| **/ |
| UINT8 Reserved253[2]; |
| |
| /** Offset 0x058C - Reserved |
| **/ |
| UINT32 Reserved254[5]; |
| |
| /** Offset 0x05A0 - Reserved |
| **/ |
| UINT16 Reserved255; |
| |
| /** Offset 0x05A2 - Reserved |
| **/ |
| UINT8 Reserved256[5]; |
| |
| /** Offset 0x05A7 - Reserved |
| **/ |
| UINT8 Reserved257[5]; |
| |
| /** Offset 0x05AC - Reserved |
| **/ |
| UINT16 Reserved258[5]; |
| |
| /** Offset 0x05B6 - Reserved |
| **/ |
| UINT16 Reserved259[5]; |
| |
| /** Offset 0x05C0 - Reserved |
| **/ |
| UINT8 Reserved260[5]; |
| |
| /** Offset 0x05C5 - Reserved |
| **/ |
| UINT8 Reserved261[5]; |
| |
| /** Offset 0x05CA - Reserved |
| **/ |
| UINT8 Reserved262[5]; |
| |
| /** Offset 0x05CF - BiosGuard |
| Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable |
| $EN_DIS |
| **/ |
| UINT8 BiosGuard; |
| |
| /** Offset 0x05D0 |
| **/ |
| UINT8 BiosGuardToolsInterface; |
| |
| /** Offset 0x05D1 - Reserved |
| **/ |
| UINT8 Reserved263; |
| |
| /** Offset 0x05D2 - Reserved |
| **/ |
| UINT8 Reserved264[2]; |
| |
| /** Offset 0x05D4 - PrmrrSize |
| Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable |
| **/ |
| UINT32 PrmrrSize; |
| |
| /** Offset 0x05D8 - SinitMemorySize |
| Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable |
| **/ |
| UINT32 SinitMemorySize; |
| |
| /** Offset 0x05DC - Reserved |
| **/ |
| UINT8 Reserved265[4]; |
| |
| /** Offset 0x05E0 - Reserved |
| **/ |
| UINT64 Reserved266; |
| |
| /** Offset 0x05E8 - TxtHeapMemorySize |
| Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable |
| **/ |
| UINT32 TxtHeapMemorySize; |
| |
| /** Offset 0x05EC - TxtDprMemorySize |
| Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable |
| **/ |
| UINT32 TxtDprMemorySize; |
| |
| /** Offset 0x05F0 - Reserved |
| **/ |
| UINT32 Reserved267; |
| |
| /** Offset 0x05F4 - Reserved |
| **/ |
| UINT32 Reserved268; |
| |
| /** Offset 0x05F8 - Reserved |
| **/ |
| UINT32 Reserved269; |
| |
| /** Offset 0x05FC - Reserved |
| **/ |
| UINT32 Reserved270; |
| |
| /** Offset 0x0600 - Reserved |
| **/ |
| UINT64 Reserved271; |
| |
| /** Offset 0x0608 - Reserved |
| **/ |
| UINT64 Reserved272; |
| |
| /** Offset 0x0610 - Reserved |
| **/ |
| UINT8 Reserved273; |
| |
| /** Offset 0x0611 - Reserved |
| **/ |
| UINT8 Reserved274[32]; |
| |
| /** Offset 0x0631 - Reserved |
| **/ |
| UINT8 Reserved275[28]; |
| |
| /** Offset 0x064D - Reserved |
| **/ |
| UINT8 Reserved276[28]; |
| |
| /** Offset 0x0669 - Reserved |
| **/ |
| UINT8 Reserved277[28]; |
| |
| /** Offset 0x0685 - Reserved |
| **/ |
| UINT8 Reserved278[28]; |
| |
| /** Offset 0x06A1 - Reserved |
| **/ |
| UINT8 Reserved279[28]; |
| |
| /** Offset 0x06BD - Reserved |
| **/ |
| UINT8 Reserved280[28]; |
| |
| /** Offset 0x06D9 - Reserved |
| **/ |
| UINT8 Reserved281[28]; |
| |
| /** Offset 0x06F5 - Reserved |
| **/ |
| UINT8 Reserved282[28]; |
| |
| /** Offset 0x0711 - Reserved |
| **/ |
| UINT8 Reserved283[28]; |
| |
| /** Offset 0x072D - Reserved |
| **/ |
| UINT8 Reserved284[28]; |
| |
| /** Offset 0x0749 - Reserved |
| **/ |
| UINT8 Reserved285[28]; |
| |
| /** Offset 0x0765 - Reserved |
| **/ |
| UINT8 Reserved286[28]; |
| |
| /** Offset 0x0781 - Reserved |
| **/ |
| UINT8 Reserved287[28]; |
| |
| /** Offset 0x079D - Reserved |
| **/ |
| UINT8 Reserved288[28]; |
| |
| /** Offset 0x07B9 - Reserved |
| **/ |
| UINT8 Reserved289[8]; |
| |
| /** Offset 0x07C1 - Reserved |
| **/ |
| UINT8 Reserved290[8]; |
| |
| /** Offset 0x07C9 - Reserved |
| **/ |
| UINT8 Reserved291[8]; |
| |
| /** Offset 0x07D1 - Reserved |
| **/ |
| UINT8 Reserved292[8]; |
| |
| /** Offset 0x07D9 - Reserved |
| **/ |
| UINT8 Reserved293[8]; |
| |
| /** Offset 0x07E1 - Reserved |
| **/ |
| UINT8 Reserved294[8]; |
| |
| /** Offset 0x07E9 - Reserved |
| **/ |
| UINT8 Reserved295[8]; |
| |
| /** Offset 0x07F1 - Reserved |
| **/ |
| UINT8 Reserved296[8]; |
| |
| /** Offset 0x07F9 - Reserved |
| **/ |
| UINT8 Reserved297[8]; |
| |
| /** Offset 0x0801 - Reserved |
| **/ |
| UINT8 Reserved298[8]; |
| |
| /** Offset 0x0809 - Reserved |
| **/ |
| UINT8 Reserved299[8]; |
| |
| /** Offset 0x0811 - Reserved |
| **/ |
| UINT8 Reserved300[8]; |
| |
| /** Offset 0x0819 - Reserved |
| **/ |
| UINT8 Reserved301[8]; |
| |
| /** Offset 0x0821 - Reserved |
| **/ |
| UINT8 Reserved302[8]; |
| |
| /** Offset 0x0829 - Reserved |
| **/ |
| UINT8 Reserved303[8]; |
| |
| /** Offset 0x0831 - Reserved |
| **/ |
| UINT8 Reserved304[8]; |
| |
| /** Offset 0x0839 - Reserved |
| **/ |
| UINT8 Reserved305[8]; |
| |
| /** Offset 0x0841 - Reserved |
| **/ |
| UINT8 Reserved306[8]; |
| |
| /** Offset 0x0849 - Reserved |
| **/ |
| UINT8 Reserved307; |
| |
| /** Offset 0x084A - Reserved |
| **/ |
| UINT8 Reserved308; |
| |
| /** Offset 0x084B - Reserved |
| **/ |
| UINT8 Reserved309; |
| |
| /** Offset 0x084C - Number of RsvdSmbusAddressTable. |
| The number of elements in the RsvdSmbusAddressTable. |
| **/ |
| UINT8 PchNumRsvdSmbusAddresses; |
| |
| /** Offset 0x084D - Reserved |
| **/ |
| UINT8 Reserved310; |
| |
| /** Offset 0x084E - Reserved |
| **/ |
| UINT16 Reserved311; |
| |
| /** Offset 0x0850 - Reserved |
| **/ |
| UINT8 Reserved312; |
| |
| /** Offset 0x0851 - Usage type for ClkSrc |
| 0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used |
| **/ |
| UINT8 PcieClkSrcUsage[18]; |
| |
| /** Offset 0x0863 - Reserved |
| **/ |
| UINT8 Reserved313[14]; |
| |
| /** Offset 0x0871 - ClkReq-to-ClkSrc mapping |
| Number of ClkReq signal assigned to ClkSrc |
| **/ |
| UINT8 PcieClkSrcClkReq[18]; |
| |
| /** Offset 0x0883 - Reserved |
| **/ |
| UINT8 Reserved314[14]; |
| |
| /** Offset 0x0891 - Reserved |
| **/ |
| UINT8 Reserved315[3]; |
| |
| /** Offset 0x0894 - Reserved |
| **/ |
| UINT32 Reserved316[8]; |
| |
| /** Offset 0x08B4 - Reserved |
| **/ |
| UINT32 Reserved317; |
| |
| /** Offset 0x08B8 - Enable PCIE RP Mask |
| Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 |
| for port1, bit1 for port2, and so on. |
| **/ |
| UINT32 PcieRpEnableMask; |
| |
| /** Offset 0x08BC - Reserved |
| **/ |
| UINT8 Reserved318; |
| |
| /** Offset 0x08BD - Reserved |
| **/ |
| UINT8 Reserved319; |
| |
| /** Offset 0x08BE - Enable HD Audio Link |
| Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. |
| $EN_DIS |
| **/ |
| UINT8 PchHdaAudioLinkHdaEnable; |
| |
| /** Offset 0x08BF - Reserved |
| **/ |
| UINT8 Reserved320[2]; |
| |
| /** Offset 0x08C1 - Reserved |
| **/ |
| UINT8 Reserved321; |
| |
| /** Offset 0x08C2 - Enable HD Audio DMIC_N Link |
| Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. |
| **/ |
| UINT8 PchHdaAudioLinkDmicEnable[2]; |
| |
| /** Offset 0x08C4 - DMIC<N> ClkA Pin Muxing (N - DMIC number) |
| Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* |
| **/ |
| UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; |
| |
| /** Offset 0x08CC - DMIC<N> ClkB Pin Muxing |
| Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_* |
| **/ |
| UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; |
| |
| /** Offset 0x08D4 - Enable HD Audio DSP |
| Enable/disable HD Audio DSP feature. |
| $EN_DIS |
| **/ |
| UINT8 PchHdaDspEnable; |
| |
| /** Offset 0x08D5 - Reserved |
| **/ |
| UINT8 Reserved322[3]; |
| |
| /** Offset 0x08D8 - DMIC<N> Data Pin Muxing |
| Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* |
| **/ |
| UINT32 PchHdaAudioLinkDmicDataPinMux[2]; |
| |
| /** Offset 0x08E0 - Enable HD Audio SSP0 Link |
| Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 |
| **/ |
| UINT8 PchHdaAudioLinkSspEnable[6]; |
| |
| /** Offset 0x08E6 - Enable HD Audio SoundWire#N Link |
| Enable/disable HD Audio SNDW#N link. Muxed with HDA. |
| **/ |
| UINT8 PchHdaAudioLinkSndwEnable[4]; |
| |
| /** Offset 0x08EA - iDisp-Link Frequency |
| iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. |
| 4: 96MHz, 3: 48MHz |
| **/ |
| UINT8 PchHdaIDispLinkFrequency; |
| |
| /** Offset 0x08EB - iDisp-Link T-mode |
| iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T |
| 0: 2T, 2: 4T, 3: 8T, 4: 16T |
| **/ |
| UINT8 PchHdaIDispLinkTmode; |
| |
| /** Offset 0x08EC - iDisplay Audio Codec disconnection |
| 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. |
| $EN_DIS |
| **/ |
| UINT8 PchHdaIDispCodecDisconnect; |
| |
| /** Offset 0x08ED - Reserved |
| **/ |
| UINT8 Reserved323[3]; |
| |
| /** Offset 0x08F0 - Reserved |
| **/ |
| UINT32 Reserved324; |
| |
| /** Offset 0x08F4 - CNVi DDR RFI Mitigation |
| Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE |
| $EN_DIS |
| **/ |
| UINT8 CnviDdrRfim; |
| |
| /** Offset 0x08F5 - Reserved |
| **/ |
| UINT8 Reserved325; |
| |
| /** Offset 0x08F6 - Reserved |
| **/ |
| UINT8 Reserved326; |
| |
| /** Offset 0x08F7 - Reserved |
| **/ |
| UINT8 Reserved327; |
| |
| /** Offset 0x08F8 - Reserved |
| **/ |
| UINT32 Reserved328; |
| |
| /** Offset 0x08FC - Reserved |
| **/ |
| UINT32 Reserved329; |
| |
| /** Offset 0x0900 - Debug Interfaces |
| Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, |
| BIT2 - Not used. |
| **/ |
| UINT8 PcdDebugInterfaceFlags; |
| |
| /** Offset 0x0901 - Serial Io Uart Debug Controller Number |
| Select SerialIo Uart Controller for debug. |
| 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 |
| **/ |
| UINT8 SerialIoUartDebugControllerNumber; |
| |
| /** Offset 0x0902 - Reserved |
| **/ |
| UINT8 Reserved330; |
| |
| /** Offset 0x0903 - Reserved |
| **/ |
| UINT8 Reserved331; |
| |
| /** Offset 0x0904 - Reserved |
| **/ |
| UINT32 Reserved332; |
| |
| /** Offset 0x0908 - Reserved |
| **/ |
| UINT8 Reserved333; |
| |
| /** Offset 0x0909 - Reserved |
| **/ |
| UINT8 Reserved334; |
| |
| /** Offset 0x090A - Reserved |
| **/ |
| UINT8 Reserved335; |
| |
| /** Offset 0x090B - Reserved |
| **/ |
| UINT8 Reserved336; |
| |
| /** Offset 0x090C - Reserved |
| **/ |
| UINT32 Reserved337; |
| |
| /** Offset 0x0910 - ISA Serial Base selection |
| Select ISA Serial Base address. Default is 0x3F8. |
| 0:0x3F8, 1:0x2F8 |
| **/ |
| UINT8 PcdIsaSerialUartBase; |
| |
| /** Offset 0x0911 - Reserved |
| **/ |
| UINT8 Reserved338; |
| |
| /** Offset 0x0912 - Reserved |
| **/ |
| UINT8 Reserved339; |
| |
| /** Offset 0x0913 - Reserved |
| **/ |
| UINT8 Reserved340; |
| |
| /** Offset 0x0914 - Reserved |
| **/ |
| UINT8 Reserved341; |
| |
| /** Offset 0x0915 - TCSS Thunderbolt PCIE Root Port 0 Enable |
| Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled |
| $EN_DIS |
| **/ |
| UINT8 TcssItbtPcie0En; |
| |
| /** Offset 0x0916 - TCSS Thunderbolt PCIE Root Port 1 Enable |
| Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled |
| $EN_DIS |
| **/ |
| UINT8 TcssItbtPcie1En; |
| |
| /** Offset 0x0917 - TCSS Thunderbolt PCIE Root Port 2 Enable |
| Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled |
| $EN_DIS |
| **/ |
| UINT8 TcssItbtPcie2En; |
| |
| /** Offset 0x0918 - TCSS Thunderbolt PCIE Root Port 3 Enable |
| Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled |
| $EN_DIS |
| **/ |
| UINT8 TcssItbtPcie3En; |
| |
| /** Offset 0x0919 - TCSS USB HOST (xHCI) Enable |
| Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below |
| $EN_DIS |
| **/ |
| UINT8 TcssXhciEn; |
| |
| /** Offset 0x091A - TCSS USB DEVICE (xDCI) Enable |
| Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled |
| $EN_DIS |
| **/ |
| UINT8 TcssXdciEn; |
| |
| /** Offset 0x091B - TCSS DMA0 Enable |
| Set TCSS DMA0. 0:Disabled 1:Enabled |
| $EN_DIS |
| **/ |
| UINT8 TcssDma0En; |
| |
| /** Offset 0x091C - TCSS DMA1 Enable |
| Set TCSS DMA1. 0:Disabled 1:Enabled |
| $EN_DIS |
| **/ |
| UINT8 TcssDma1En; |
| |
| /** Offset 0x091D - Reserved |
| **/ |
| UINT8 Reserved342; |
| |
| /** Offset 0x091E - Reserved |
| **/ |
| UINT8 Reserved343; |
| |
| /** Offset 0x091F - Early Command Training |
| Enables/Disable Early Command Training |
| $EN_DIS |
| **/ |
| UINT8 ECT; |
| |
| /** Offset 0x0920 - Reserved |
| **/ |
| UINT8 Reserved344; |
| |
| /** Offset 0x0921 - Reserved |
| **/ |
| UINT8 Reserved345; |
| |
| /** Offset 0x0922 - Reserved |
| **/ |
| UINT8 Reserved346; |
| |
| /** Offset 0x0923 - Reserved |
| **/ |
| UINT8 Reserved347; |
| |
| /** Offset 0x0924 - Reserved |
| **/ |
| UINT8 Reserved348; |
| |
| /** Offset 0x0925 - Reserved |
| **/ |
| UINT8 Reserved349; |
| |
| /** Offset 0x0926 - Reserved |
| **/ |
| UINT8 Reserved350; |
| |
| /** Offset 0x0927 - Reserved |
| **/ |
| UINT8 Reserved351; |
| |
| /** Offset 0x0928 - Reserved |
| **/ |
| UINT8 Reserved352; |
| |
| /** Offset 0x0929 - Reserved |
| **/ |
| UINT8 Reserved353; |
| |
| /** Offset 0x092A - Reserved |
| **/ |
| UINT8 Reserved354; |
| |
| /** Offset 0x092B - Reserved |
| **/ |
| UINT8 Reserved355; |
| |
| /** Offset 0x092C - Reserved |
| **/ |
| UINT8 Reserved356; |
| |
| /** Offset 0x092D - Reserved |
| **/ |
| UINT8 Reserved357; |
| |
| /** Offset 0x092E - Reserved |
| **/ |
| UINT8 Reserved358; |
| |
| /** Offset 0x092F - Reserved |
| **/ |
| UINT8 Reserved359; |
| |
| /** Offset 0x0930 - Reserved |
| **/ |
| UINT8 Reserved360; |
| |
| /** Offset 0x0931 - Reserved |
| **/ |
| UINT8 Reserved361; |
| |
| /** Offset 0x0932 - Reserved |
| **/ |
| UINT8 Reserved362; |
| |
| /** Offset 0x0933 - Reserved |
| **/ |
| UINT8 Reserved363; |
| |
| /** Offset 0x0934 - Reserved |
| **/ |
| UINT8 Reserved364; |
| |
| /** Offset 0x0935 - Reserved |
| **/ |
| UINT8 Reserved365; |
| |
| /** Offset 0x0936 - Late Command Training |
| Enables/Disable Late Command Training |
| $EN_DIS |
| **/ |
| UINT8 LCT; |
| |
| /** Offset 0x0937 - Reserved |
| **/ |
| UINT8 Reserved366; |
| |
| /** Offset 0x0938 - Rank Margin Tool |
| Enable/disable Rank Margin Tool |
| $EN_DIS |
| **/ |
| UINT8 RMT; |
| |
| /** Offset 0x0939 - Reserved |
| **/ |
| UINT8 Reserved367; |
| |
| /** Offset 0x093A - Reserved |
| **/ |
| UINT8 Reserved368; |
| |
| /** Offset 0x093B - Reserved |
| **/ |
| UINT8 Reserved369; |
| |
| /** Offset 0x093C - Reserved |
| **/ |
| UINT8 Reserved370; |
| |
| /** Offset 0x093D - Reserved |
| **/ |
| UINT8 Reserved371; |
| |
| /** Offset 0x093E - Reserved |
| **/ |
| UINT8 Reserved372; |
| |
| /** Offset 0x093F - Reserved |
| **/ |
| UINT8 Reserved373; |
| |
| /** Offset 0x0940 - Reserved |
| **/ |
| UINT8 Reserved374; |
| |
| /** Offset 0x0941 - Reserved |
| **/ |
| UINT8 Reserved375; |
| |
| /** Offset 0x0942 - Reserved |
| **/ |
| UINT8 Reserved376; |
| |
| /** Offset 0x0943 - Reserved |
| **/ |
| UINT8 Reserved377; |
| |
| /** Offset 0x0944 - Reserved |
| **/ |
| UINT8 Reserved378; |
| |
| /** Offset 0x0945 - Reserved |
| **/ |
| UINT8 Reserved379; |
| |
| /** Offset 0x0946 - Reserved |
| **/ |
| UINT8 Reserved380; |
| |
| /** Offset 0x0947 - Reserved |
| **/ |
| UINT8 Reserved381; |
| |
| /** Offset 0x0948 - Reserved |
| **/ |
| UINT8 Reserved382; |
| |
| /** Offset 0x0949 - Reserved |
| **/ |
| UINT8 Reserved383; |
| |
| /** Offset 0x094A - Reserved |
| **/ |
| UINT8 Reserved384; |
| |
| /** Offset 0x094B - Reserved |
| **/ |
| UINT8 Reserved385; |
| |
| /** Offset 0x094C - Reserved |
| **/ |
| UINT8 Reserved386; |
| |
| /** Offset 0x094D - Reserved |
| **/ |
| UINT8 Reserved387; |
| |
| /** Offset 0x094E - Reserved |
| **/ |
| UINT8 Reserved388; |
| |
| /** Offset 0x094F - Reserved |
| **/ |
| UINT8 Reserved389; |
| |
| /** Offset 0x0950 - Reserved |
| **/ |
| UINT8 Reserved390; |
| |
| /** Offset 0x0951 - Reserved |
| **/ |
| UINT8 Reserved391; |
| |
| /** Offset 0x0952 - Reserved |
| **/ |
| UINT8 Reserved392; |
| |
| /** Offset 0x0953 - Reserved |
| **/ |
| UINT8 Reserved393; |
| |
| /** Offset 0x0954 - Reserved |
| **/ |
| UINT8 Reserved394; |
| |
| /** Offset 0x0955 - Reserved |
| **/ |
| UINT8 Reserved395; |
| |
| /** Offset 0x0956 - Reserved |
| **/ |
| UINT8 Reserved396; |
| |
| /** Offset 0x0957 - Reserved |
| **/ |
| UINT8 Reserved397; |
| |
| /** Offset 0x0958 - Reserved |
| **/ |
| UINT8 Reserved398; |
| |
| /** Offset 0x0959 - Reserved |
| **/ |
| UINT8 Reserved399; |
| |
| /** Offset 0x095A - Reserved |
| **/ |
| UINT8 Reserved400; |
| |
| /** Offset 0x095B - Reserved |
| **/ |
| UINT8 Reserved401; |
| |
| /** Offset 0x095C - Reserved |
| **/ |
| UINT8 Reserved402; |
| |
| /** Offset 0x095D - Reserved |
| **/ |
| UINT8 Reserved403; |
| |
| /** Offset 0x095E - Reserved |
| **/ |
| UINT8 Reserved404; |
| |
| /** Offset 0x095F - Reserved |
| **/ |
| UINT8 Reserved405; |
| |
| /** Offset 0x0960 - Reserved |
| **/ |
| UINT8 Reserved406; |
| |
| /** Offset 0x0961 - IbeccParity |
| In-Band ECC Parity Control |
| $EN_DIS |
| **/ |
| UINT8 IbeccParity; |
| |
| /** Offset 0x0962 - IbeccOperationMode |
| In-Band ECC Operation Mode |
| 0:Protect base on address range, 1: Non-protected, 2: All protected |
| **/ |
| UINT8 IbeccOperationMode; |
| |
| /** Offset 0x0963 - IbeccProtectedRegionEnable |
| In-Band ECC Protected Region Enable |
| $EN_DIS |
| **/ |
| UINT8 IbeccProtectedRegionEnable[8]; |
| |
| /** Offset 0x096B - Reserved |
| **/ |
| UINT8 Reserved407[1]; |
| |
| /** Offset 0x096C - IbeccProtectedRegionBases |
| IBECC Protected Region Bases per IBECC instance |
| **/ |
| UINT16 IbeccProtectedRegionBase[8]; |
| |
| /** Offset 0x097C - IbeccProtectedRegionMasks |
| IBECC Protected Region Masks |
| **/ |
| UINT16 IbeccProtectedRegionMask[8]; |
| |
| /** Offset 0x098C - IbeccProtectedRegionOverallBases |
| IBECC Protected Region Bases based on enabled IBECC instance |
| **/ |
| UINT16 IbeccProtectedRegionOverallBase[8]; |
| |
| /** Offset 0x099C - Reserved |
| **/ |
| UINT8 Reserved408; |
| |
| /** Offset 0x099D - Reserved |
| **/ |
| UINT8 Reserved409; |
| |
| /** Offset 0x099E - Reserved |
| **/ |
| UINT8 Reserved410; |
| |
| /** Offset 0x099F - Reserved |
| **/ |
| UINT8 Reserved411; |
| |
| /** Offset 0x09A0 - Reserved |
| **/ |
| UINT8 Reserved412; |
| |
| /** Offset 0x09A1 - Reserved |
| **/ |
| UINT8 Reserved413; |
| |
| /** Offset 0x09A2 - Reserved |
| **/ |
| UINT8 Reserved414; |
| |
| /** Offset 0x09A3 - Reserved |
| **/ |
| UINT8 Reserved415; |
| |
| /** Offset 0x09A4 - Reserved |
| **/ |
| UINT8 Reserved416; |
| |
| /** Offset 0x09A5 - Reserved |
| **/ |
| UINT8 Reserved417; |
| |
| /** Offset 0x09A6 - Reserved |
| **/ |
| UINT8 Reserved418; |
| |
| /** Offset 0x09A7 - Reserved |
| **/ |
| UINT8 Reserved419; |
| |
| /** Offset 0x09A8 - Reserved |
| **/ |
| UINT8 Reserved420; |
| |
| /** Offset 0x09A9 - Reserved |
| **/ |
| UINT8 Reserved421; |
| |
| /** Offset 0x09AA - Reserved |
| **/ |
| UINT8 Reserved422; |
| |
| /** Offset 0x09AB - Reserved |
| **/ |
| UINT8 Reserved423; |
| |
| /** Offset 0x09AC - Reserved |
| **/ |
| UINT8 Reserved424; |
| |
| /** Offset 0x09AD - Reserved |
| **/ |
| UINT8 Reserved425; |
| |
| /** Offset 0x09AE - Ch Hash Mask |
| Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to |
| BITS [19:6] Default is 0x30CC |
| **/ |
| UINT16 ChHashMask; |
| |
| /** Offset 0x09B0 - Reserved |
| **/ |
| UINT32 Reserved426; |
| |
| /** Offset 0x09B4 - Reserved |
| **/ |
| UINT16 Reserved427; |
| |
| /** Offset 0x09B6 - Reserved |
| **/ |
| UINT16 Reserved428; |
| |
| /** Offset 0x09B8 - Reserved |
| **/ |
| UINT8 Reserved429; |
| |
| /** Offset 0x09B9 - Reserved |
| **/ |
| UINT8 Reserved430; |
| |
| /** Offset 0x09BA - Reserved |
| **/ |
| UINT8 Reserved431; |
| |
| /** Offset 0x09BB - Reserved |
| **/ |
| UINT8 Reserved432; |
| |
| /** Offset 0x09BC - Reserved |
| **/ |
| UINT8 Reserved433; |
| |
| /** Offset 0x09BD - Reserved |
| **/ |
| UINT8 Reserved434; |
| |
| /** Offset 0x09BE - Reserved |
| **/ |
| UINT8 Reserved435; |
| |
| /** Offset 0x09BF - Reserved |
| **/ |
| UINT8 Reserved436; |
| |
| /** Offset 0x09C0 - Reserved |
| **/ |
| UINT8 Reserved437; |
| |
| /** Offset 0x09C1 - Reserved |
| **/ |
| UINT8 Reserved438; |
| |
| /** Offset 0x09C2 - Reserved |
| **/ |
| UINT8 Reserved439; |
| |
| /** Offset 0x09C3 - Reserved |
| **/ |
| UINT8 Reserved440; |
| |
| /** Offset 0x09C4 - Reserved |
| **/ |
| UINT8 Reserved441; |
| |
| /** Offset 0x09C5 - Reserved |
| **/ |
| UINT8 Reserved442; |
| |
| /** Offset 0x09C6 - Reserved |
| **/ |
| UINT8 Reserved443; |
| |
| /** Offset 0x09C7 - Reserved |
| **/ |
| UINT8 Reserved444; |
| |
| /** Offset 0x09C8 - Reserved |
| **/ |
| UINT8 Reserved445; |
| |
| /** Offset 0x09C9 - Reserved |
| **/ |
| UINT8 Reserved446; |
| |
| /** Offset 0x09CA - Reserved |
| **/ |
| UINT8 Reserved447; |
| |
| /** Offset 0x09CB - Reserved |
| **/ |
| UINT8 Reserved448; |
| |
| /** Offset 0x09CC - Reserved |
| **/ |
| UINT8 Reserved449; |
| |
| /** Offset 0x09CD - Reserved |
| **/ |
| UINT8 Reserved450; |
| |
| /** Offset 0x09CE - Reserved |
| **/ |
| UINT8 Reserved451; |
| |
| /** Offset 0x09CF - Reserved |
| **/ |
| UINT8 Reserved452; |
| |
| /** Offset 0x09D0 - Reserved |
| **/ |
| UINT8 Reserved453; |
| |
| /** Offset 0x09D1 - Reserved |
| **/ |
| UINT8 Reserved454; |
| |
| /** Offset 0x09D2 - Reserved |
| **/ |
| UINT8 Reserved455; |
| |
| /** Offset 0x09D3 - Reserved |
| **/ |
| UINT8 Reserved456; |
| |
| /** Offset 0x09D4 - Reserved |
| **/ |
| UINT8 Reserved457; |
| |
| /** Offset 0x09D5 - Reserved |
| **/ |
| UINT8 Reserved458; |
| |
| /** Offset 0x09D6 - Reserved |
| **/ |
| UINT8 Reserved459; |
| |
| /** Offset 0x09D7 - Reserved |
| **/ |
| UINT8 Reserved460; |
| |
| /** Offset 0x09D8 - Reserved |
| **/ |
| UINT8 Reserved461; |
| |
| /** Offset 0x09D9 - Reserved |
| **/ |
| UINT8 Reserved462; |
| |
| /** Offset 0x09DA - Reserved |
| **/ |
| UINT8 Reserved463; |
| |
| /** Offset 0x09DB - Reserved |
| **/ |
| UINT8 Reserved464; |
| |
| /** Offset 0x09DC - Reserved |
| **/ |
| UINT8 Reserved465; |
| |
| /** Offset 0x09DD - Reserved |
| **/ |
| UINT8 Reserved466; |
| |
| /** Offset 0x09DE - Reserved |
| **/ |
| UINT8 Reserved467; |
| |
| /** Offset 0x09DF - Reserved |
| **/ |
| UINT8 Reserved468; |
| |
| /** Offset 0x09E0 - Reserved |
| **/ |
| UINT8 Reserved469; |
| |
| /** Offset 0x09E1 - Reserved |
| **/ |
| UINT8 Reserved470; |
| |
| /** Offset 0x09E2 - Reserved |
| **/ |
| UINT8 Reserved471; |
| |
| /** Offset 0x09E3 - Reserved |
| **/ |
| UINT8 Reserved472; |
| |
| /** Offset 0x09E4 - Reserved |
| **/ |
| UINT8 Reserved473; |
| |
| /** Offset 0x09E5 - Reserved |
| **/ |
| UINT8 Reserved474; |
| |
| /** Offset 0x09E6 - Reserved |
| **/ |
| UINT8 Reserved475; |
| |
| /** Offset 0x09E7 - Reserved |
| **/ |
| UINT8 Reserved476; |
| |
| /** Offset 0x09E8 - Reserved |
| **/ |
| UINT8 Reserved477; |
| |
| /** Offset 0x09E9 - Reserved |
| **/ |
| UINT8 Reserved478; |
| |
| /** Offset 0x09EA - Reserved |
| **/ |
| UINT8 Reserved479; |
| |
| /** Offset 0x09EB - Reserved |
| **/ |
| UINT8 Reserved480; |
| |
| /** Offset 0x09EC - Reserved |
| **/ |
| UINT8 Reserved481; |
| |
| /** Offset 0x09ED - Reserved |
| **/ |
| UINT8 Reserved482; |
| |
| /** Offset 0x09EE - Reserved |
| **/ |
| UINT8 Reserved483; |
| |
| /** Offset 0x09EF - Reserved |
| **/ |
| UINT8 Reserved484; |
| |
| /** Offset 0x09F0 - Reserved |
| **/ |
| UINT8 Reserved485; |
| |
| /** Offset 0x09F1 - PcdSerialDebugLevel |
| Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, |
| Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, |
| Info & Verbose. |
| 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load |
| Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose |
| **/ |
| UINT8 PcdSerialDebugLevel; |
| |
| /** Offset 0x09F2 - Reserved |
| **/ |
| UINT8 Reserved486; |
| |
| /** Offset 0x09F3 - Reserved |
| **/ |
| UINT8 Reserved487; |
| |
| /** Offset 0x09F4 - Reserved |
| **/ |
| UINT16 Reserved488; |
| |
| /** Offset 0x09F6 - Reserved |
| **/ |
| UINT16 Reserved489; |
| |
| /** Offset 0x09F8 - Reserved |
| **/ |
| UINT8 Reserved490; |
| |
| /** Offset 0x09F9 - Reserved |
| **/ |
| UINT8 Reserved491; |
| |
| /** Offset 0x09FA - TCSS USB Port Enable |
| Bitmap for per port enabling |
| **/ |
| UINT8 UsbTcPortEnPreMem; |
| |
| /** Offset 0x09FB - Reserved |
| **/ |
| UINT8 Reserved492; |
| |
| /** Offset 0x09FC - Reserved |
| **/ |
| UINT16 Reserved493; |
| |
| /** Offset 0x09FE - Reserved |
| **/ |
| UINT8 Reserved494; |
| |
| /** Offset 0x09FF - Reserved |
| **/ |
| UINT8 Reserved495; |
| |
| /** Offset 0x0A00 - Reserved |
| **/ |
| UINT32 Reserved496[4]; |
| |
| /** Offset 0x0A10 - Reserved |
| **/ |
| UINT16 Reserved497; |
| |
| /** Offset 0x0A12 - Reserved |
| **/ |
| UINT8 Reserved498; |
| |
| /** Offset 0x0A13 - Reserved |
| **/ |
| UINT8 Reserved499; |
| |
| /** Offset 0x0A14 - Reserved |
| **/ |
| UINT8 Reserved500; |
| |
| /** Offset 0x0A15 - Reserved |
| **/ |
| UINT8 Reserved501; |
| |
| /** Offset 0x0A16 - Reserved |
| **/ |
| UINT8 Reserved502; |
| |
| /** Offset 0x0A17 - Reserved |
| **/ |
| UINT8 Reserved503; |
| |
| /** Offset 0x0A18 - Reserved |
| **/ |
| UINT16 Reserved504; |
| |
| /** Offset 0x0A1A - Reserved |
| **/ |
| UINT16 Reserved505; |
| |
| /** Offset 0x0A1C - Reserved |
| **/ |
| UINT16 Reserved506; |
| |
| /** Offset 0x0A1E - Reserved |
| **/ |
| UINT8 Reserved507; |
| |
| /** Offset 0x0A1F - Reserved |
| **/ |
| UINT8 Reserved508; |
| |
| /** Offset 0x0A20 - Reserved |
| **/ |
| UINT8 Reserved509; |
| |
| /** Offset 0x0A21 - Reserved |
| **/ |
| UINT8 Reserved510; |
| |
| /** Offset 0x0A22 - Reserved |
| **/ |
| UINT8 Reserved511; |
| |
| /** Offset 0x0A23 - Reserved |
| **/ |
| UINT8 Reserved512[4]; |
| |
| /** Offset 0x0A27 - Skip external display device scanning |
| Enable: Do not scan for external display device, Disable (Default): Scan external |
| display devices |
| $EN_DIS |
| **/ |
| UINT8 SkipExtGfxScan; |
| |
| /** Offset 0x0A28 - Reserved |
| **/ |
| UINT8 Reserved513; |
| |
| /** Offset 0x0A29 - Lock PCU Thermal Management registers |
| Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 |
| $EN_DIS |
| **/ |
| UINT8 LockPTMregs; |
| |
| /** Offset 0x0A2A - Reserved |
| **/ |
| UINT8 Reserved514; |
| |
| /** Offset 0x0A2B - Reserved |
| **/ |
| UINT8 Reserved515; |
| |
| /** Offset 0x0A2C - Reserved |
| **/ |
| UINT32 Reserved516; |
| |
| /** Offset 0x0A30 - Reserved |
| **/ |
| UINT8 Reserved517; |
| |
| /** Offset 0x0A31 - Reserved |
| **/ |
| UINT8 Reserved518; |
| |
| /** Offset 0x0A32 - Reserved |
| **/ |
| UINT16 Reserved519; |
| |
| /** Offset 0x0A34 - Reserved |
| **/ |
| UINT16 Reserved520; |
| |
| /** Offset 0x0A36 - Reserved |
| **/ |
| UINT8 Reserved521[89]; |
| |
| /** Offset 0x0A8F - Reserved |
| **/ |
| UINT8 Reserved522; |
| |
| /** Offset 0x0A90 - Reserved |
| **/ |
| UINT16 Reserved523; |
| |
| /** Offset 0x0A92 - Reserved |
| **/ |
| UINT16 Reserved524; |
| |
| /** Offset 0x0A94 - Reserved |
| **/ |
| UINT8 Reserved525[12]; |
| |
| /** Offset 0x0AA0 - Smbus dynamic power gating |
| Disable or Enable Smbus dynamic power gating. |
| $EN_DIS |
| **/ |
| UINT8 SmbusDynamicPowerGating; |
| |
| /** Offset 0x0AA1 - Disable and Lock Watch Dog Register |
| Set 1 to clear WDT status, then disable and lock WDT registers. |
| $EN_DIS |
| **/ |
| UINT8 WdtDisableAndLock; |
| |
| /** Offset 0x0AA2 - Reserved |
| **/ |
| UINT8 Reserved526; |
| |
| /** Offset 0x0AA3 - Reserved |
| **/ |
| UINT8 Reserved527; |
| |
| /** Offset 0x0AA4 - Reserved |
| **/ |
| UINT8 Reserved528; |
| |
| /** Offset 0x0AA5 - Reserved |
| **/ |
| UINT8 Reserved529; |
| |
| /** Offset 0x0AA6 - Reserved |
| **/ |
| UINT8 Reserved530; |
| |
| /** Offset 0x0AA7 - Reserved |
| **/ |
| UINT8 Reserved531; |
| |
| /** Offset 0x0AA8 - Reserved |
| **/ |
| UINT8 Reserved532; |
| |
| /** Offset 0x0AA9 - Reserved |
| **/ |
| UINT8 Reserved533; |
| |
| /** Offset 0x0AAA - Skip CPU replacement check |
| Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check |
| $EN_DIS |
| **/ |
| UINT8 SkipCpuReplacementCheck; |
| |
| /** Offset 0x0AAB - Reserved |
| **/ |
| UINT8 Reserved534; |
| |
| /** Offset 0x0AAC - Reserved |
| **/ |
| UINT8 Reserved535; |
| |
| /** Offset 0x0AAD - Serial Io Uart Debug Mode |
| Select SerialIo Uart Controller mode |
| 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, |
| 4:SerialIoUartSkipInit |
| **/ |
| UINT8 SerialIoUartDebugMode; |
| |
| /** Offset 0x0AAE - Reserved |
| **/ |
| UINT8 Reserved536[2]; |
| |
| /** Offset 0x0AB0 - Reserved |
| **/ |
| UINT32 Reserved537; |
| |
| /** Offset 0x0AB4 - Reserved |
| **/ |
| UINT32 Reserved538; |
| |
| /** Offset 0x0AB8 - Reserved |
| **/ |
| UINT32 Reserved539; |
| |
| /** Offset 0x0ABC - Reserved |
| **/ |
| UINT32 Reserved540; |
| |
| /** Offset 0x0AC0 - Reserved |
| **/ |
| UINT32 Reserved541; |
| |
| /** Offset 0x0AC4 - Reserved |
| **/ |
| UINT8 Reserved542[8]; |
| |
| /** Offset 0x0ACC - Reserved |
| **/ |
| UINT8 Reserved543[7]; |
| |
| /** Offset 0x0AD3 - Reserved |
| **/ |
| UINT8 Reserved544[5]; |
| } FSP_M_CONFIG; |
| |
| /** Fsp M UPD Configuration |
| **/ |
| typedef struct { |
| |
| /** Offset 0x0000 |
| **/ |
| FSP_UPD_HEADER FspUpdHeader; |
| |
| /** Offset 0x0020 |
| **/ |
| FSPM_ARCH_UPD FspmArchUpd; |
| |
| /** Offset 0x0040 |
| **/ |
| FSP_M_CONFIG FspmConfig; |
| |
| /** Offset 0x0AD8 |
| **/ |
| UINT8 UnusedUpdSpace35[6]; |
| |
| /** Offset 0x0ADE |
| **/ |
| UINT16 UpdTerminator; |
| } FSPM_UPD; |
| |
| #pragma pack() |
| |
| #endif |