| config SOC_INTEL_COMMON_BLOCK_CPU |
| bool |
| default n |
| help |
| This option selects Intel Common CPU Model support code |
| which provides various CPU related APIs which are common |
| between all Intel Processor families. Common CPU code is supported |
| for SOCs starting from SKL,KBL,APL, and future. |
| |
| config SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| bool |
| default n |
| help |
| This option selects Intel Common CPU MP Init code. In |
| this common MP Init mechanism, the MP Init is occurring before |
| calling FSP Silicon Init. Hence, MP Init will be pulled to |
| BS_DEV_INIT_CHIPS Entry. And on Exit of BS_DEV_INIT, it is |
| ensured that all MTRRs are re-programmed based on the DRAM |
| resource settings. |
| |
| config SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
| bool |
| depends on SOC_INTEL_COMMON_BLOCK_CPU |
| |
| config SOC_INTEL_COMMON_BLOCK_CAR |
| bool |
| default n |
| help |
| This option allows you to select how cache-as-ram (CAR) is set up. |
| |
| config INTEL_CAR_NEM |
| bool |
| default n |
| help |
| Traditionally, CAR is set up by using Non-Evict mode. This method |
| does not allow CAR and cache to co-exist, because cache fills are |
| blocked in NEM. |
| |
| config INTEL_CAR_CQOS |
| bool |
| default n |
| help |
| Cache Quality of Service allows more fine-grained control of cache |
| usage. As result, it is possible to set up a portion of L2 cache for |
| CAR and use the remainder for actual caching. |
| |
| config INTEL_CAR_NEM_ENHANCED |
| bool |
| default n |
| help |
| A current limitation of NEM (Non-Evict mode) is that code and data sizes |
| are derived from the requirement to not write out any modified cache line. |
| With NEM, if there is no physical memory behind the cached area, |
| the modified data will be lost and NEM results will be inconsistent. |
| ENHANCED NEM guarantees that modified data is always |
| kept in cache while clean data is replaced. |
| |
| config CAR_HAS_SF_MASKS |
| bool |
| depends on INTEL_CAR_NEM_ENHANCED |
| help |
| In the case of non-inclusive cache architecture Snoop Filter MSR |
| IA32_L3_SF_MASK_x programming is required along with the data ways. |
| This is applicable for TGL and beyond. |
| |
| config SF_MASK_2WAYS_PER_BIT |
| bool |
| depends on INTEL_CAR_NEM_ENHANCED |
| help |
| In the case of non-inclusive cache architecture when two ways in |
| the SF mask are controlled by one bit of the SF QoS register. |
| This is applicable for TGL alone. |
| |
| config COS_MAPPED_TO_MSB |
| bool |
| depends on INTEL_CAR_NEM_ENHANCED |
| help |
| On TGL and JSL platform the class of service configuration |
| is mapped to MSB of MSR IA32_PQR_ASSOC. |
| |
| config CAR_HAS_L3_PROTECTED_WAYS |
| bool |
| depends on INTEL_CAR_NEM_ENHANCED |
| help |
| On ADL and onwards platform has a newer requirement to protect |
| L3 ways in Non-Inclusive eNEM mode. Hence, MSR 0xc85 is to program |
| the data ways. |
| |
| config USE_INTEL_FSP_MP_INIT |
| bool "Perform MP Initialization by FSP" |
| default n |
| depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI |
| help |
| This option allows FSP to perform multiprocessor initialization. |
| |
| config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI |
| bool "Perform MP Initialization by FSP using coreboot MP PPI service" |
| default y if MP_SERVICES_PPI |
| default n |
| help |
| This option allows FSP to make use of MP services PPI published by |
| coreboot to perform multiprocessor initialization. |
| |
| config CPU_SUPPORTS_INTEL_TME |
| bool |
| default n |
| help |
| Select this if the SoC supports Intel Total Memory Encryption (TME). |
| |
| config INTEL_TME |
| bool "Total Memory Encryption (TME)/Multi-key TME (MKTME)" |
| depends on CPU_SUPPORTS_INTEL_TME |
| default y |
| help |
| Enable Total Memory Encryption (TME)/Multi-key TME (MKTME). The spec is |
| available at "https://software.intel.com/sites/default/files/managed/a5 |
| /16/Multi-Key-Total-Memory-Encryption-Spec.pdf". If CPU supports TME, |
| it would get enabled. If CPU supports MKTME, this same config option |
| enables MKTME. |
| |
| config CPU_XTAL_HZ |
| int |
| help |
| Base clock which virtually everything runs on. |
| |
| config CPU_SUPPORTS_PM_TIMER_EMULATION |
| bool |
| default n |
| help |
| Select this if the SoC's ucode supports PM ACPI timer emulation (Common |
| timer Copy), which is required to be able to disable the TCO PM ACPI |
| timer for power saving. |
| |
| config SOC_INTEL_NO_BOOTGUARD_MSR |
| bool |
| help |
| Select this on platforms that do not support Bootguard related MSRs |
| 0x139, MSR_BC_PBEC and 0x13A, MSR_BOOT_GUARD_SACM_INFO. |
| |
| config SOC_INTEL_DISABLE_POWER_LIMITS |
| bool |
| default n |
| help |
| Select this if the Running Average Power Limits (RAPL) algorithm |
| for constant power management is not needed. |
| |
| config SOC_INTEL_SET_MIN_CLOCK_RATIO |
| bool |
| depends on !SOC_INTEL_DISABLE_POWER_LIMITS |
| default n |
| help |
| If the power budget of the mainboard is limited, it can be useful to |
| limit the CPU power dissipation at the cost of performance by setting |
| the lowest possible CPU clock. Enable this option if you need smallest |
| possible CPU clock. This setting can be overruled by the OS if it has an |
| p-state driver which can adjust the clock to its need. |
| |
| config HAVE_HYPERTHREADING |
| def_bool n |
| |
| config FSP_HYPERTHREADING |
| bool "Enable Hyper-Threading" |
| depends on HAVE_HYPERTHREADING |
| default y |