Kconfig!
Works on Kontron, qemu, and serengeti.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
tested on abuild only.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/Kconfig b/src/Kconfig
new file mode 100644
index 0000000..ca7fa61
--- /dev/null
+++ b/src/Kconfig
@@ -0,0 +1,275 @@
+##
+## This file is part of the coreboot repair project.
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following conditions
+## are met:
+## 1. Redistributions of source code must retain the above copyright
+## notice, this list of conditions and the following disclaimer.
+## 2. Redistributions in binary form must reproduce the above copyright
+## notice, this list of conditions and the following disclaimer in the
+## documentation and/or other materials provided with the distribution.
+## 3. The name of the author may not be used to endorse or promote products
+## derived from this software without specific prior written permission.
+##
+## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+## SUCH DAMAGE.
+##
+
+mainmenu "Coreboot Configuration"
+
+source src/mainboard/Kconfig
+source src/arch/i386/Kconfig
+source src/arch/ppc/Kconfig
+source src/devices/Kconfig
+source src/northbridge/Kconfig
+source src/southbridge/Kconfig
+source src/superio/Kconfig
+source src/cpu/Kconfig
+
+config CBFS
+ bool
+ default y
+
+config HAVE_HIGH_TABLES
+ bool
+ default y
+
+config PCI_BUS_SEGN_BITS
+ int
+ default 0
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0
+
+config CPU_ADDR_BITS
+ int
+ default 36
+
+config XIP_ROM_BASE
+ hex
+ default 0xfffe0000
+
+config XIP_ROM_SIZE
+ hex
+ default 0x20000
+
+config LB_CKS_RANGE_START
+ int
+ default 49
+
+config LB_CKS_RANGE_END
+ int
+ default 125
+
+config LB_CKS_LOC
+ int
+ default 126
+
+config LOGICAL_CPUS
+ int
+ default 1
+
+config PCI_ROM_RUN
+ int
+ default 0
+
+config HT_CHAIN_UNITID_BASE
+ int
+ default 1
+
+config HT_CHAIN_END_UNITID_BASE
+ int
+ default 32
+
+config HEAP_SIZE
+ hex
+ default 0x2000
+
+config COREBOOT_V2
+ bool
+ default y
+
+config COREBOOT_V4
+ bool
+ default y
+
+config DEBUG
+ bool
+ default n
+
+config USE_PRINTK_IN_CAR
+ bool
+ default n
+
+config USE_OPTION_TABLE
+ bool
+ default n
+
+config MAX_CPUS
+ int
+ default 1
+
+config MMCONF_SUPPORT_DEFAULT
+ bool
+ default n
+
+config MMCONF_SUPPORT
+ bool
+ default n
+
+config LB_MEM_TOPK
+ int
+ default 2048
+
+config MULTIBOOT
+ bool
+ default n
+
+config COMPRESSED_PAYLOAD_LZMA
+ bool
+ default y
+
+config COMPRESSED_PAYLOAD_NRV2B
+ bool
+ default n
+
+source src/console/Kconfig
+
+config HAVE_ACPI_RESUME
+ bool
+ default n
+
+config ACPI_SSDTX_NUM
+ int
+ default 0
+
+config HAVE_ACPI_TABLES
+ bool
+ default n
+
+config HAVE_FALLBACK_BOOT
+ bool
+ default y
+
+config USE_FALLBACK_IMAGE
+ bool
+ default y
+
+config HAVE_HARD_RESET
+ bool
+ default n
+
+config HAVE_INIT_TIMER
+ bool
+ default n
+
+config HAVE_MAINBOARD_RESOURCES
+ bool
+ default n
+
+config HAVE_MOVNTI
+ bool
+ default y
+
+config HAVE_MP_TABLE
+ bool
+ default n
+
+config HAVE_OPTION_TABLE
+ bool
+ default y
+
+config HAVE_PIRQ_TABLE
+ bool
+ default n
+
+config PIRQ_ROUTE
+ bool
+ default n
+
+config HAVE_SMI_HANDLER
+ bool
+ default n
+
+config PCI_IO_CFG_EXT
+ bool
+ default n
+
+config IOAPIC
+ bool
+ default n
+
+menu "Drivers"
+
+endmenu
+
+menu "Payload"
+
+config COMPRESSED_PAYLOAD_LZMA
+ bool "Use LZMA compression for payloads"
+ default yes
+
+choice
+ prompt "Payload type"
+ default PAYLOAD_NONE
+
+config PAYLOAD_ELF
+ bool "An ELF executable payload file"
+ help
+ Select this option if you have a payload image (an ELF file)
+ which coreboot should run as soon as the basic hardware
+ initialization is completed.
+
+ You will be able to specify the location and file name of the
+ payload image later.
+
+config PAYLOAD_NONE
+ bool "No payload"
+ help
+ Select this option if you want to create an "empty" coreboot
+ ROM image for a certain mainboard, i.e. a coreboot ROM image
+ which does not yet contain a payload.
+
+ For such an image to be useful, you have to use the 'lar' tool
+ to add a payload to the ROM image later.
+
+endchoice
+
+config NORMAL_PAYLOAD_FILE
+ string "Normal payload path and filename"
+ depends on PAYLOAD_ELF
+ default "payload.elf"
+ help
+ The path and filename of the ELF executable file to use as normal payload.
+
+config FALLBACK_PAYLOAD_FILE
+ string "Fallback payload path and filename"
+ depends on PAYLOAD_ELF
+ default "payload.elf"
+ help
+ The path and filename of the ELF executable file to use as fallback payload.
+
+endmenu
+
+config GDB_STUB
+ bool "Enable GDB debugging support"
+ default y
+ help
+ If this is set, then you will be able to set breakpoints for gdb debugging.
+ See: src/arch/i386/lib/c_start.S
+
diff --git a/src/arch/i386/Kconfig b/src/arch/i386/Kconfig
new file mode 100644
index 0000000..ce36f55
--- /dev/null
+++ b/src/arch/i386/Kconfig
@@ -0,0 +1,59 @@
+config ARCH_X86
+ boolean
+ help
+ This option is used to set the architecture of a mainboard.
+ It is usually set in mainboard/*/Kconfig.
+
+config ARCH
+ string
+ default i386
+ depends on ARCH_X86
+ help
+ This is the name of the respective subdirectory in arch/.
+
+config ROMBASE
+ hex
+ default 0xffe00000 if COREBOOT_ROMSIZE_KB_2048
+ default 0xfff00000 if COREBOOT_ROMSIZE_KB_1024
+ default 0xfff80000 if COREBOOT_ROMSIZE_KB_512
+ default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256
+ default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128
+
+config PAYLOAD_SIZE
+ hex
+ default 0
+
+config ROM_PAYLOAD_START
+ hex
+ default 0xffe00000 if COREBOOT_ROMSIZE_KB_2048
+ default 0xfff00000 if COREBOOT_ROMSIZE_KB_1024
+ default 0xfff80000 if COREBOOT_ROMSIZE_KB_512
+ default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256
+ default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128
+
+config ROM_IMAGE_SIZE
+ hex
+ default 0x200000 if COREBOOT_ROMSIZE_KB_2048
+ default 0x100000 if COREBOOT_ROMSIZE_KB_1024
+ default 0x80000 if COREBOOT_ROMSIZE_KB_512
+ default 0x40000 if COREBOOT_ROMSIZE_KB_256
+ default 0x20000 if COREBOOT_ROMSIZE_KB_128
+
+config RAMBASE
+ hex
+ default 0x100000
+
+config STACK_SIZE
+ hex
+ default 0x8000
+
+
+menu "Misc Options"
+
+config MAX_REBOOT_CNT
+ int "Maximum Reboot Count"
+ default 3
+
+endmenu
+
+
diff --git a/src/arch/i386/Makefile.inc b/src/arch/i386/Makefile.inc
new file mode 100644
index 0000000..4195183
--- /dev/null
+++ b/src/arch/i386/Makefile.inc
@@ -0,0 +1,98 @@
+#######################################################################
+# Take care of subdirectories
+subdirs-y += boot
+subdirs-y += init
+subdirs-y += lib
+subdirs-y += smp
+
+obj-y += ../../option_table.o
+
+ifdef POST_EVALUATION
+#######################################################################
+# Build the final rom image
+
+$(obj)/coreboot.rom: $(obj)/coreboot.bootblock $(obj)/coreboot_ram $(CBFSTOOL)
+ $(Q)rm -f $@
+ $(Q)$(CBFSTOOL) $@ create $(shell expr 1024 \* $(CONFIG_COREBOOT_ROMSIZE_KB)) 131072 $(obj)/coreboot.bootblock
+ $(Q)$(CBFSTOOL) $@ add-stage $(obj)/coreboot_ram normal/coreboot_ram $(CBFS_COMPRESS_FLAG)
+ $(Q)if [ -f fallback/coreboot_apc ]; \
+ then \
+ $(CBFSTOOL) $@ add-stage fallback/coreboot_apc fallback/coreboot_apc $(CBFS_COMPRESS_FLAG); \
+ fi
+ $(Q)$(CBFSTOOL) $@ add-stage $(obj)/coreboot_ram fallback/coreboot_ram $(CBFS_COMPRESS_FLAG)
+ifeq ($(CONFIG_PAYLOAD_NONE),y)
+ $(Q)printf " PAYLOAD none (as specified by user)\n"
+else
+ printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) $(COMPRESSFLAG)\n"
+ $(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) fallback/payload $(CBFS_COMPRESS_FLAG)
+ printf " PAYLOAD $(CONFIG_NORMAL_PAYLOAD_FILE) $(COMPRESSFLAG)\n"
+ $(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_NORMAL_PAYLOAD_FILE) normal/payload $(CBFS_COMPRESS_FLAG)
+ $(CBFSTOOL) ./build/coreboot.rom print
+endif
+
+
+#######################################################################
+# Build the bootblock
+
+BOOTBLOCK_SIZE=65536
+
+$(obj)/coreboot.bootblock: $(obj)/coreboot.strip
+ $(Q)printf " CREATE $(subst $(obj)/,,$(@))\n"
+ $(Q)dd if=$< of=$(obj)/coreboot.bootblock.one obs=$(BOOTBLOCK_SIZE) conv=sync
+ $(Q)cat $(obj)/coreboot.bootblock.one $(obj)/coreboot.bootblock.one > $(obj)/coreboot.bootblock
+
+$(obj)/coreboot.strip: $(obj)/coreboot
+ $(Q)printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
+ $(Q)$(OBJCOPY) -O binary $< $@
+
+$(obj)/ldscript.ld: $(ldscripts) $(obj)/ldoptions
+ $(Q)printf 'INCLUDE "ldoptions"\n' > $@
+ $(Q)printf '$(foreach ldscript,$(ldscripts),INCLUDE "$(ldscript)"\n)' >> $@
+
+$(obj)/crt0_includes.h: $(crt0s)
+ $(Q)printf '$(foreach crt0,$(obj)/config.h $(crt0s),#include "$(crt0)"\n)' > $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/crt0.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s
+ $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $@)/crt0.disasm
+
+$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/crt0_includes.h
+ $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@
+
+$(obj)/coreboot: $(initobjs) $(obj)/ldscript.ld
+ $(Q)printf " LINK $(subst $(obj)/,,$(@))\n"
+ $(Q)$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/ldscript.ld $(initobjs)
+ $(Q)$(NM) -n $(obj)/coreboot | sort > $(obj)/coreboot.map
+
+#######################################################################
+# i386 specific tools
+
+$(obj)/option_table.h $(obj)/option_table.c: $(obj)/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout
+ $(Q)printf " OPTION $(subst $(obj)/,,$(@))\n"
+ $(Q)$(obj)/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --header $(obj)/option_table.h --option $(obj)/option_table.c
+
+$(obj)/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc80/mc146818rtc.h $(top)/src/include/boot/coreboot_tables.h
+ $(Q)printf " HOSTCC $(subst $(obj)/,,$(@))\n"
+ $(Q)$(HOSTCC) $(HOSTCFLAGS) -include $(obj)/config.h $< -o $@
+
+#######################################################################
+# Build the coreboot_ram (stage 2)
+
+$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/config/coreboot_ram.ld #ldoptions
+ $(Q)printf " CC $(subst $(obj)/,,$(@))\n"
+ $(Q)$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/config/coreboot_ram.ld $(obj)/coreboot_ram.o
+ $(Q)$(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map
+
+$(obj)/coreboot_ram.o: $(obj)/arch/i386/lib/c_start.o $(drivers) $(obj)/coreboot.a $(LIBGCC_FILE_NAME)
+ $(Q)printf " CC $(subst $(obj)/,,$(@))\n"
+ $(Q)$(CC) -nostdlib -r -o $@ $(obj)/arch/i386/lib/c_start.o $(drivers) -Wl,-\( $(obj)/coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\)
+
+$(obj)/coreboot.a: $(objs)
+ $(Q)printf " AR $(subst $(obj)/,,$(@))\n"
+ $(Q)rm -f $(obj)/coreboot.a
+ $(Q)$(AR) cr $(obj)/coreboot.a $(objs)
+
+
+#######################################################################
+# done
+
+endif
diff --git a/src/arch/i386/boot/Makefile.inc b/src/arch/i386/boot/Makefile.inc
new file mode 100644
index 0000000..40bb3b8
--- /dev/null
+++ b/src/arch/i386/boot/Makefile.inc
@@ -0,0 +1,10 @@
+
+obj-y += boot.o
+obj-y += coreboot_table.o
+obj-$(CONFIG_MULTIBOOT) += multiboot.o
+obj-y += tables.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += pirq_routing.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.o
+obj-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S
+
diff --git a/src/arch/i386/init/Makefile.inc b/src/arch/i386/init/Makefile.inc
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/arch/i386/init/Makefile.inc
@@ -0,0 +1 @@
+#
diff --git a/src/arch/i386/lib/Makefile.inc b/src/arch/i386/lib/Makefile.inc
new file mode 100644
index 0000000..a1cf617
--- /dev/null
+++ b/src/arch/i386/lib/Makefile.inc
@@ -0,0 +1,15 @@
+obj-y += c_start.o
+obj-y += cpu.o
+obj-y += pci_ops_conf1.o
+obj-y += pci_ops_conf2.o
+obj-y += pci_ops_mmconf.o
+obj-y += pci_ops_auto.o
+obj-y += exception.o
+
+initobj-y += printk_init.o
+initobj-y += cbfs_and_run.o
+
+ifdef POST_EVALUATION
+$(obj)/arch/i386/lib/console.o :: $(obj)/build.h
+endif
+
diff --git a/src/arch/i386/smp/Makefile.inc b/src/arch/i386/smp/Makefile.inc
new file mode 100644
index 0000000..119dd6d
--- /dev/null
+++ b/src/arch/i386/smp/Makefile.inc
@@ -0,0 +1,5 @@
+obj-$(CONFIG_HAVE_MP_TABLE) += mpspec.o
+# what about this: how awkward.
+#object ioapic.o CONFIG_IOAPIC
+
+
diff --git a/src/arch/ppc/Kconfig b/src/arch/ppc/Kconfig
new file mode 100644
index 0000000..23de36c
--- /dev/null
+++ b/src/arch/ppc/Kconfig
@@ -0,0 +1,13 @@
+config ARCH_POWERPC
+ boolean
+ help
+ This option is used to set the architecture of a mainboard.
+ It is usually set in mainboard/*/Kconfig.
+
+config ARCH
+ string
+ default ppc
+ depends on ARCH_POWERPC
+ help
+ This is the name of the respective subdirectory in arch/.
+
diff --git a/src/boot/Makefile.inc b/src/boot/Makefile.inc
new file mode 100644
index 0000000..01542b3
--- /dev/null
+++ b/src/boot/Makefile.inc
@@ -0,0 +1,2 @@
+obj-y += hardwaremain.o
+obj-y += selfboot.o
diff --git a/src/console/Kconfig b/src/console/Kconfig
new file mode 100644
index 0000000..386f839
--- /dev/null
+++ b/src/console/Kconfig
@@ -0,0 +1,40 @@
+menu "Console Options"
+
+config SERIAL_CONSOLE
+ bool "See output on the serial port console"
+ default y
+
+config TTYS0_BASE
+ hex "I/O base for the serial port (default 0x3f8)"
+ depends on SERIAL_CONSOLE
+ default 0x3f8
+
+config SERIAL_SET_SPEED
+ bool "Override the serial console baud rate"
+ default y
+ depends on SERIAL_CONSOLE
+
+config TTYS0_BAUD
+ int "Serial console baud rate (default 115200)"
+ depends on SERIAL_SET_SPEED
+ default 115200
+
+config USBDEBUG_DIRECT
+ bool "Support a USB debug dongle. Not supported on all chipsets. FIX DEPENDENCY HERE"
+ default n
+
+config CONSOLE_VGA
+ bool
+ default n
+
+config MAXIMUM_CONSOLE_LOGLEVEL
+ int
+ default 9
+
+config DEFAULT_CONSOLE_LOGLEVEL
+ int
+ default 9
+
+endmenu
+
+
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
new file mode 100644
index 0000000..242c93e
--- /dev/null
+++ b/src/console/Makefile.inc
@@ -0,0 +1,12 @@
+obj-y += printk.o
+obj-y += console.o
+obj-y += vtxprintf.o
+obj-y += vsprintf.o
+initobj-y += vtxprintf.o
+initobj-y += vsprintf.o
+driver-$(CONFIG_SERIAL_CONSOLE) += uart8250_console.o
+driver-$(CONFIG_USBDEBUG_DIRECT) += usbdebug_direct_console.o
+driver-$(CONFIG_CONSOLE_VGA) += vga_console.o
+driver-$(CONFIG_CONSOLE_BTEXT) += btext_console.o
+driver-$(CONFIG_CONSOLE_BTEXT) += font-8x16.o
+driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.o
diff --git a/src/console/console.c b/src/console/console.c
index 78823af..008130f 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -8,8 +8,6 @@
#include <pc80/mc146818rtc.h>
-static int initialized;
-
/* initialize the console */
void console_init(void)
{
@@ -22,7 +20,6 @@
continue;
driver->init();
}
- initialized = 1;
}
static void __console_tx_byte(unsigned char byte)
@@ -45,8 +42,6 @@
void console_tx_byte(unsigned char byte)
{
- if (!initialized)
- return;
if (byte == '\n')
__console_tx_byte('\r');
__console_tx_byte(byte);
@@ -55,8 +50,6 @@
unsigned char console_rx_byte(void)
{
struct console_driver *driver;
- if (!initialized)
- return 0;
for(driver = console_drivers; driver < econsole_drivers; driver++) {
if (driver->tst_byte)
break;
@@ -70,8 +63,6 @@
int console_tst_byte(void)
{
struct console_driver *driver;
- if (!initialized)
- return 0;
for(driver = console_drivers; driver < econsole_drivers; driver++)
if (driver->tst_byte)
return driver->tst_byte();
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
new file mode 100644
index 0000000..de2ceea
--- /dev/null
+++ b/src/cpu/Kconfig
@@ -0,0 +1,18 @@
+#source src/cpu/amd/Kconfig
+source src/cpu/emulation/Kconfig
+source src/cpu/intel/Kconfig
+source src/cpu/via/Kconfig
+source src/cpu/x86/Kconfig
+source src/cpu/ppc/Kconfig
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffdf8000 if CPU_INTEL_CORE
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000 if CPU_INTEL_CORE
+
+config SMP
+ bool
+ default n
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
new file mode 100644
index 0000000..aa4435f
--- /dev/null
+++ b/src/cpu/Makefile.inc
@@ -0,0 +1,8 @@
+#input amd
+subdirs-y += intel
+subdirs-y += via
+subdirs-y += emulation
+#input ppc
+#input simple_init
+#input via
+#input x86
diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig
new file mode 100644
index 0000000..fdf52fb
--- /dev/null
+++ b/src/cpu/amd/Kconfig
@@ -0,0 +1,8 @@
+source src/cpu/amd/socket_754/Kconfig
+source src/cpu/amd/socket_939/Kconfig
+source src/cpu/amd/socket_940/Kconfig
+source src/cpu/amd/socket_AM2/Kconfig
+source src/cpu/amd/socket_AM2r2/Kconfig
+source src/cpu/amd/socket_F/Kconfig
+source src/cpu/amd/socket_F_1207/Kconfig
+source src/cpu/amd/socket_S1G1/Kconfig
diff --git a/src/cpu/amd/socket_F/Kconfig b/src/cpu/amd/socket_F/Kconfig
new file mode 100644
index 0000000..b63b596
--- /dev/null
+++ b/src/cpu/amd/socket_F/Kconfig
@@ -0,0 +1,3 @@
+config CPU_AMD_SOCKET_F
+ bool
+ default false
diff --git a/src/cpu/emulation/Kconfig b/src/cpu/emulation/Kconfig
new file mode 100644
index 0000000..25d55e6
--- /dev/null
+++ b/src/cpu/emulation/Kconfig
@@ -0,0 +1,2 @@
+source src/cpu/emulation/qemu-x86/Kconfig
+
diff --git a/src/cpu/emulation/Makefile.inc b/src/cpu/emulation/Makefile.inc
new file mode 100644
index 0000000..ac166af
--- /dev/null
+++ b/src/cpu/emulation/Makefile.inc
@@ -0,0 +1 @@
+subdirs-y += qemu-x86
diff --git a/src/cpu/emulation/qemu-x86/Kconfig b/src/cpu/emulation/qemu-x86/Kconfig
new file mode 100644
index 0000000..15b3538
--- /dev/null
+++ b/src/cpu/emulation/qemu-x86/Kconfig
@@ -0,0 +1,4 @@
+config CPU_EMULATION_QEMU_X86
+ bool
+ default false
+
diff --git a/src/cpu/emulation/qemu-x86/Makefile.inc b/src/cpu/emulation/qemu-x86/Makefile.inc
new file mode 100644
index 0000000..840af27d
--- /dev/null
+++ b/src/cpu/emulation/qemu-x86/Makefile.inc
@@ -0,0 +1 @@
+obj-$(CONFIG_CPU_EMULATION_QEMU_X86) += northbridge.o
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
new file mode 100644
index 0000000..87623a3
--- /dev/null
+++ b/src/cpu/intel/Kconfig
@@ -0,0 +1,4 @@
+source src/cpu/intel/model_6ex/Kconfig
+source src/cpu/intel/model_6fx/Kconfig
+source src/cpu/intel/socket_mFCPGA478/Kconfig
+source src/cpu/intel/socket_PGA370/Kconfig
\ No newline at end of file
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
new file mode 100644
index 0000000..afe5cd3
--- /dev/null
+++ b/src/cpu/intel/Makefile.inc
@@ -0,0 +1,14 @@
+# Note: from here on down, we are socket-centric. Socket choice determines what other cpu files are included.
+# Therefore:
+# ONLY include Makefile.inc from socket directories!
+
+subdirs-y += speedstep
+subdirs-y += socket_mFCPGA478
+subdirs-y += socket_PGA370
+
+#socket_mPGA478
+#socket_mPGA479M
+#socket_mPGA603
+#socket_mPGA604
+#socket_mPGA604_533Mhz
+#socket_mPGA604_800Mhz
diff --git a/src/cpu/intel/hyperthreading/Makefile.inc b/src/cpu/intel/hyperthreading/Makefile.inc
new file mode 100644
index 0000000..34cf8ee
--- /dev/null
+++ b/src/cpu/intel/hyperthreading/Makefile.inc
@@ -0,0 +1 @@
+obj-y += intel_sibling.o
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
new file mode 100644
index 0000000..26513df
--- /dev/null
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -0,0 +1 @@
+obj-y += microcode.o
diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc
new file mode 100644
index 0000000..4756e33
--- /dev/null
+++ b/src/cpu/intel/model_69x/Makefile.inc
@@ -0,0 +1 @@
+driver-y += model_69x_init.o
diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc
new file mode 100644
index 0000000..bbadb50
--- /dev/null
+++ b/src/cpu/intel/model_6dx/Makefile.inc
@@ -0,0 +1 @@
+driver-y += model_6dx_init.o
diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig
new file mode 100644
index 0000000..7d5e7692
--- /dev/null
+++ b/src/cpu/intel/model_6ex/Kconfig
@@ -0,0 +1,4 @@
+config CPU_INTEL_CORE
+ bool
+ default n
+ select SMP
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
new file mode 100644
index 0000000..e4676ea
--- /dev/null
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -0,0 +1 @@
+driver-y += model_6ex_init.o
diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig
new file mode 100644
index 0000000..484114c
--- /dev/null
+++ b/src/cpu/intel/model_6fx/Kconfig
@@ -0,0 +1 @@
+# select HAVE_MOVNTI
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
new file mode 100644
index 0000000..4db7801
--- /dev/null
+++ b/src/cpu/intel/model_6fx/Makefile.inc
@@ -0,0 +1 @@
+driver-y += model_6fx_init.o
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
new file mode 100644
index 0000000..a595629
--- /dev/null
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Ron Minnich <rminnich@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+obj-y += model_6xx_init.o
+
diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig
new file mode 100644
index 0000000..d7098b0
--- /dev/null
+++ b/src/cpu/intel/socket_PGA370/Kconfig
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config CPU_INTEL_SOCKET_PGA370
+ bool
+ default false
diff --git a/src/cpu/intel/socket_PGA370/Makefile.inc b/src/cpu/intel/socket_PGA370/Makefile.inc
new file mode 100644
index 0000000..46a851a
--- /dev/null
+++ b/src/cpu/intel/socket_PGA370/Makefile.inc
@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ifeq ($(CONFIG_CPU_INTEL_SOCKET_PGA370),y)
+ obj-y += socket_PGA370.o
+ subdirs-y += ../model_6xx
+ subdirs-y += ../../x86/tsc
+ subdirs-y += ../../x86/mtrr
+ subdirs-y += ../../x86/fpu
+ subdirs-y += ../../x86/mmx
+ subdirs-y += ../../x86/sse
+ subdirs-y += ../../x86/lapic
+ subdirs-y += ../../x86/cache
+ subdirs-y += ../../x86/smm
+ subdirs-y += ../microcode
+endif
+
diff --git a/src/cpu/intel/socket_mFCPGA478/Kconfig b/src/cpu/intel/socket_mFCPGA478/Kconfig
new file mode 100644
index 0000000..0f01535
--- /dev/null
+++ b/src/cpu/intel/socket_mFCPGA478/Kconfig
@@ -0,0 +1,3 @@
+config CPU_INTEL_SOCKET_MFCPGA478
+ bool
+ default false
diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
new file mode 100644
index 0000000..808dd4f
--- /dev/null
+++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
@@ -0,0 +1,17 @@
+ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCPGA478),y)
+ obj-y += socket_mFCPGA478.o
+ subdirs-y += ../model_69x
+ subdirs-y += ../model_6dx
+ subdirs-y += ../model_6ex
+ subdirs-y += ../model_6fx
+ subdirs-y += ../../x86/tsc
+ subdirs-y += ../../x86/mtrr
+ subdirs-y += ../../x86/fpu
+ subdirs-y += ../../x86/mmx
+ subdirs-y += ../../x86/sse
+ subdirs-y += ../../x86/lapic
+ subdirs-y += ../../x86/cache
+ subdirs-y += ../../x86/smm
+ subdirs-y += ../microcode
+ subdirs-y += ../hyperthreading
+endif
diff --git a/src/cpu/intel/speedstep/Makefile.inc b/src/cpu/intel/speedstep/Makefile.inc
new file mode 100644
index 0000000..4351d68
--- /dev/null
+++ b/src/cpu/intel/speedstep/Makefile.inc
@@ -0,0 +1,5 @@
+ifeq ($(CONFIG_HAVE_ACPI_TABLES), y)
+ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCPGA478), y)
+ obj-y += acpi.o
+endif
+endif
diff --git a/src/cpu/ppc/Kconfig b/src/cpu/ppc/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/cpu/ppc/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/cpu/ppc/Makefile.inc b/src/cpu/ppc/Makefile.inc
new file mode 100644
index 0000000..a9cd587
--- /dev/null
+++ b/src/cpu/ppc/Makefile.inc
@@ -0,0 +1,6 @@
+#subdirs-y += ../simple_init
+#subdirs-y += mpc74xx
+#subdirs-y += ppc4xx
+#subdirs-y += ppc7xx
+#subdirs-y += ppc970
+
diff --git a/src/cpu/simple_init/Makefile.inc b/src/cpu/simple_init/Makefile.inc
new file mode 100644
index 0000000..4861359
--- /dev/null
+++ b/src/cpu/simple_init/Makefile.inc
@@ -0,0 +1 @@
+obj-y += simple_cpu_init.o
diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig
new file mode 100644
index 0000000..6927f6d
--- /dev/null
+++ b/src/cpu/via/Kconfig
@@ -0,0 +1 @@
+source src/cpu/via/model_c7/Kconfig
diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc
new file mode 100644
index 0000000..6d62f22
--- /dev/null
+++ b/src/cpu/via/Makefile.inc
@@ -0,0 +1,2 @@
+#subdirs-y += model_c7
+subdirs-y += model_c7
diff --git a/src/cpu/via/model_c7/Kconfig b/src/cpu/via/model_c7/Kconfig
new file mode 100644
index 0000000..e7e2cd4
--- /dev/null
+++ b/src/cpu/via/model_c7/Kconfig
@@ -0,0 +1,3 @@
+config CPU_VIA_C7
+ bool
+ default n
diff --git a/src/cpu/via/model_c7/Makefile.inc b/src/cpu/via/model_c7/Makefile.inc
new file mode 100644
index 0000000..8e645eb
--- /dev/null
+++ b/src/cpu/via/model_c7/Makefile.inc
@@ -0,0 +1,13 @@
+ifeq ($(CONFIG_CPU_VIA_C7),y)
+ subdirs-y += ../../x86/tsc
+ subdirs-y += ../../x86/mtrr
+ subdirs-y += ../../x86/fpu
+ subdirs-y += ../../x86/mmx
+ subdirs-y += ../../x86/sse
+ subdirs-y += ../../x86/lapic
+ subdirs-y += ../../x86/cache
+ subdirs-y += ../../x86/smm
+ subdirs-y += ../../intel/microcode
+endif
+
+obj-y += model_c7_init.o
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
new file mode 100644
index 0000000..b036baf
--- /dev/null
+++ b/src/cpu/x86/Kconfig
@@ -0,0 +1,11 @@
+config SERIAL_CPU_INIT
+ bool
+ default y
+
+config XIP_ROM_BASE
+ hex
+ default 0xfffe0000
+
+config XIP_ROM_BASE
+ hex
+ default 0x2000
diff --git a/src/cpu/x86/cache/Makefile.inc b/src/cpu/x86/cache/Makefile.inc
new file mode 100644
index 0000000..75679e5
--- /dev/null
+++ b/src/cpu/x86/cache/Makefile.inc
@@ -0,0 +1 @@
+obj-y += cache.o
diff --git a/src/cpu/x86/fpu/Makefile.inc b/src/cpu/x86/fpu/Makefile.inc
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/cpu/x86/fpu/Makefile.inc
@@ -0,0 +1 @@
+#
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
new file mode 100644
index 0000000..128deb2
--- /dev/null
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -0,0 +1,4 @@
+obj-y += lapic.o
+obj-y += lapic_cpu_init.o
+obj-y += secondary.o
+
diff --git a/src/cpu/x86/mmx/Makefile.inc b/src/cpu/x86/mmx/Makefile.inc
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/cpu/x86/mmx/Makefile.inc
@@ -0,0 +1 @@
+#
diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc
new file mode 100644
index 0000000..b68873e
--- /dev/null
+++ b/src/cpu/x86/mtrr/Makefile.inc
@@ -0,0 +1 @@
+obj-y += mtrr.o
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
new file mode 100644
index 0000000..6a56601
--- /dev/null
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -0,0 +1,45 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+##if CONFIG_HAVE_SMI_HANDLER
+## object smmrelocate.S
+##
+## smmobject smmhandler.S
+## smmobject smihandler.o
+##
+## makerule smm.o
+## depends "$(SMM-OBJECTS) $(TOP)/src/console/printk.o $(TOP)/src/console/vtxprintf.o $(LIBGCC_FILE_NAME)"
+## action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^"
+## end
+##
+## makerule smm
+## depends "smm.o $(TOP)/src/cpu/x86/smm/smm.ld ldoptions"
+## action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o smm.elf -T $(TOP)/src/cpu/x86/smm/smm.ld smm.o"
+## action "$(CONFIG_CROSS_COMPILE)nm -n smm.elf | sort > smm.map"
+## action "$(OBJCOPY) -O binary smm.elf smm"
+## end
+##
+## makerule smm_bin.c
+## depends "smm"
+## action "(echo 'unsigned char smm[] = {'; od -vtx1 smm | sed -e 's,^[0-9]* *,,' -e 's:[0-9a-f][0-9a-f] :0x&,:g' -e 's:[0-9a-f][0-9a-f]$$:0x&,:'; echo '}; unsigned int smm_len = '; wc -c smm |awk '{print $$1;}' ; echo ';') > smm_bin.c"
+## end
+##
+## object ./smm_bin.o
+##end
diff --git a/src/cpu/x86/sse/Makefile.inc b/src/cpu/x86/sse/Makefile.inc
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/cpu/x86/sse/Makefile.inc
@@ -0,0 +1 @@
+#
diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc
new file mode 100644
index 0000000..93bd137
--- /dev/null
+++ b/src/cpu/x86/tsc/Makefile.inc
@@ -0,0 +1,7 @@
+obj-y += delay_tsc.o
+
+# default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
+# if CONFIG_UDELAY_TSC
+# default CONFIG_HAVE_INIT_TIMER=1
+# object delay_tsc.o
+# end
diff --git a/src/devices/Kconfig b/src/devices/Kconfig
new file mode 100644
index 0000000..6f78cc6
--- /dev/null
+++ b/src/devices/Kconfig
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 coresystems GmbH
+## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+menu "Devices"
+
+config VGA_ROM_RUN
+ bool
+ help
+ Execute PCI/AGP option ROMs if available. This is required to
+ enable PCI/AGP VGA plugin cards.
+
+choice
+ prompt "Execute PCI Option ROMs"
+ default PCI_OPTION_ROM_RUN_REALMODE
+ help
+ Execute PCI/AGP option ROMs if available. You can choose to
+ execute PCI option ROMs natively (32bit x86 system required),
+ in an emulator (x86emu), or ignore option ROM execution.
+
+ config PCI_OPTION_ROM_RUN_REALMODE
+ prompt "Run VGA ROMs"
+ bool
+ select VGA_ROM_RUN
+ help
+ Execute PCI/AGP option ROMs if available. This is required to
+ enable PCI/AGP VGA plugin cards.
+
+ config NO_RUN
+ prompt "DO NOT Run VGA ROMs"
+ bool
+ help
+ Execute PCI/AGP option ROMs if available. This is required to
+ enable PCI/AGP VGA plugin cards.
+
+endchoice
+endmenu
diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc
new file mode 100644
index 0000000..9ef4e69
--- /dev/null
+++ b/src/devices/Makefile.inc
@@ -0,0 +1,21 @@
+obj-y += device.o
+obj-y += root_device.o
+obj-y += device_util.o
+obj-y += pci_device.o
+obj-y += hypertransport.o
+obj-y += pcix_device.o
+obj-y += pciexp_device.o
+obj-y += agp_device.o
+obj-y += cardbus_device.o
+obj-y += pnp_device.o
+obj-y += pci_ops.o
+obj-y += smbus_ops.o
+
+ifeq ($(CONFIG_PCI_ROM_RUN),y)
+obj-$(CONFIG_PCI_ROM_RUN) += pci_rom.o
+subdirs-$(CONFIG_PCI_ROM_RUN) += ../../util/x86emu
+else
+obj-$(CONFIG_VGA_ROM_RUN) += pci_rom.o
+subdirs-$(CONFIG_VGA_ROM_RUN) += ../../util/x86emu
+endif
+
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
new file mode 100644
index 0000000..061728a
--- /dev/null
+++ b/src/drivers/Makefile.inc
@@ -0,0 +1 @@
+subdirs-y += pci
diff --git a/src/drivers/pci/Makefile.inc b/src/drivers/pci/Makefile.inc
new file mode 100644
index 0000000..09ac260
--- /dev/null
+++ b/src/drivers/pci/Makefile.inc
@@ -0,0 +1 @@
+subdirs-y += onboard
diff --git a/src/drivers/pci/onboard/Makefile.inc b/src/drivers/pci/onboard/Makefile.inc
new file mode 100644
index 0000000..5a16314
--- /dev/null
+++ b/src/drivers/pci/onboard/Makefile.inc
@@ -0,0 +1 @@
+obj-y += onboard.o
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
new file mode 100644
index 0000000..1d76aac
--- /dev/null
+++ b/src/lib/Makefile.inc
@@ -0,0 +1,29 @@
+obj-y += clog2.o
+obj-y += uart8250.o
+obj-y += memset.o
+obj-y += memcpy.o
+obj-y += memcmp.o
+obj-y += memmove.o
+obj-y += malloc.o
+obj-y += delay.o
+obj-y += fallback_boot.o
+obj-y += compute_ip_checksum.o
+obj-y += version.o
+obj-y += cbfs.o
+obj-y += lzma.o
+#obj-y += lzmadecode.o
+
+initobj-y += uart8250.o
+initobj-y += memset.o
+initobj-y += memcpy.o
+initobj-y += memcmp.o
+initobj-y += cbfs.o
+initobj-y += lzma.o
+#initobj-y += lzmadecode.o
+
+obj-$(CONFIG_USBDEBUG_DIRECT) += usbdebug_direct.o
+obj-$(CONFIG_COMPRESSED_PAYLOAD_LZMA) += lzma.o
+
+ifdef POST_EVALUATION
+$(obj)/lib/version.o :: $(obj)/build.h
+endif
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
new file mode 100644
index 0000000..14b1d5d
--- /dev/null
+++ b/src/mainboard/Kconfig
@@ -0,0 +1,343 @@
+
+menu "Mainboard"
+
+choice
+ prompt "Mainboard vendor"
+ default VENDOR_EMULATION
+
+config VENDOR_ATREND
+ bool "A-Trend"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_ABIT
+ bool "ABIT"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_ADVANTECH
+ bool "Advantech"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_AGAMI
+ bool "Agami"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_AMD
+ bool "AMD"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_ARIMA
+ bool "Arima"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_ARTEC
+ bool "Artec Group"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_ASI
+ bool "ASI"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_ASUS
+ bool "ASUS"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_AXUS
+ bool "AXUS"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_AZZA
+ bool "Azza"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_BCOM
+ bool "BCOM"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_BIOSTAR
+ bool "Biostar"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_BROADCOM
+ bool "Broadcom"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_COMPAQ
+ bool "Compaq"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_DELL
+ bool "DELL"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_DIGITALLOGIC
+ bool "Digital Logic"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_EAGLELION
+ bool "Eagle Lion"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_EMBEDDEDPLANET
+ bool "Embedded Planet"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_EMULATION
+ bool "Emulation"
+ help
+ Select this option for various system emulators, such as QEMU.
+
+config VENDOR_GIGABYTE
+ bool "Gigabyte"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_HP
+ bool "HP"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_IBM
+ bool "IBM"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_IEI
+ bool "IEI"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_INTEL
+ bool "Intel"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_IWILL
+ bool "Iwill"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_JETWAY
+ bool "Jetway"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_KONTRON
+ bool "Kontron"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_LIPPERT
+ bool "Lippert"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_MOTOROLA
+ bool "Motorola"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_MSI
+ bool "MSI"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_NEC
+ bool "NEC"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_NEWISYS
+ bool "Newisys"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_NVIDIA
+ bool "NVidia"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_OLPC
+ bool "OLPC"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_PCENGINES
+ bool "PC Engines"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_RCA
+ bool "RCA"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_SUNW
+ bool "SUN Microsystems"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_SUPERMICRO
+ bool "Supermicro"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_TECHNEXION
+ bool "Technexion"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_THOMSON
+ bool "Thomson"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_TOTALIMPACT
+ bool "Total Impact"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_TYAN
+ bool "Tyan"
+ help
+ Select this option for systems from the vendor.
+
+config VENDOR_VIA
+ bool "VIA"
+ help
+ Select this option for systems from the vendor.
+
+endchoice
+
+config MAINBOARD_VENDOR
+ string
+ default "EMULATION"
+ depends on VENDOR_EMULATION
+
+config MAINBOARD_VENDOR
+ string
+ default "KONTRON"
+ depends on VENDOR_KONTRON
+
+config MAINBOARD_VENDOR
+ string
+ default "VIA"
+ depends on VENDOR_VIA
+
+config MAINBOARD_VENDOR
+ string
+ default "AMD"
+ depends on VENDOR_AMD
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1019
+ depends on VENDOR_VIA
+
+source "src/mainboard/a-trend/Kconfig"
+source "src/mainboard/abit/Kconfig"
+source "src/mainboard/advantech/Kconfig"
+source "src/mainboard/amd/Kconfig"
+source "src/mainboard/arima/Kconfig"
+source "src/mainboard/artecgroup/Kconfig"
+source "src/mainboard/asi/Kconfig"
+source "src/mainboard/asus/Kconfig"
+source "src/mainboard/axus/Kconfig"
+source "src/mainboard/azza/Kconfig"
+source "src/mainboard/bcom/Kconfig"
+source "src/mainboard/biostar/Kconfig"
+source "src/mainboard/broadcom/Kconfig"
+source "src/mainboard/compaq/Kconfig"
+source "src/mainboard/dell/Kconfig"
+source "src/mainboard/digitallogic/Kconfig"
+source "src/mainboard/eaglelion/Kconfig"
+source "src/mainboard/embeddedplanet/Kconfig"
+source "src/mainboard/emulation/Kconfig"
+source "src/mainboard/gigabyte/Kconfig"
+source "src/mainboard/hp/Kconfig"
+source "src/mainboard/ibm/Kconfig"
+source "src/mainboard/iei/Kconfig"
+source "src/mainboard/intel/Kconfig"
+source "src/mainboard/iwill/Kconfig"
+source "src/mainboard/jetway/Kconfig"
+source "src/mainboard/kontron/Kconfig"
+source "src/mainboard/lippert/Kconfig"
+source "src/mainboard/motorola/Kconfig"
+source "src/mainboard/msi/Kconfig"
+source "src/mainboard/nec/Kconfig"
+source "src/mainboard/newisys/Kconfig"
+source "src/mainboard/nvidia/Kconfig"
+source "src/mainboard/olpc/Kconfig"
+source "src/mainboard/pcengines/Kconfig"
+source "src/mainboard/rca/Kconfig"
+source "src/mainboard/sunw/Kconfig"
+source "src/mainboard/supermicro/Kconfig"
+source "src/mainboard/technexion/Kconfig"
+source "src/mainboard/technologic/Kconfig"
+source "src/mainboard/televideo/Kconfig"
+source "src/mainboard/thomson/Kconfig"
+source "src/mainboard/totalimpact/Kconfig"
+source "src/mainboard/tyan/Kconfig"
+source "src/mainboard/via/Kconfig"
+
+choice
+ prompt "ROM chip size"
+ default COREBOOT_ROMSIZE_KB_256
+
+config COREBOOT_ROMSIZE_KB_128
+ bool "128 KB"
+ help
+ Choose this option if you have a 128 KB ROM chip.
+
+config COREBOOT_ROMSIZE_KB_256
+ bool "256 KB"
+ help
+ Choose this option if you have a 256 KB ROM chip.
+
+config COREBOOT_ROMSIZE_KB_512
+ bool "512 KB"
+ help
+ Choose this option if you have a 512 KB ROM chip.
+
+config COREBOOT_ROMSIZE_KB_1024
+ bool "1024 KB (1 MB)"
+ help
+ Choose this option if you have a 1024 KB (1 MB) ROM chip.
+
+config COREBOOT_ROMSIZE_KB_2048
+ bool "2048 KB (2 MB)"
+ help
+ Choose this option if you have a 2048 KB (2 MB) ROM chip.
+
+endchoice
+
+config COREBOOT_ROMSIZE_KB
+ int
+ default 128 if COREBOOT_ROMSIZE_KB_128
+ default 256 if COREBOOT_ROMSIZE_KB_256
+ default 512 if COREBOOT_ROMSIZE_KB_512
+ default 1024 if COREBOOT_ROMSIZE_KB_1024
+ default 2048 if COREBOOT_ROMSIZE_KB_2048
+ help
+ Map the config names to an integer.
+
+endmenu
+
diff --git a/src/mainboard/a-trend/Kconfig b/src/mainboard/a-trend/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/a-trend/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/a-trend/atc-6220/devicetree.cb b/src/mainboard/a-trend/atc-6220/devicetree.cb
new file mode 100644
index 0000000..700f7c4
--- /dev/null
+++ b/src/mainboard/a-trend/atc-6220/devicetree.cb
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 7.0 on # ISA bridge
+ chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.3 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.6 on # Consumer IR
+ end
+ device pnp 3f0.7 on # GPIO 1
+ end
+ device pnp 3f0.8 on # GPIO 2
+ end
+ device pnp 3f0.a on # ACPI
+ end
+ end
+ end
+ device pci 7.1 on end # IDE
+ device pci 7.2 on end # USB
+ device pci 7.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "0"
+ register "ide0_drive1_udma33_enable" = "0"
+ register "ide1_drive0_udma33_enable" = "0"
+ register "ide1_drive1_udma33_enable" = "0"
+ end
+ end
+end
diff --git a/src/mainboard/a-trend/atc-6240/devicetree.cb b/src/mainboard/a-trend/atc-6240/devicetree.cb
new file mode 100644
index 0000000..2a8caec
--- /dev/null
+++ b/src/mainboard/a-trend/atc-6240/devicetree.cb
@@ -0,0 +1,69 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 7.0 on # ISA bridge
+ chip superio/winbond/w83627hf # Super I/O
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.3 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.6 on # Consumer IR
+ io 0x60 = 0x00
+ end
+ device pnp 3f0.7 on # Game port / MIDI / GPIO 1
+ io 0x60 = 0x201
+ io 0x62 = 0x330
+ irq 0x70 = 9
+ end
+ device pnp 3f0.8 off # GPIO 2 / WDT
+ end
+ device pnp 3f0.9 off # GPIO 3
+ end
+ device pnp 3f0.a off # ACPI
+ end
+ device pnp 3f0.b off # HWM (TODO)
+ end
+ end
+ end
+ device pci 7.1 on end # IDE
+ device pci 7.2 on end # USB
+ device pci 7.3 on end # ACPI
+ device pci c.0 on end # Onboard audio (ES1371)
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "0"
+ register "ide0_drive1_udma33_enable" = "0"
+ register "ide1_drive0_udma33_enable" = "0"
+ register "ide1_drive1_udma33_enable" = "0"
+ end
+ end
+end
diff --git a/src/mainboard/abit/Kconfig b/src/mainboard/abit/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/abit/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/abit/be6-ii_v2_0/devicetree.cb b/src/mainboard/abit/be6-ii_v2_0/devicetree.cb
new file mode 100644
index 0000000..d2200d2
--- /dev/null
+++ b/src/mainboard/abit/be6-ii_v2_0/devicetree.cb
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 7.0 on # ISA bridge
+ chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.3 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.6 on # Consumer IR
+ end
+ device pnp 3f0.7 on # GPIO 1
+ end
+ device pnp 3f0.8 on # GPIO 2
+ end
+ device pnp 3f0.a on # ACPI
+ end
+ end
+ end
+ device pci 7.1 on end # IDE, UDMA/33 (part of 82371EB)
+ device pci 7.2 on end # USB
+ device pci 7.3 on end # ACPI
+ device pci 13.0 on end # IDE, UDMA/66 (HPT366 controller)
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ register "ide0_drive0_udma33_enable" = "1"
+ register "ide0_drive1_udma33_enable" = "1"
+ register "ide1_drive0_udma33_enable" = "1"
+ register "ide1_drive1_udma33_enable" = "1"
+ end
+ end
+end
diff --git a/src/mainboard/advantech/Kconfig b/src/mainboard/advantech/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/advantech/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/advantech/pcm-5820/devicetree.cb b/src/mainboard/advantech/pcm-5820/devicetree.cb
new file mode 100644
index 0000000..b416e9a
--- /dev/null
+++ b/src/mainboard/advantech/pcm-5820/devicetree.cb
@@ -0,0 +1,56 @@
+chip northbridge/amd/gx1 # Northbridge
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ chip southbridge/amd/cs5530 # Southbridge
+ device pci 12.0 on # ISA bridge
+ chip superio/winbond/w83977f # SUper I/O
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.4 on # RTC / On-Now control
+ io 0x60 = 0x70
+ irq 0x70 = 8
+ end
+ device pnp 3f0.5 on # PS/2 keyboard / mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.6 on # IR
+ # TODO?
+ end
+ device pnp 3f0.7 on # GPIO 1
+ # TODO?
+ end
+ device pnp 3f0.8 on # GPIO 2
+ # TODO?
+ end
+ end
+ end
+ device pci 12.1 on end # SMI
+ device pci 12.2 on end # IDE
+ device pci 12.3 on end # Audio (onboard)
+ device pci 12.4 on end # VGA
+ device pci 13.0 on end # USB
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end
+ chip cpu/amd/model_gx1 # CPU
+ end
+end
diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig
new file mode 100644
index 0000000..f16f5e1
--- /dev/null
+++ b/src/mainboard/amd/Kconfig
@@ -0,0 +1 @@
+source "src/mainboard/amd/serengeti_cheetah/Kconfig"
\ No newline at end of file
diff --git a/src/mainboard/amd/db800/devicetree.cb b/src/mainboard/amd/db800/devicetree.cb
new file mode 100644
index 0000000..d79fb51
--- /dev/null
+++ b/src/mainboard/amd/db800/devicetree.cb
@@ -0,0 +1,68 @@
+chip northbridge/amd/lx
+ device pci_domain 0 on
+ device pci 1.0 on end # Northbridge
+ device pci 1.1 on end # Graphics
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
+ register "lpc_serirq_enable" = "0x0000105a"
+ register "lpc_serirq_polarity" = "0x0000EFA5"
+ register "lpc_serirq_mode" = "1"
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "1" # 0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "0"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci d.0 on end # Ethernet
+ device pci e.0 on end # Slot1
+ device pci f.0 on # ISA Bridge
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off end # Com2
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b off end # HW Monitor
+ end
+ end
+ device pci f.2 on end # IDE Controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+ # APIC cluster is late CPU init.
+ device apic_cluster 0 on
+ chip cpu/amd/model_lx
+ device apic 0 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/amd/dbm690t/devicetree.cb b/src/mainboard/amd/dbm690t/devicetree.cb
new file mode 100644
index 0000000..d873681
--- /dev/null
+++ b/src/mainboard/amd/dbm690t/devicetree.cb
@@ -0,0 +1,117 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_S1G1
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # southbridge
+ chip southbridge/amd/rs690
+ device pci 0.0 on end # HT 0x7910
+ device pci 1.0 on # Internal Graphics P2P bridge 0x7912
+ chip drivers/pci/onboard
+ device pci 5.0 on end # Internal Graphics 0x791F
+ register "rom_address" = "0xfff00000"
+ end
+ end
+ device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
+ device pci 3.0 off end # PCIE P2P bridge 0x791b
+ device pci 4.0 on end # PCIE P2P bridge 0x7914
+ device pci 5.0 on end # PCIE P2P bridge 0x7915
+ device pci 6.0 on end # PCIE P2P bridge 0x7916
+ device pci 7.0 on end # PCIE P2P bridge 0x7917
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ register "vga_rom_address" = "0xfff00000"
+ register "gpp_configuration" = "4"
+ register "port_enable" = "0xfc"
+ register "gfx_dev2_dev3" = "1"
+ register "gfx_dual_slot" = "0"
+ register "gfx_lane_reversal" = "0"
+ register "gfx_tmds" = "0"
+ register "gfx_compliance" = "0"
+ register "gfx_reconfiguration" = "1"
+ register "gfx_link_width" = "0"
+ end
+ chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
+ device pci 12.0 on end # SATA 0x4380
+ device pci 13.0 on end # USB 0x4387
+ device pci 13.1 on end # USB 0x4388
+ device pci 13.2 on end # USB 0x4389
+ device pci 13.3 on end # USB 0x438a
+ device pci 13.4 on end # USB 0x438b
+ device pci 13.5 on end # USB 2 0x4386
+ device pci 14.0 on # SM 0x4385
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ end # SM
+ device pci 14.1 on end # IDE 0x438c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x438d
+ chip superio/ite/it8712f
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 off end # EC
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 on # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
+ end
+ device pnp 2e.8 off # MIDI
+ io 0x60 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.9 off # GAME
+ io 0x60 = 0x220
+ end
+ device pnp 2e.a off end # CIR
+ end #superio/ite/it8712f
+ end #LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 on end # ACI 0x4382
+ device pci 14.6 on end # MCI 0x438e
+ register "ide0_enable" = "1"
+ register "sata0_enable" = "1"
+ register "hda_viddid" = "0x10ec0882"
+ end #southbridge/amd/sb600
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end #northbridge/amd/amdk8
+ end #pci_domain
+end #northbridge/amd/amdk8/root_complex
+
diff --git a/src/mainboard/amd/norwich/devicetree.cb b/src/mainboard/amd/norwich/devicetree.cb
new file mode 100644
index 0000000..bc08b95
--- /dev/null
+++ b/src/mainboard/amd/norwich/devicetree.cb
@@ -0,0 +1,41 @@
+chip northbridge/amd/lx
+ device pci_domain 0 on
+ device pci 1.0 on end # Northbridge
+ device pci 1.1 on end # Graphics
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+ register "lpc_serirq_enable" = "0x00001002"
+ register "lpc_serirq_polarity" = "0x0000EFFD"
+ register "lpc_serirq_mode" = "1"
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" #0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "1"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci b.0 on end # Slot 3
+ device pci c.0 on end # Slot 4
+ device pci d.0 on end # Slot 1
+ device pci e.0 on end # Slot 2
+ device pci f.0 on end # ISA Bridge
+ device pci f.2 on end # IDE Controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+ # APIC cluster is late CPU init.
+ device apic_cluster 0 on
+ chip cpu/amd/model_lx
+ device apic 0 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/amd/pistachio/devicetree.cb b/src/mainboard/amd/pistachio/devicetree.cb
new file mode 100644
index 0000000..0306417
--- /dev/null
+++ b/src/mainboard/amd/pistachio/devicetree.cb
@@ -0,0 +1,77 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_AM2
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # southbridge, K8 HT Configuration
+ chip southbridge/amd/rs690
+ device pci 0.0 on end # HT 0x7910
+ # device pci 0.1 off end # CLK
+ device pci 1.0 on # Internal Graphics P2P bridge 0x7912
+ chip drivers/pci/onboard
+ device pci 5.0 on end # Internal Graphics 0x791F
+ register "rom_address" = "0xfff00000"
+ end
+ end
+ device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
+ device pci 3.0 off end # PCIE P2P bridge 0x791b
+ device pci 4.0 on end # PCIE P2P bridge 0x7914
+ device pci 5.0 on end # PCIE P2P bridge 0x7915
+ device pci 6.0 on end # PCIE P2P bridge 0x7916
+ device pci 7.0 on end # PCIE P2P bridge 0x7917
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ register "vga_rom_address" = "0xfff00000"
+ register "gpp_configuration" = "4"
+ register "port_enable" = "0xfc"
+ register "gfx_dev2_dev3" = "1"
+ register "gfx_dual_slot" = "0"
+ register "gfx_lane_reversal" = "0"
+ register "gfx_tmds" = "0"
+ register "gfx_compliance" = "0"
+ register "gfx_reconfiguration" = "1"
+ register "gfx_link_width" = "0"
+ end
+ chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
+ device pci 12.0 on end # SATA 0x4380
+ device pci 13.0 on end # USB 0x4387
+ device pci 13.1 on end # USB 0x4388
+ device pci 13.2 on end # USB 0x4389
+ device pci 13.3 on end # USB 0x438a
+ device pci 13.4 on end # USB 0x438b
+ device pci 13.5 on end # USB 2 0x4386
+ device pci 14.0 on # SM 0x4385
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 off end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 off end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 off end
+ end
+ end # SM
+ device pci 14.1 on end # IDE 0x438c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on end # LPC 0x438d
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 on end # ACI 0x4382
+ device pci 14.6 on end # MCI 0x438e
+ register "ide0_enable" = "1"
+ register "sata0_enable" = "1"
+ register "hda_viddid" = "0x10ec0882"
+ end #southbridge/amd/sb600
+ end # device pci 18.0
+
+ device pci 18.1 on end # K8 Address Map
+ device pci 18.2 on end # K8 DRAM Controller and HT Trace Mode
+ device pci 18.3 on end # K8 Miscellaneous Control
+ end #northbridge/amd/amdk8
+ end #pci_domain
+end #northbridge/amd/amdk8/root_complex
+
diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb
new file mode 100644
index 0000000..8c7de64
--- /dev/null
+++ b/src/mainboard/amd/rumba/devicetree.cb
@@ -0,0 +1,21 @@
+chip northbridge/amd/gx2
+ device apic_cluster 0 on
+ chip cpu/amd/model_gx2
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ device pci 1.0 on end
+ device pci 1.1 on end
+ chip southbridge/amd/cs5536
+ register "lpc_serirq_enable" = "0x80" # enabled with default timing
+ device pci d.0 on end # Realtek 8139 LAN
+ device pci f.0 on end # ISA Bridge
+ device pci f.2 on end # IDE Controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.4 on end # UHCI
+ end
+ end
+end
+
diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig
new file mode 100644
index 0000000..bb1571d
--- /dev/null
+++ b/src/mainboard/amd/serengeti_cheetah/Kconfig
@@ -0,0 +1,49 @@
+choice
+ prompt "Mainboard model"
+ depends on VENDOR_AMD
+
+config BOARD_AMD_SERENGETI_CHEETAH
+ bool "SERENGETI_CHEETAH"
+ select ARCH_X86
+ select CPU_AMD_K8
+ select CPU_AMD_SOCKET_F
+ select NORTHBRIDGE_AMD_AMDK8
+ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+ select SOUTHBRIDGE_AMD_AMD8111
+ select SUPERIO_WINBOND_W83627THF
+ select PIRQ_TABLE
+ select MMCONF_SUPPORT
+ select USE_PRINTK_IN_CAR
+ help
+ AMD Serengeti Series mainboards
+endchoice
+
+config MAINBOARD_DIR
+ string
+ default amd/serengeti_cheetah
+ depends on BOARD_AMD_SERENGETI_CHEETAH
+
+#config DCACHE_RAM_BASE
+# hex
+# default 0xffdf8000
+# depends on BOARD_AMD_SERENGETI_CHEETAH
+#
+#config DCACHE_RAM_SIZE
+# hex
+# default 0x8000
+# depends on BOARD_AMD_SERENGETI_CHEETAH
+
+config LB_CKS_RANGE_END
+ int
+ default 122
+ depends on BOARD_AMD_SERENGETI_CHEETAH
+
+config LB_CKS_LOC
+ int
+ default 123
+ depends on BOARD_AMD_SERENGETI_CHEETAH
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Serengeti-Cheetah"
+ depends on BOARD_AMD_SERENGETI_CHEETAH
diff --git a/src/mainboard/amd/serengeti_cheetah/Makefile.inc b/src/mainboard/amd/serengeti_cheetah/Makefile.inc
new file mode 100644
index 0000000..c54df30
--- /dev/null
+++ b/src/mainboard/amd/serengeti_cheetah/Makefile.inc
@@ -0,0 +1,95 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
+##
+
+driver-y += mainboard.o
+
+#needed by irq_tables and mptable and acpi_tables
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
+
+#./ssdt.o is in northbridge/amd/amdk8/Config.lb
+obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o
+obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += ssdt4.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+MAINBOARD_OPTIONS=\
+ -DCONFIG_AP_IN_SIPI_WAIT=1 \
+ -DCONFIG_USE_PRINTK_IN_CAR=1 \
+ -DCONFIG_HAVE_HIGH_TABLES=1 \
+ -DCONFIG_MMCONF_SUPPORT=1 \
+ -DCONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+ iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+ mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
+ iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+ perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
+ mv pci2.hex ssdt2.c
+
+$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
+ iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
+ perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
+ mv pci3.hex ssdt3.c
+
+$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
+ iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+ perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
+ mv pci4.hex ssdt4.c
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+ perl -e 's/\.rodata/.rom.data/g' -pi $@
+ perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+
diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb
new file mode 100644
index 0000000..b9742b4
--- /dev/null
+++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb
@@ -0,0 +1,159 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_F
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/amd/amd8132
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on
+ chip drivers/i2c/i2cmux # pca9556 smbus mux
+ device i2c 18 on #0 pca9516 1
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ end
+ device i2c 18 on #1 pca9516 2
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-2-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-2-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-3-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-3-1
+ device i2c 57 on end
+ end
+ end
+ end
+ end # acpi
+ device pci 1.5 off end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ chip northbridge/amd/amdk8
+ device pci 19.0 on # northbridge
+ chip southbridge/amd/amd8151
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 1.0 on end
+ end
+ end # device pci 19.0
+
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+
+
+ end #pci_domain
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 off end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 off end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# end
+
+end
+
+
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
new file mode 100644
index 0000000..71c4daa
--- /dev/null
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
@@ -0,0 +1,152 @@
+chip northbridge/amd/amdfam10/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_F_1207 #L1 and DDR2
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdfam10
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/amd/amd8132
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on
+ chip drivers/i2c/i2cmux2 # pca9556 smbus mux
+ chip drivers/i2c/i2cmux2 # pca9556 smbus mux
+ device i2c 18 on #0 pca9516 1
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ end
+ device i2c 18 on #1 pca9516 2
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 53 on end
+ end
+ end
+ end
+ end
+ end # acpi
+ device pci 1.5 off end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+# device pci 00.5 on end
+ end
+ end #pci_domain
+ #for node 32 to node 63
+# device pci_domain 0 on
+# chip northbridge/amd/amdfam10
+# device pci 00.0 on end# northbridge
+# device pci 00.0 on end
+# device pci 00.0 on end
+# device pci 00.0 on end
+# device pci 00.1 on end
+# device pci 00.2 on end
+# device pci 00.3 on end
+# device pci 00.4 on end
+# device pci 00.5 on end
+# end
+# end #pci_domain
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 off end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 off end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# device pnp 0.8 off end # hard reset
+# device pnp 0.9 off end # mcp55
+# device pnp 0.a on end # GH ext table
+# end
+
+end
+
+
diff --git a/src/mainboard/arima/Kconfig b/src/mainboard/arima/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/arima/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/arima/hdama/devicetree.cb b/src/mainboard/arima/hdama/devicetree.cb
new file mode 100644
index 0000000..2552e18
--- /dev/null
+++ b/src/mainboard/arima/hdama/devicetree.cb
@@ -0,0 +1,196 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on # PCIX bridge
+ ## On board NIC A
+ #chip drivers/generic/generic
+ # device pci 3.0 on
+ # irq 0 = 0x13
+ # end
+ #end
+ ## On board NIC B
+ #chip drivers/generic/generic
+ # device pci 4.0 on
+ # irq 0 = 0x13
+ # end
+ #end
+ ## PCI Slot 3
+ #chip drivers/generic/generic
+ # device pci 1.0 on
+ # irq 0 = 0x11
+ # irq 1 = 0x12
+ # irq 2 = 0x13
+ # irq 3 = 0x10
+ # end
+ #end
+ ## PCI Slot 4
+ #chip drivers/generic/generic
+ # device pci 2.0 on
+ # irq 0 = 0x12
+ # irq 1 = 0x13
+ # irq 2 = 0x10
+ # irq 3 = 0x11
+ # end
+ #end
+ end
+ device pci 0.1 on end # IOAPIC
+ device pci 1.0 on # PCIX bridge
+ ## PCI Slot 1
+ #chip drivers/generic/generic
+ # device pci 1.0 on
+ # irq 0 = 0x11
+ # irq 1 = 0x12
+ # irq 2 = 0x13
+ # irq 3 = 0x10
+ # end
+ #end
+ ## PCI Slot 2
+ #chip drivers/generic/generic
+ # device pci 2.0 on
+ # irq 0 = 0x12
+ # irq 1 = 0x13
+ # irq 2 = 0x10
+ # irq 3 = 0x11
+ # end
+ #end
+ end
+ device pci 1.1 on end # IOAPIC
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent of the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end # USB0
+ device pci 0.1 on end # USB1
+ device pci 0.2 off end # USB 2.0
+ device pci 1.0 off end # LAN
+ chip drivers/pci/onboard
+ device pci 6.0 on end # ATI Rage XL
+ register "rom_address" = "0xfff80000"
+ end
+ ## PCI Slot 5 (correct?)
+ #chip drivers/generic/generic
+ # device pci 5.0 on
+ # irq 0 = 0x11
+ # irq 1 = 0x12
+ # irq 2 = 0x13
+ # irq 3 = 0x10
+ # end
+ #end
+ ## PCI Slot 6 (correct?)
+ #chip drivers/generic/generic
+ # device pci 4.0 on
+ # irq 0 = 0x10
+ # irq 1 = 0x11
+ # irq 2 = 0x12
+ # irq 3 = 0x13
+ # end
+ #end
+
+ end
+ # LPC bridge
+ device pci 1.0 on
+ chip superio/nsc/pc87360
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 off # Com 2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Com 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 off end # SWC
+ device pnp 2e.5 off end # Mouse
+ device pnp 2e.6 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.8 off end # ACB
+ device pnp 2e.9 off end # FSCM
+ device pnp 2e.a off end # WDT
+ end
+ end
+ device pci 1.1 on end # IDE
+ device pci 1.2 on end # SMBus 2.0
+ device pci 1.3 on # System Management
+ chip drivers/generic/generic
+ #phillips pca9545 smbus mux
+ device i2c 70 on
+ # analog_devices adm1026
+ chip drivers/generic/generic
+ device i2c 2c on end
+ end
+ end
+ device i2c 70 on end
+ device i2c 70 on end
+ device i2c 70 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ end
+ device pci 1.5 off end # AC97 Audio
+ device pci 1.6 on end # AC97 Modem
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+
+ device pci 18.0 on end # LDT1
+ device pci 18.0 on end # LDT2
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end # chip northbridge/amd/amdk8
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/artecgroup/Kconfig b/src/mainboard/artecgroup/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/artecgroup/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/artecgroup/dbe61/devicetree.cb b/src/mainboard/artecgroup/dbe61/devicetree.cb
new file mode 100644
index 0000000..16e97fc
--- /dev/null
+++ b/src/mainboard/artecgroup/dbe61/devicetree.cb
@@ -0,0 +1,42 @@
+chip northbridge/amd/lx
+ device pci_domain 0 on
+ device pci 1.0 on end # Northbridge
+ device pci 1.1 on end # Graphics
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+ register "lpc_serirq_enable" = "0x00001002"
+ register "lpc_serirq_polarity" = "0x0000EFFD"
+ register "lpc_serirq_mode" = "1"
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" #0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "0"
+ register "com1_address" = "0x2F8"
+ register "com1_irq" = "3"
+ register "com2_enable" = "1"
+ register "com2_address" = "0x3F8"
+ register "com2_irq" = "4"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci b.0 on end # Slot 3
+ device pci c.0 on end # Slot 4
+ device pci d.0 on end # Slot 1
+ device pci e.0 on end # Slot 2
+ device pci f.0 on end # ISA Bridge
+ device pci f.2 on end # IDE Controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+ # APIC cluster is late CPU init.
+ device apic_cluster 0 on
+ chip cpu/amd/model_lx
+ device apic 0 on end
+ end
+ end
+
+end
+
diff --git a/src/mainboard/asi/Kconfig b/src/mainboard/asi/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/asi/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/asi/mb_5blgp/devicetree.cb b/src/mainboard/asi/mb_5blgp/devicetree.cb
new file mode 100644
index 0000000..f50be6e
--- /dev/null
+++ b/src/mainboard/asi/mb_5blgp/devicetree.cb
@@ -0,0 +1,55 @@
+chip northbridge/amd/gx1 # Northbridge
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ chip southbridge/amd/cs5530 # Southbridge
+ device pci 0f.0 on end # Ethernet
+ device pci 12.0 on # ISA bridge
+ chip superio/nsc/pc87351 # Super I/O
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.e on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 on # System wake-up control (SWC)
+ irq 0x60 = 0x500
+ end
+ device pnp 2e.5 on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.6 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.7 on # GPIO
+ irq 0x60 = 0x800
+ end
+ device pnp 2e.8 on # Fan speed control
+ irq 0x60 = 0x900
+ end
+ end
+ end
+ device pci 12.1 off end # SMI
+ device pci 12.2 on end # IDE
+ device pci 12.3 on end # Audio
+ device pci 12.4 on end # VGA
+ device pci 13.0 on end # USB
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "0" # No connector on this board
+ end
+ end
+ chip cpu/amd/model_gx1 # CPU
+ end
+end
diff --git a/src/mainboard/asi/mb_5blmp/devicetree.cb b/src/mainboard/asi/mb_5blmp/devicetree.cb
new file mode 100644
index 0000000..8ec750c
--- /dev/null
+++ b/src/mainboard/asi/mb_5blmp/devicetree.cb
@@ -0,0 +1,56 @@
+chip northbridge/amd/gx1 # Northbridge
+ device pci_domain 0 on
+ device pci 0.0 on end # Host bridge
+ chip southbridge/amd/cs5530 # Southbridge
+ device pci 0f.0 off end # Ethernet (Realtek RTL8139B)
+ device pci 12.0 on # ISA bridge
+ chip superio/nsc/pc87351 # Super I/O
+ device pnp 2e.4 on # PS/2 keyboard (+ mouse?)
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ # irq 0x72 = 12
+ end
+ device pnp 2e.a on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.e on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.f off # Floppy
+ io 0x60 = 0x3f2
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.10 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.12 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ end
+ end
+ device pci 12.1 off end # SMI
+ device pci 12.2 on end # IDE
+ device pci 12.3 on end # Audio
+ device pci 12.4 on end # VGA (onboard)
+ # device pci 12.4 on # VGA (onboard)
+ # chip drivers/pci/onboard
+ # device pci 12.4 on end
+ # register "rom_address" = "0xfffc0000" # 256 KB image
+ # # register "rom_address" = "0xfff80000" # 512 KB image
+ # # register "rom_address" = "0xfff00000" # 1 MB image
+ # end
+ # end
+ device pci 13.0 on end # USB
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end
+ chip cpu/amd/model_gx1 # CPU
+ end
+end
+
diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/asus/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/asus/a8n_e/devicetree.cb b/src/mainboard/asus/a8n_e/devicetree.cb
new file mode 100644
index 0000000..ee8a7b4
--- /dev/null
+++ b/src/mainboard/asus/a8n_e/devicetree.cb
@@ -0,0 +1,130 @@
+chip northbridge/amd/amdk8/root_complex # Root complex
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/amd/socket_939 # Socket 939 CPU
+ device apic 0 on end # APIC
+ end
+ end
+
+ device pci_domain 0 on # PCI domain
+ chip northbridge/amd/amdk8 # mc0
+ device pci 18.0 on # Northbridge
+ # Devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/ck804 # Southbridge
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/ite/it8712f # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2 (N/A on this board)
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.4 on # Environment controller
+ io 0x60 = 0x290
+ io 0x62 = 0x0000
+ irq 0x70 = 0x00
+ end
+ device pnp 2e.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x71 = 2
+ end
+ device pnp 2e.6 on # PS/2 mouse
+ irq 0x70 = 12
+ irq 0x71 = 2
+ end
+ device pnp 2e.7 on # GPIO config
+ io 0x60 = 0x0800
+ # Set GPIO 1 & 2
+ io 0x25 = 0x0000
+ # Set GPIO 3 & 4
+ io 0x27 = 0x2540
+ # GPIO Polarity for Set 3
+ io 0xb2 = 0x2100
+ # GPIO Pin Internal Pull up for Set 3
+ io 0xba = 0x0100
+ # Simple I/O register config
+ io 0xc0 = 0x0000
+ io 0xc2 = 0x2540
+ io 0xc8 = 0x0000
+ io 0xca = 0x0500
+ end
+ device pnp 2e.8 on # Midi port
+ io 0x60 = 0x300
+ irq 0x70 = 10
+ end
+ device pnp 2e.9 on # Game port
+ io 0x60 = 0x201
+ end
+ device pnp 2e.a off # IR (N/A on this board)
+ io 0x60 = 0x310
+ irq 0x70 = 11
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ # chip drivers/generic/generic #dimm 0-0-0
+ # device i2c 50 on end
+ # end
+ # chip drivers/generic/generic #dimm 0-0-1
+ # device i2c 51 on end
+ # end
+ # chip drivers/generic/generic #dimm 0-1-0
+ # device i2c 52 on end
+ # end
+ # chip drivers/generic/generic #dimm 0-1-1
+ # device i2c 53 on end
+ # end
+ # chip drivers/generic/generic #dimm 1-0-0
+ # device i2c 54 on end
+ # end
+ # chip drivers/generic/generic #dimm 1-0-1
+ # device i2c 55 on end
+ # end
+ # chip drivers/generic/generic #dimm 1-1-0
+ # device i2c 56 on end
+ # end
+ # chip drivers/generic/generic #dimm 1-1-1
+ # device i2c 57 on end
+ # end
+ end
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # Onboard audio (ACI)
+ device pci 4.1 off end # Onboard modem (MCI), N/A
+ device pci 6.0 on end # IDE
+ device pci 7.0 on end # SATA 1
+ device pci 8.0 on end # SATA 0
+ device pci 9.0 on end # PCI
+ device pci a.0 on end # NIC
+ device pci b.0 on end # PCI E 3
+ device pci c.0 on end # PCI E 2
+ device pci d.0 on end # PCI E 1
+ device pci e.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ # register "mac_eeprom_smbus" = "3"
+ # register "mac_eeprom_addr" = "0x51"
+ end
+ end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
diff --git a/src/mainboard/asus/a8v-e_se/devicetree.cb b/src/mainboard/asus/a8v-e_se/devicetree.cb
new file mode 100644
index 0000000..6568e38
--- /dev/null
+++ b/src/mainboard/asus/a8v-e_se/devicetree.cb
@@ -0,0 +1,96 @@
+chip northbridge/amd/amdk8/root_complex # Root complex
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/amd/socket_939 # CPU
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ chip northbridge/amd/amdk8 # mc0
+ device pci 18.0 on # Northbridge
+ # Devices on link 0, link 0 == LDT 0
+ chip southbridge/via/vt8237r # Southbridge
+ register "ide0_enable" = "1" # Enable IDE channel 0
+ register "ide1_enable" = "1" # Enable IDE channel 1
+ register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
+ register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
+ register "fn_ctrl_lo" = "0" # Enable SB functions
+ register "fn_ctrl_hi" = "0xad" # Enable SB functions
+ device pci 0.0 on end # HT
+ device pci f.1 on end # IDE
+ device pci 11.0 on # LPC
+ chip drivers/generic/generic # DIMM 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic # DIMM 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-1
+ device i2c 53 on end
+ end
+ chip superio/winbond/w83627ehg # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2 (N/A on this board)
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 off # PS/2 keyboard (off)
+ end
+ device pnp 2e.106 off # Serial flash
+ io 0x60 = 0x100
+ end
+ device pnp 2e.007 off # GPIO 1
+ end
+ device pnp 2e.107 on # Game port
+ io 0x60 = 0x201
+ end
+ device pnp 2e.207 on # MIDI
+ io 0x62 = 0x330
+ irq 0x70 = 0xa
+ end
+ device pnp 2e.307 off # GPIO 6
+ end
+ device pnp 2e.8 off # WDTO_PLED
+ end
+ device pnp 2e.009 on # GPIO 2 on LDN 9 is in sio_setup
+ end
+ device pnp 2e.109 off # GPIO 3
+ end
+ device pnp 2e.209 off # GPIO 4
+ end
+ device pnp 2e.309 on # GPIO5
+ end
+ device pnp 2e.a off # ACPI
+ end
+ device pnp 2e.b on # Hardware monitor
+ io 0x60 = 0x290
+ irq 0x70 = 0
+ end
+ end
+ end
+ device pci 12.0 off end # VIA LAN (off, other chip used)
+ end
+ chip southbridge/via/k8t890 # "Southbridge" K8T890
+ end
+ end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
diff --git a/src/mainboard/asus/m2v-mx_se/devicetree.cb b/src/mainboard/asus/m2v-mx_se/devicetree.cb
new file mode 100644
index 0000000..2248fc6
--- /dev/null
+++ b/src/mainboard/asus/m2v-mx_se/devicetree.cb
@@ -0,0 +1,76 @@
+chip northbridge/amd/amdk8/root_complex # Root complex
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/amd/socket_AM2 # CPU
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ chip northbridge/amd/amdk8 # mc0
+ device pci 18.0 on # Northbridge
+ # Devices on link 0, link 0 == LDT 0
+ chip southbridge/via/vt8237r # Southbridge
+ register "ide0_enable" = "1" # Enable IDE channel 0
+ register "ide1_enable" = "1" # Enable IDE channel 1
+ register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
+ register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
+ register "fn_ctrl_lo" = "0xc0" # Enable SB functions
+ register "fn_ctrl_hi" = "0x1d" # Enable SB functions
+ device pci 0.0 on end # HT
+ device pci f.1 on end # IDE
+ device pci 11.0 on # LPC
+ chip drivers/generic/generic # DIMM 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic # DIMM 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-1
+ device i2c 53 on end
+ end
+ chip superio/ite/it8712f # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Environment controller
+ io 0x60 = 0x290
+ io 0x62 = 0x230
+ irq 0x70 = 0x00
+ end
+ device pnp 2e.5 off end # PS/2 keyboard
+ device pnp 2e.6 off end # PS/2 mouse
+ device pnp 2e.7 off end # GPIO config
+ device pnp 2e.8 off end # Midi port
+ device pnp 2e.9 off end # Game port
+ device pnp 2e.a off end # IR
+ end
+ end
+ device pci 12.0 on end # VIA LAN
+ device pci 13.0 on end # br
+ device pci 13.1 on end # br2 need to have it here to discover it
+ end
+ chip southbridge/via/k8t890 # "Southbridge" K8M890
+ end
+ end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
diff --git a/src/mainboard/asus/mew-am/devicetree.cb b/src/mainboard/asus/mew-am/devicetree.cb
new file mode 100644
index 0000000..2ca0e68
--- /dev/null
+++ b/src/mainboard/asus/mew-am/devicetree.cb
@@ -0,0 +1,60 @@
+chip northbridge/intel/i82810 # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_PGA370 # CPU
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
+ device pci 1.0 on end # Chipset Graphics Controller (CGC)
+ chip southbridge/intel/i82801xx # Southbridge
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # ISA bridge
+ chip superio/smsc/smscsuperio # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 4
+ end
+ device pnp 2e.4 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.7 on # PS/2 keyboard / mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 2e.9 on # Game port
+ io 0x60 = 0x201
+ end
+ device pnp 2e.a on # Power-management events (PME)
+ io 0x60 = 0x600
+ end
+ device pnp 2e.b on # MIDI port (MPU-401)
+ io 0x60 = 0x330
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.2 on end # USB
+ device pci 1f.3 on end # SMbus
+ device pci 1f.5 off end # AC'97 audio (N/A, uses CS4280 chip)
+ device pci 1f.6 off end # AC'97 modem (N/A)
+ end
+ end
+end
diff --git a/src/mainboard/asus/mew-vm/devicetree.cb b/src/mainboard/asus/mew-vm/devicetree.cb
new file mode 100644
index 0000000..5ff7186
--- /dev/null
+++ b/src/mainboard/asus/mew-vm/devicetree.cb
@@ -0,0 +1,58 @@
+chip northbridge/intel/i82810
+ device pci_domain 0 on
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on # Onboard Video
+ #chip drivers/pci/onboard
+ # device pci 1.0 on end
+ # register "rom_address" = "0xfff80000"
+ #end
+ end
+ chip southbridge/intel/i82801xx # Southbridge
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
+ device pci 1e.0 on # PCI Bridge
+ #chip drivers/pci/onboard
+ # device pci 1.0 on end
+ # register "rom_address" = "0xfff80000"
+ #end
+ end
+ device pci 1f.0 on # ISA/LPC? Bridge
+ chip superio/smsc/lpc47b272
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.7 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # Keyboard interrupt
+ irq 0x72 = 12 # Mouse interrupt
+ end
+ device pnp 2e.a off end # ACPI
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.2 on end # USB
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # AC'97, no header on MEW-VM
+ device pci 1f.6 off end # AC'97 Modem (MC'97)
+ end
+ end
+ chip cpu/intel/socket_PGA370
+ end
+end
+
diff --git a/src/mainboard/asus/p2b-d/devicetree.cb b/src/mainboard/asus/p2b-d/devicetree.cb
new file mode 100644
index 0000000..befd946
--- /dev/null
+++ b/src/mainboard/asus/p2b-d/devicetree.cb
@@ -0,0 +1,62 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 1 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 4.0 on # ISA bridge
+ chip superio/winbond/w83977tf # Super I/O
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.3 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.5 on # PS/2 keyboard / mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.7 on # GPIO 1
+ end
+ device pnp 3f0.8 on # GPIO 2
+ end
+ device pnp 3f0.9 on # GPIO 3
+ end
+ device pnp 3f0.a on # ACPI
+ end
+ end
+ end
+ device pci 4.1 on end # IDE
+ device pci 4.2 on end # USB
+ device pci 4.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "1"
+ register "ide0_drive1_udma33_enable" = "1"
+ register "ide1_drive0_udma33_enable" = "1"
+ register "ide1_drive1_udma33_enable" = "1"
+ end
+ end
+end
diff --git a/src/mainboard/asus/p2b-ds/devicetree.cb b/src/mainboard/asus/p2b-ds/devicetree.cb
new file mode 100644
index 0000000..d40c96d
--- /dev/null
+++ b/src/mainboard/asus/p2b-ds/devicetree.cb
@@ -0,0 +1,63 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 1 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 4.0 on # ISA bridge
+ chip superio/winbond/w83977tf # Super I/O
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.3 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.5 on # PS/2 keyboard / mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.7 on # GPIO 1
+ end
+ device pnp 3f0.8 on # GPIO 2
+ end
+ device pnp 3f0.9 on # GPIO 3
+ end
+ device pnp 3f0.a on # ACPI
+ end
+ end
+ end
+ device pci 4.1 on end # IDE
+ device pci 4.2 on end # USB
+ device pci 4.3 on end # ACPI
+ device pci 6.0 on end # Onboard SCSI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "1"
+ register "ide0_drive1_udma33_enable" = "1"
+ register "ide1_drive0_udma33_enable" = "1"
+ register "ide1_drive1_udma33_enable" = "1"
+ end
+ end
+end
diff --git a/src/mainboard/asus/p2b-f/devicetree.cb b/src/mainboard/asus/p2b-f/devicetree.cb
new file mode 100644
index 0000000..183e9a2
--- /dev/null
+++ b/src/mainboard/asus/p2b-f/devicetree.cb
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 4.0 on # ISA bridge
+ chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.3 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.6 on # Consumer IR
+ end
+ device pnp 3f0.7 on # GPIO 1
+ end
+ device pnp 3f0.8 on # GPIO 2
+ end
+ device pnp 3f0.a on # ACPI
+ end
+ end
+ end
+ device pci 4.1 on end # IDE
+ device pci 4.2 on end # USB
+ device pci 4.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "0"
+ register "ide0_drive1_udma33_enable" = "0"
+ register "ide1_drive0_udma33_enable" = "0"
+ register "ide1_drive1_udma33_enable" = "0"
+ end
+ end
+end
diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb
new file mode 100644
index 0000000..e682fc1
--- /dev/null
+++ b/src/mainboard/asus/p2b/devicetree.cb
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 4.0 on # ISA bridge
+ chip superio/winbond/w83977tf # Super I/O
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.3 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.5 on # PS/2 keyboard / mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.7 on # GPIO 1
+ end
+ device pnp 3f0.8 on # GPIO 2
+ end
+ device pnp 3f0.9 on # GPIO 3
+ end
+ device pnp 3f0.a on # ACPI
+ end
+ end
+ end
+ device pci 4.1 on end # IDE
+ device pci 4.2 on end # USB
+ device pci 4.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "0"
+ register "ide0_drive1_udma33_enable" = "0"
+ register "ide1_drive0_udma33_enable" = "0"
+ register "ide1_drive1_udma33_enable" = "0"
+ end
+ end
+end
diff --git a/src/mainboard/asus/p3b-f/devicetree.cb b/src/mainboard/asus/p3b-f/devicetree.cb
new file mode 100644
index 0000000..183e9a2
--- /dev/null
+++ b/src/mainboard/asus/p3b-f/devicetree.cb
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 4.0 on # ISA bridge
+ chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.3 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.6 on # Consumer IR
+ end
+ device pnp 3f0.7 on # GPIO 1
+ end
+ device pnp 3f0.8 on # GPIO 2
+ end
+ device pnp 3f0.a on # ACPI
+ end
+ end
+ end
+ device pci 4.1 on end # IDE
+ device pci 4.2 on end # USB
+ device pci 4.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "0"
+ register "ide0_drive1_udma33_enable" = "0"
+ register "ide1_drive0_udma33_enable" = "0"
+ register "ide1_drive1_udma33_enable" = "0"
+ end
+ end
+end
diff --git a/src/mainboard/axus/Kconfig b/src/mainboard/axus/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/axus/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/axus/tc320/devicetree.cb b/src/mainboard/axus/tc320/devicetree.cb
new file mode 100644
index 0000000..cf670c7
--- /dev/null
+++ b/src/mainboard/axus/tc320/devicetree.cb
@@ -0,0 +1,55 @@
+chip northbridge/amd/gx1 # Northbridge
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ chip southbridge/amd/cs5530 # Southbridge
+ device pci 12.0 on # ISA bridge
+ chip superio/nsc/pc97317 # Super I/O
+ device pnp 2e.0 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.1 on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.2 on # RTC, advanced power control (APC)
+ io 0x60 = 0x70
+ irq 0x70 = 8
+ end
+ device pnp 2e.3 off # Floppy (N/A on this board)
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.4 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.5 off # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.6 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0xe0
+ end
+ device pnp 2e.8 on # Power management
+ io 0x60 = 0xe800
+ end
+ end
+ end
+ device pci 12.1 off end # SMI
+ device pci 12.2 off end # IDE
+ device pci 12.3 on end # Audio
+ device pci 12.4 on end # VGA (onboard)
+ device pci 13.0 on end # USB
+ # register "ide0_enable" = "1"
+ # register "ide1_enable" = "1"
+ end
+ end
+ chip cpu/amd/model_gx1 # CPU
+ end
+end
diff --git a/src/mainboard/azza/Kconfig b/src/mainboard/azza/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/azza/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/azza/pt-6ibd/devicetree.cb b/src/mainboard/azza/pt-6ibd/devicetree.cb
new file mode 100644
index 0000000..06bbaed
--- /dev/null
+++ b/src/mainboard/azza/pt-6ibd/devicetree.cb
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 7.0 on # ISA bridge
+ chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.3 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.5 on # PS/2 keyboard / mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.6 on # Consumer IR
+ end
+ device pnp 3f0.7 on # GPIO 1
+ end
+ device pnp 3f0.8 on # GPIO 2
+ end
+ device pnp 3f0.a on # ACPI
+ end
+ end
+ end
+ device pci 7.1 on end # IDE
+ device pci 7.2 on end # USB
+ device pci 7.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "0"
+ register "ide0_drive1_udma33_enable" = "0"
+ register "ide1_drive0_udma33_enable" = "0"
+ register "ide1_drive1_udma33_enable" = "0"
+ end
+ end
+end
diff --git a/src/mainboard/bcom/Kconfig b/src/mainboard/bcom/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/bcom/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/bcom/winnet100/devicetree.cb b/src/mainboard/bcom/winnet100/devicetree.cb
new file mode 100644
index 0000000..872b8f3
--- /dev/null
+++ b/src/mainboard/bcom/winnet100/devicetree.cb
@@ -0,0 +1,56 @@
+chip northbridge/amd/gx1 # Northbridge
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ chip southbridge/amd/cs5530 # Southbridge
+ device pci 0f.0 on end # Ethernet (onboard)
+ device pci 12.0 on # ISA bridge
+ chip superio/nsc/pc97317 # Super I/O
+ device pnp 2e.0 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.1 on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.2 on # RTC, Advanced power control (APC)
+ io 0x60 = 0x70
+ irq 0x70 = 8
+ end
+ device pnp 2e.3 off # Floppy (N/A on this board)
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.4 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.5 on # COM2 (used for smartcard reader)
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.6 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0xe0
+ end
+ device pnp 2e.8 on # Power management
+ io 0x60 = 0xe8
+ end
+ end
+ end
+ device pci 12.1 off end # SMI
+ device pci 12.2 on end # IDE
+ device pci 12.3 on end # Audio
+ device pci 12.4 on end # VGA (onboard)
+ device pci 13.0 on end # USB
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "0" # Not available/needed on this board
+ end
+ end
+ chip cpu/amd/model_gx1 # CPU
+ end
+end
diff --git a/src/mainboard/bcom/winnetp680/devicetree.cb b/src/mainboard/bcom/winnetp680/devicetree.cb
new file mode 100644
index 0000000..2461464
--- /dev/null
+++ b/src/mainboard/bcom/winnetp680/devicetree.cb
@@ -0,0 +1,64 @@
+chip northbridge/via/cn700 # Northbridge
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # AGP Bridge
+ device pci 0.1 on end # Error Reporting
+ device pci 0.2 on end # Host Bus Control
+ device pci 0.3 on end # Memory Controller
+ device pci 0.4 on end # Power Management
+ device pci 0.7 on end # V-Link Controller
+ device pci 1.0 on end # PCI Bridge
+ chip southbridge/via/vt8237r # Southbridge
+ # Enable both IDE channels.
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ # Both cables are 40pin.
+ register "ide0_80pin_cable" = "0"
+ register "ide1_80pin_cable" = "0"
+ register "fn_ctrl_lo" = "0x80"
+ register "fn_ctrl_hi" = "0x1d"
+ device pci f.0 on end # IDE
+ device pci 10.0 on end # UHCI
+ device pci 10.1 on end # UHCI
+ device pci 10.2 on end # UHCI
+ device pci 10.3 on end # UHCI
+ device pci 10.4 on end # EHCI
+ device pci 11.0 on # Southbridge LPC
+ chip superio/winbond/w83697hf # Super I/O
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.6 off end # Consumer IR
+ device pnp 2e.7 off end # Game port, GPIO 1
+ device pnp 2e.8 off end # MIDI port, GPIO 5
+ device pnp 2e.9 off end # GPIO 2-4
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HWM
+ io 0x60 = 0x290
+ end
+ end
+ end
+ device pci 11.5 on end # AC'97 audio
+ device pci 12.0 on end # Ethernet
+ end
+ end
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/via/model_c7 # VIA C7
+ device apic 0 on end # APIC
+ end
+ end
+end
diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/biostar/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/biostar/m6tba/devicetree.cb b/src/mainboard/biostar/m6tba/devicetree.cb
new file mode 100644
index 0000000..ed6af31
--- /dev/null
+++ b/src/mainboard/biostar/m6tba/devicetree.cb
@@ -0,0 +1,53 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 7.0 on # ISA bridge
+ chip superio/smsc/smscsuperio # Super I/O
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 3f0.4 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.5 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.7 on # PS/2 keyboard / mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.8 on # Aux I/O
+ end
+ end
+ end
+ device pci 7.1 on end # IDE
+ device pci 7.2 on end # USB
+ device pci 7.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "0"
+ register "ide0_drive1_udma33_enable" = "0"
+ register "ide1_drive0_udma33_enable" = "0"
+ register "ide1_drive1_udma33_enable" = "0"
+ end
+ end
+end
diff --git a/src/mainboard/broadcom/Kconfig b/src/mainboard/broadcom/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/broadcom/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb
new file mode 100644
index 0000000..4c35506
--- /dev/null
+++ b/src/mainboard/broadcom/blast/devicetree.cb
@@ -0,0 +1,148 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # northbridge
+ # devices on link 0
+ chip southbridge/broadcom/bcm5780 # HT2000
+ device pci 0.0 on end # PXB 1 0x0130
+ device pci 1.0 on # PXB 2 0x0130
+ device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
+ device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
+ end
+ device pci 2.0 on end # PCI E 1 #0x0132
+ device pci 3.0 on end # PCI E 2
+ device pci 4.0 on end # PCI E 3
+ device pci 5.0 on end # PCI E 4
+ end
+ chip southbridge/broadcom/bcm5785 # HT1000
+ device pci 0.0 on # HT PXB 0x0036
+ device pci d.0 on end # PPBX 0x0104
+ device pci e.0 on end # SATA 0x024a
+ end
+ device pci 1.0 on # Legacy pci main 0x0205
+ chip drivers/i2c/i2cmux2 # pca9554 smbus mux
+ device i2c 71 on end #0 pca9554 0
+ device i2c 71 on end #0 pca9554 1
+ device i2c 71 on end #0 pca9554 2
+ device i2c 71 on end #0 pca9554 3
+ device i2c 71 on end #0 pca9554 4
+ device i2c 71 on end #0 pca9554 5
+ device i2c 71 on #0 pca9554 6
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ end
+ device i2c 71 on #1 pca9554 7
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 53 on end
+ end
+ end
+ end
+
+ end
+ device pci 1.1 on end # IDE 0x0214
+ device pci 1.2 on # LPC 0x0234
+ chip superio/nsc/pc87417
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 off # Com 2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Com 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 off end # SWC
+ device pnp 2e.5 off end # Mouse
+ device pnp 2e.6 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.f off end # XBUS
+ device pnp 2e.10 on #RTC
+ io 0x60 = 0x70
+ io 0x62 = 0x72
+ end
+ end
+ end
+ device pci 1.3 on end # WDTimer 0x0238
+ device pci 1.4 on end # XIOAPIC0 0x0235
+ device pci 1.5 on end # XIOAPIC1
+ device pci 1.6 on end # XIOAPIC2
+ device pci 2.0 on end # USB 0x0223
+ device pci 2.1 on end # USB
+ device pci 2.2 on end # USB
+ #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,),
+ chip drivers/pci/onboard
+ device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
+ # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
+ register "rom_address" = "0xfff80000"
+ end
+ end
+ #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
+# chip drivers/pci/onboard
+# device pci 0.0 on end # fake, will be disabled
+# end
+# chip drivers/pci/onboard
+# device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
+# register "rom_address" = "0xfff80000"
+# end
+
+
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+
+
+ end #pci_domain
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 off end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 off end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# end
+
+end
+
diff --git a/src/mainboard/compaq/Kconfig b/src/mainboard/compaq/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/compaq/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb b/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb
new file mode 100644
index 0000000..be23f2f
--- /dev/null
+++ b/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb
@@ -0,0 +1,63 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ device pci a.0 on end # NIC (onboard)
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 14.0 on # ISA bridge
+ # chip superio/nsc/pc97307 # Super I/O
+ chip superio/nsc/pc97317 # Super I/O (FIXME: Should be PC97307!)
+ device pnp 15c.0 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 15c.1 on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ device pnp 15c.2 on # RTC, APC
+ io 0x60 = 0x70
+ irq 0x70 = 8
+ end
+ device pnp 15c.3 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 15c.4 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 15c.5 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 15c.6 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 15c.7 on # GPIO 1
+ end
+ device pnp 15c.8 on # Power management
+ end
+ end
+ end
+ device pci 14.1 on end # IDE
+ device pci 14.2 on end # USB
+ device pci 14.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "0"
+ register "ide0_drive1_udma33_enable" = "0"
+ register "ide1_drive0_udma33_enable" = "0"
+ register "ide1_drive1_udma33_enable" = "0"
+ end
+ end
+end
diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/dell/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb
new file mode 100644
index 0000000..4e93a3a
--- /dev/null
+++ b/src/mainboard/dell/s1850/devicetree.cb
@@ -0,0 +1,71 @@
+chip northbridge/intel/e7520 # mch
+ device pci_domain 0 on
+ chip southbridge/intel/i82801er # i82801er
+ # USB ports
+ device pci 1d.0 on end
+ device pci 1d.1 on end
+ device pci 1d.2 on end
+ device pci 1d.3 on end
+ device pci 1d.7 on end
+
+ # -> Bridge
+ device pci 1e.0 on end
+
+ # -> ISA
+ device pci 1f.0 on
+ chip superio/nsc/pc8374
+ device pnp 2e.0 off end
+ device pnp 2e.1 off end
+ device pnp 2e.2 off end
+ device pnp 2e.3 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 off end
+ device pnp 2e.5 off end
+ device pnp 2e.6 off end
+ device pnp 2e.7 off end
+ device pnp 2e.8 off end
+ end
+ end
+ # -> IDE
+ device pci 1f.1 on end
+ # -> SATA
+ device pci 1f.2 on end
+ device pci 1f.3 on end
+
+ register "pirq_a_d" = "0x8a07030b"
+ register "pirq_e_h" = "0x85808080"
+ end
+ device pci 00.0 on end
+ device pci 00.1 on end
+ device pci 01.0 on end
+ device pci 02.0 on
+ chip southbridge/intel/pxhd # pxhd1
+ # Bus bridges and ioapics usually bus 1
+ device pci 0.0 on
+ # On board gig e1000
+ chip drivers/generic/generic
+ device pci 03.0 on end
+ device pci 03.1 on end
+ end
+ end
+ device pci 0.1 on end
+ device pci 0.2 on end
+ device pci 0.3 on end
+ end
+ end
+ device pci 04.0 on end
+ device pci 06.0 on end
+ end
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA604 # cpu 0
+ device apic 0 on end
+ end
+ chip cpu/intel/socket_mPGA604 # cpu 1
+ device apic 6 on end
+ end
+ end
+ register "intrline" = "0x00070100"
+end
+
diff --git a/src/mainboard/digitallogic/Kconfig b/src/mainboard/digitallogic/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/digitallogic/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/digitallogic/adl855pc/devicetree.cb b/src/mainboard/digitallogic/adl855pc/devicetree.cb
new file mode 100644
index 0000000..f0106b0
--- /dev/null
+++ b/src/mainboard/digitallogic/adl855pc/devicetree.cb
@@ -0,0 +1,61 @@
+chip northbridge/intel/i855pm
+ device pci_domain 0 on
+ device pci 0.0 on end
+ device pci 1.0 on end
+ chip southbridge/intel/i82801dbm
+# pci 11.0 on end
+# pci 11.1 on end
+# pci 11.2 on end
+# pci 11.3 on end
+# pci 11.4 on end
+# pci 11.5 on end
+# pci 11.6 on end
+# pci 12.0 on end
+ register "enable_usb" = "0"
+ register "enable_native_ide" = "0"
+ register "enable_usb" = "0"
+ register "enable_native_ide" = "0"
+ chip superio/winbond/w83627hf # link 1
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ register "com1" = "{1}"
+ # register "com1" = "{1, 0, 0x3f8, 4}"
+ # register "lpt" = "{1}"
+ end
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA479M
+ device apic 0 on end
+ end
+ end
+end
diff --git a/src/mainboard/digitallogic/msm586seg/devicetree.cb b/src/mainboard/digitallogic/msm586seg/devicetree.cb
new file mode 100644
index 0000000..30606b5
--- /dev/null
+++ b/src/mainboard/digitallogic/msm586seg/devicetree.cb
@@ -0,0 +1,16 @@
+chip cpu/amd/sc520
+ device pci_domain 0 on
+ device pci 0.0 on end
+
+ chip drivers/pci/onboard
+ device pci 12.0 on end # enet
+ end
+ chip drivers/pci/onboard
+ device pci 14.0 on end # 69000
+ register "rom_address" = "0x2000000"
+ end
+# register "com1" = "{1}"
+# register "com1" = "{1, 0, 0x3f8, 4}"
+ end
+
+end
diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb
new file mode 100644
index 0000000..9636dee
--- /dev/null
+++ b/src/mainboard/digitallogic/msm800sev/devicetree.cb
@@ -0,0 +1,86 @@
+chip northbridge/amd/lx
+ device pci_domain 0 on
+ device pci 1.0 on end
+ device pci 1.1 on end
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+ # How to get these? Boot linux and do this:
+ # rdmsr 0x51400025
+ register "lpc_serirq_enable" = "0x0000105a"
+ # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
+ register "lpc_serirq_polarity" = "0x0000EFA5"
+ # mode is high 10 bits (determined from code)
+ register "lpc_serirq_mode" = "1"
+ # Don't yet know how to find this.
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" #0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "0"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci f.0 on # ISA Bridge
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci f.1 on end # Flash controller
+ device pci f.2 on end # IDE controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+
+ # APIC cluster is late CPU init.
+ device apic_cluster 0 on
+ chip cpu/amd/model_lx
+ device apic 0 on end
+ end
+ end
+
+end
+
diff --git a/src/mainboard/eaglelion/5bcm/devicetree.cb b/src/mainboard/eaglelion/5bcm/devicetree.cb
new file mode 100644
index 0000000..2e0c816
--- /dev/null
+++ b/src/mainboard/eaglelion/5bcm/devicetree.cb
@@ -0,0 +1,54 @@
+chip northbridge/amd/gx1
+ device pci_domain 0 on
+ device pci 0.0 on end
+ chip southbridge/amd/cs5530
+ device pci 12.0 on
+ chip superio/nsc/pc97317
+ device pnp 2e.0 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.1 on # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.2 on # RTC
+ io 0x60 = 0x70
+ irq 0x70 = 8
+ end
+ device pnp 2e.3 off # FDC
+ end
+ device pnp 2e.4 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.5 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.6 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0xe0
+ end
+ device pnp 2e.8 on # Power Management
+ io 0x60 = 0xe800
+ end
+ register "com1" = "{115200}"
+ register "com2" = "{38400}"
+ end
+ device pci 12.1 off end # SMI
+ device pci 12.2 on end # IDE
+ device pci 12.3 off end # Audio
+ device pci 12.4 off end # VGA
+ end
+ end
+ end
+
+ chip cpu/amd/model_gx1
+ end
+
+end
+
diff --git a/src/mainboard/eaglelion/Kconfig b/src/mainboard/eaglelion/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/eaglelion/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/embeddedplanet/Kconfig b/src/mainboard/embeddedplanet/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/embeddedplanet/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/embeddedplanet/ep405pc/devicetree.cb b/src/mainboard/embeddedplanet/ep405pc/devicetree.cb
new file mode 100644
index 0000000..b6f5329
--- /dev/null
+++ b/src/mainboard/embeddedplanet/ep405pc/devicetree.cb
@@ -0,0 +1,17 @@
+chip cpu/ppc/ppc4xx
+ device pci_domain 0 on
+ device pci 0.0 on end
+ chip southbridge/winbond/w83c553
+ device pci 9.0 on end # ISA bridge
+ device pci 9.1 on end # IDE contoller
+ end
+ device pci e.0 on end
+ end
+end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
+makedefine CFLAGS += -msoft-float
diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig
new file mode 100644
index 0000000..023adff
--- /dev/null
+++ b/src/mainboard/emulation/Kconfig
@@ -0,0 +1,25 @@
+choice
+ prompt "Mainboard model"
+ depends on VENDOR_EMULATION
+
+config BOARD_EMULATION_QEMU_X86
+ bool "QEMU x86"
+ select ARCH_X86
+ select CPU_I586
+ select SOUTHBRIDGE_INTEL_I82371EB
+ select CPU_EMULATION_QEMU_X86
+ select CONSOLE_SERIAL8250
+ help
+ x86 QEMU variant.
+
+endchoice
+
+config MAINBOARD_DIR
+ string
+ default emulation/qemu-x86
+ depends on BOARD_EMULATION_QEMU_X86
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "QEMU-86"
+ depends on BOARD_EMULATION_QEMU_X86
diff --git a/src/mainboard/emulation/qemu-x86/Makefile.inc b/src/mainboard/emulation/qemu-x86/Makefile.inc
new file mode 100644
index 0000000..1985b2e
--- /dev/null
+++ b/src/mainboard/emulation/qemu-x86/Makefile.inc
@@ -0,0 +1,21 @@
+initobj-y += crt0.o
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += auto.inc
+
+obj-y += mainboard.o
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+ $(obj)/romcc -mcpu=i386 -O $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+
+endif
diff --git a/src/mainboard/emulation/qemu-x86/devicetree.cb b/src/mainboard/emulation/qemu-x86/devicetree.cb
new file mode 100644
index 0000000..745ff18
--- /dev/null
+++ b/src/mainboard/emulation/qemu-x86/devicetree.cb
@@ -0,0 +1,15 @@
+chip cpu/emulation/qemu-x86
+ device pci_domain 0 on
+ device pci 0.0 on end
+
+ chip southbridge/intel/i82371eb # southbridge
+ device pci 01.0 on end
+ device pci 01.1 on end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+
+# register "com1" = "{1}"
+# register "com1" = "{1, 0, 0x3f8, 4}"
+ end
+end
diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/gigabyte/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/gigabyte/ga-6bxc/devicetree.cb b/src/mainboard/gigabyte/ga-6bxc/devicetree.cb
new file mode 100644
index 0000000..d75ae19
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-6bxc/devicetree.cb
@@ -0,0 +1,57 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 7.0 on # ISA bridge
+ chip superio/ite/it8671f # Super I/O
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.2 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 3f0.4 on # APC
+ end
+ device pnp 3f0.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 3f0.6 on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ device pnp 3f0.7 on # GPIO
+ end
+ end
+ end
+ device pci 7.1 on end # IDE
+ device pci 7.2 on end # USB
+ device pci 7.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "0"
+ register "ide0_drive1_udma33_enable" = "0"
+ register "ide1_drive0_udma33_enable" = "0"
+ register "ide1_drive1_udma33_enable" = "0"
+ end
+ end
+end
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
new file mode 100644
index 0000000..b7cc72f
--- /dev/null
+++ b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
@@ -0,0 +1,106 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_AM2
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8 #mc0
+ device pci 18.0 on
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/sis/sis966
+ device pci 0.0 on end # Northbridge
+ device pci 1.0 on # AGP bridge
+ chip drivers/pci/onboard # Integrated VGA
+ device pci 0.0 on end
+ register "rom_address" = "0xfff80000"
+ end
+ end
+ device pci 2.0 on # LPC
+ chip superio/ite/it8716f
+ device pnp 2e.0 off # Floppy (N/A)
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2 (N/A)
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 off # Parallel port (N/A)
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # EC
+ io 0x60 = 0x290
+ io 0x62 = 0x230
+ irq 0x70 = 9
+ end
+ device pnp 2e.5 off # PS/2 keyboard (N/A)
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 off # Mouse (N/A)
+ irq 0x70 = 12
+ end
+ device pnp 2e.8 off # MIDI (N/A)
+ io 0x60 = 0x300
+ irq 0x70 = 10
+ end
+ device pnp 2e.9 off # GAME (N/A)
+ io 0x60 = 0x220
+ end
+ device pnp 2e.a off end # CIR (N/A)
+ end
+ end
+
+ device pci 2.5 off end # IDE (SiS5513)
+ device pci 2.6 off end # Modem (SiS7013)
+ device pci 2.7 off end # Audio (SiS7012)
+ device pci 3.0 on end # USB (SiS7001,USB1.1)
+ device pci 3.1 on end # USB (SiS7001,USB1.1)
+ device pci 3.3 on end # USB (SiS7002,USB2.0)
+ device pci 4.0 on end # NIC (SiS191)
+ device pci 5.0 on end # SATA (SiS1183,Native Mode)
+ device pci 6.0 on end # PCI-e x1
+ device pci 7.0 on end # PCI-e x1
+ device pci a.0 off end
+ device pci b.0 off end
+ device pci c.0 off end
+ device pci d.0 off end
+ device pci e.0 off end
+ device pci f.0 off end # HD Audio (SiS7502)
+
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ end
+ end # device pci 18.0
+ device pci 18.0 on end # Link 1
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end # mc0
+
+ end # PCI domain
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 off end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 off end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# device pnp 0.8 off end # io
+# device pnp 0.9 off end # io
+# end
+end #root_complex
diff --git a/src/mainboard/gigabyte/m57sli/devicetree.cb b/src/mainboard/gigabyte/m57sli/devicetree.cb
new file mode 100644
index 0000000..60692d6
--- /dev/null
+++ b/src/mainboard/gigabyte/m57sli/devicetree.cb
@@ -0,0 +1,202 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_AM2
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8 #mc0
+ device pci 18.0 on
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/mcp55
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/ite/it8716f
+ # Floppy and any LDN
+ device pnp 2e.0 off
+ # Watchdog from CLKIN, CLKIN = 24 MHz
+ irq 0x23 = 0x11
+ # Serial Flash (SPI only)
+ #0x24 = 0x1a
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # EC
+ io 0x60 = 0x290
+ io 0x62 = 0x230
+ irq 0x70 = 9
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 on # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO, SPI flash
+ # pin 84 is not GP10
+ irq 0x25 = 0x0
+ # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
+ irq 0x26 = 0x43
+ # pin 13 is GP35
+ irq 0x27 = 0x20
+ # pin 70 is not GP46
+ #irq 0x28 = 0x0
+ # pin 6,3,128,127,126 is GP63,64,65,66,67
+ irq 0x29 = 0x81
+ # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
+ #irq 0x2c = 0x1f
+ # Simple I/O base
+ io 0x62 = 0x800
+ # Serial Flash I/O (SPI only)
+ io 0x64 = 0x820
+ # watch dog force timeout (parallel flash only)
+ #irq 0x71 = 0x1
+ # No WDT interrupt
+ irq 0x72 = 0x0
+ # GPIO pin set 1 disable internal pullup
+ irq 0xb8 = 0x0
+ # GPIO pin set 5 enable internal pullup
+ irq 0xbc = 0x01
+ # SIO pin set 1 alternate function
+ #irq 0xc0 = 0x0
+ # SIO pin set 2 mixed function
+ irq 0xc1 = 0x43
+ # SIO pin set 3 mixed function
+ irq 0xc2 = 0x20
+ # SIO pin set 4 alternate function
+ #irq 0xc3 = 0x0
+ # SIO pin set 1 input mode
+ #irq 0xc8 = 0x0
+ # SIO pin set 2 input mode
+ irq 0xc9 = 0x0
+ # SIO pin set 4 input mode
+ #irq 0xcb = 0x0
+ # Generate SMI# on EC IRQ
+ #irq 0xf0 = 0x10
+ # SMI# level trigger
+ #irq 0xf1 = 0x40
+ # HWMON alert beep pin location
+ irq 0xf6 = 0x28
+ end
+ device pnp 2e.8 off # MIDI
+ io 0x60 = 0x300
+ irq 0x70 = 10
+ end
+ device pnp 2e.9 off # GAME
+ io 0x60 = 0x220
+ end
+ device pnp 2e.a off end # CIR
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ end # SM
+#WTF?!? We already have device pci 1.1 in the section above
+ device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+# chip drivers/generic/generic #PCIXA Slot1
+# device i2c 50 on end
+# end
+# chip drivers/generic/generic #PCIXB Slot1
+# device i2c 51 on end
+# end
+# chip drivers/generic/generic #PCIXB Slot2
+# device i2c 52 on end
+# end
+# chip drivers/generic/generic #PCI Slot1
+# device i2c 53 on end
+# end
+# chip drivers/generic/generic #Master MCP55 PCI-E
+# device i2c 54 on end
+# end
+# chip drivers/generic/generic #Slave MCP55 PCI-E
+# device i2c 55 on end
+# end
+ chip drivers/generic/generic #MAC EEPROM
+ device i2c 51 on end
+ end
+
+ end # SM
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # IDE
+ device pci 5.0 on end # SATA 0
+ device pci 5.1 on end # SATA 1
+ device pci 5.2 on end # SATA 2
+ device pci 6.0 on end # PCI
+ device pci 6.1 on end # AZA
+ device pci 8.0 on end # NIC
+ device pci 9.0 off end # NIC
+ device pci a.0 on end # PCI E 5
+ device pci b.0 on end # PCI E 4
+ device pci c.0 on end # PCI E 3
+ device pci d.0 on end # PCI E 2
+ device pci e.0 on end # PCI E 1
+ device pci f.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end # device pci 18.0
+ device pci 18.0 on end # Link 1
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end # mc0
+
+ end # PCI domain
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 on end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 on end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# device pnp 0.8 off end # io
+# device pnp 0.9 off end # io
+# end
+end #root_complex
diff --git a/src/mainboard/hp/Kconfig b/src/mainboard/hp/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/hp/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/hp/dl145_g3/devicetree.cb b/src/mainboard/hp/dl145_g3/devicetree.cb
new file mode 100644
index 0000000..0d038d3
--- /dev/null
+++ b/src/mainboard/hp/dl145_g3/devicetree.cb
@@ -0,0 +1,96 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_F
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8 # northbridge
+ device pci 18.0 on # devices on link 0
+ chip southbridge/broadcom/bcm21000 # HT2100
+ device pci 0.0 on
+ end # bridge to slot PCI-E 4x ??
+ device pci 1.0 on
+ end
+ device pci 2.0 on
+ end # unused
+ device pci 3.0 on # bridge to slot PCI-E 16x ??
+ end
+ device pci 4.0 on
+ end # unused
+ device pci 5.0 on
+ device pci 4.0 on end # BCM5715 NIC
+ device pci 4.1 on end # BCM5715 NIC
+ end
+ end
+ chip southbridge/broadcom/bcm5785 # HT1000
+ device pci 0.0 on # HT PXB 0x0036
+ device pci d.0 on end # PCI/PCI-X bridge 0x0104
+ device pci e.0 on end # SATA 0x024a
+ end
+ device pci 1.0 on end # Legacy pci main 0x0205
+ device pci 1.1 on end # IDE 0x0214
+ device pci 1.2 on # LPC 0x0234
+ chip superio/nsc/pc87417
+ device pnp 4e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 4e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 4e.2 off # Com 2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 4e.3 off # Com 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.4 off end # SWC
+ device pnp 4e.5 off end # Mouse
+ device pnp 4e.6 off # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 4e.7 off end # GPIO
+ device pnp 4e.f off end # XBUS
+ device pnp 4e.10 on #RTC
+ io 0x60 = 0x70
+ io 0x62 = 0x72
+ end
+ end # end superio
+ end # end pci 1.2
+ device pci 1.3 off end # WDTimer 0x0238
+ device pci 1.4 on end # XIOAPIC0 0x0235
+ device pci 1.5 on end # XIOAPIC1
+ device pci 1.6 on end # XIOAPIC2
+ device pci 2.0 on end # USB 0x0223
+ device pci 2.1 on end # USB
+ device pci 2.2 on end # USB
+ device pci 3.0 on end # VGA
+
+ #bx_a013+ start
+ #chip drivers/pci/onboard #SATA2
+ # device pci 5.0 on end
+ # device pci 5.1 on end
+ # device pci 5.2 on end
+ # device pci 5.3 on end
+ #end
+ #bx_a013+ end
+ end
+ end
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end # amdk8
+
+ end #pci_domain
+end
+
+
diff --git a/src/mainboard/ibm/Kconfig b/src/mainboard/ibm/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/ibm/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/ibm/e325/devicetree.cb b/src/mainboard/ibm/e325/devicetree.cb
new file mode 100644
index 0000000..4db7c00
--- /dev/null
+++ b/src/mainboard/ibm/e325/devicetree.cb
@@ -0,0 +1,81 @@
+chip northbridge/amd/amdk8/root_complex
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on end # LDT 0
+ device pci 18.0 on # LDT 1
+ chip southbridge/amd/amd8131
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 on end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/nsc/pc87366
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 off # Com 2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Com 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 off end # SWC
+ device pnp 2e.5 off end # Mouse
+ device pnp 2e.6 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.8 off end # ACB
+ device pnp 2e.9 off end # FSCM
+ device pnp 2e.a off end # WDT
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
+ end
+ end # device pci 18.0
+ device pci 18.0 on end # LDT2
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/ibm/e326/devicetree.cb b/src/mainboard/ibm/e326/devicetree.cb
new file mode 100644
index 0000000..11c57e8
--- /dev/null
+++ b/src/mainboard/ibm/e326/devicetree.cb
@@ -0,0 +1,77 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on end # LDT 0
+ device pci 18.0 on # LDT 1
+ chip southbridge/amd/amd8131
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 on end
+ device pci 1.0 off end
+ chip drivers/pci/onboard
+ device pci 5.0 on end # ATI Rage XL
+ register "rom_address" = "0xfff80000"
+ end
+ end
+ device pci 1.0 on
+ chip superio/nsc/pc87366
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 off # Com 2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Com 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 off end # SWC
+ device pnp 2e.5 off end # Mouse
+ device pnp 2e.6 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.8 off end # ACB
+ device pnp 2e.9 off end # FSCM
+ device pnp 2e.a off end # WDT
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+ device pci 18.0 on end # LDT2
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/iei/Kconfig b/src/mainboard/iei/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/iei/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/iei/juki-511p/devicetree.cb b/src/mainboard/iei/juki-511p/devicetree.cb
new file mode 100644
index 0000000..486fbd5
--- /dev/null
+++ b/src/mainboard/iei/juki-511p/devicetree.cb
@@ -0,0 +1,59 @@
+chip northbridge/amd/gx1
+ device pci_domain 0 on
+ device pci 0.0 on end
+ chip southbridge/amd/cs5530
+
+ device pci 12.0 on
+ chip superio/winbond/w83977f
+ device pnp 3f0.0 on # FDC
+ irq 0x70 = 6
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ register "com1" = "{115200}"
+ device pnp 3f0.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ register "com2" = "{115200}"
+ device pnp 3f0.4 on # RTC
+ io 0x60 = 0x070
+ irq 0x70 = 8
+ end
+ device pnp 3f0.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # Int 1 for PS/2 keyboard
+ irq 0x72 = 12 # Int 12 for PS/2 mouse
+ end
+ device pnp 3f0.6 off # IR
+ end
+ device pnp 3f0.7 off # GPIO1
+ end
+ device pnp 3f0.8 off # GPIO
+ end
+ end
+ device pci 12.1 on end # SMI
+ device pci 12.2 on end # IDE
+ device pci 12.3 on end # Audio
+ device pci 12.4 on end # VGA onboard
+
+ end
+
+ device pci 0e.0 on end # ETH0
+ device pci 13.0 on end # USB
+
+ end
+ end
+
+ chip cpu/amd/model_gx1
+ end
+
+end
+
diff --git a/src/mainboard/iei/nova4899r/devicetree.cb b/src/mainboard/iei/nova4899r/devicetree.cb
new file mode 100644
index 0000000..f26db42
--- /dev/null
+++ b/src/mainboard/iei/nova4899r/devicetree.cb
@@ -0,0 +1,66 @@
+chip northbridge/amd/gx1
+ device pci_domain 0 on
+ device pci 0.0 on end
+ chip southbridge/amd/cs5530
+ device pci 0a.0 on end # ETH0
+ device pci 0b.0 off end # ETH1
+ device pci 0c.0 on end # ETH2
+ device pci 0f.0 on end # PCI slot
+ device pci 12.0 on
+ chip superio/winbond/w83977tf
+ device pnp 2e.0 on # FDC
+ irq 0x70 = 6
+ end
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ register "com1" = "{115200}"
+ device pnp 2e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ register "com2" = "{115200}"
+ device pnp 2e.4 off # Reserved
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 0x01 # Int 1 for PS/2 keyboard
+ irq 0x72 = 0x0c # Int 12 for PS/2 mouse
+ end
+ device pnp 2e.6 on # IR
+ io 0x60 = 0x2e8
+ irq 0x70 = 3
+ end
+ device pnp 2e.7 on # GAME/MIDI/GPIO1
+ io 0x60 = 0x290
+ end
+ device pnp 2e.8 on # GPIO2
+ io 0x60 = 0x110
+ end
+ device pnp 2e.9 on # GPIO3
+ io 0x60 = 0x120
+ end
+ device pnp 2e.A on # Power Management
+ io 0x60 = 0xe800
+ end
+ end
+ device pci 12.1 on end # SMI
+ device pci 12.2 on end # IDE
+ device pci 12.3 on end # Audio
+ device pci 12.4 on end # VGA onboard
+ end
+ device pci 13.0 on end # USB
+ end
+ end
+
+ chip cpu/amd/model_gx1
+ end
+
+end
+
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb
new file mode 100644
index 0000000..59a4875
--- /dev/null
+++ b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb
@@ -0,0 +1,76 @@
+chip northbridge/amd/lx
+ device pci_domain 0 on
+ device pci 1.0 on end # Northbridge
+ device pci 1.1 on end # Graphics
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
+ register "lpc_serirq_enable" = "0x0000105a"
+ register "lpc_serirq_polarity" = "0x0000EFA5"
+ register "lpc_serirq_mode" = "1"
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "1" # 0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "0"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci 9.0 on end # Slot1
+ device pci a.0 on end # Slot2
+ device pci b.0 on end # Slot3
+ device pci c.0 on end # Slot4
+ device pci e.0 on end # Ethernet 0
+ device pci 10.0 on end # Ethernet 1
+ device pci 11.0 on end # SATA
+ device pci f.0 on # ISA Bridge
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b off end # HW Monitor
+ end
+ end
+ device pci f.2 on end # IDE Controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+ # APIC cluster is late CPU init.
+ device apic_cluster 0 on
+ chip cpu/amd/model_lx
+ device apic 0 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/intel/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/intel/jarrell/devicetree.cb b/src/mainboard/intel/jarrell/devicetree.cb
new file mode 100644
index 0000000..e4cdbde
--- /dev/null
+++ b/src/mainboard/intel/jarrell/devicetree.cb
@@ -0,0 +1,79 @@
+chip northbridge/intel/e7520
+ device pci_domain 0 on
+ device pci 00.0 on end
+ device pci 00.1 on end
+ device pci 01.0 on end
+ device pci 02.0 on
+ chip southbridge/intel/pxhd # pxhd1
+ device pci 00.0 on end
+ device pci 00.1 on end
+ device pci 00.2 on
+ chip drivers/generic/generic
+ device pci 04.0 on end
+ device pci 04.1 on end
+ end
+ end
+ device pci 00.3 on end
+ end
+ end
+ device pci 06.0 on end
+ chip southbridge/intel/i82801er # i82801er
+ device pci 1d.0 on end
+ device pci 1d.1 on end
+ device pci 1d.2 on end
+ device pci 1d.3 off end
+ device pci 1d.7 on end
+ device pci 1e.0 on
+ chip drivers/ati/ragexl
+ device pci 0c.0 on end
+ end
+ end
+ device pci 1f.0 on
+ chip superio/nsc/pc87427
+ device pnp 2e.0 off end
+ device pnp 2e.2 on
+# io 0x60 = 0x2f8
+# irq 0x70 = 3
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on
+# io 0x60 = 0x3f8
+# irq 0x70 = 4
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.4 off end
+ device pnp 2e.5 off end
+ device pnp 2e.6 on
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.7 off end
+ device pnp 2e.9 off end
+ device pnp 2e.a off end
+ device pnp 2e.f on end
+ device pnp 2e.10 off end
+ device pnp 2e.14 off end
+ end
+ end
+ device pci 1f.1 on end
+ device pci 1f.2 off end
+ device pci 1f.3 on end
+ device pci 1f.5 off end
+ device pci 1f.6 off end
+ register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO"
+ register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW"
+ register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA604 # cpu 0
+ device apic 0 on end
+ end
+ chip cpu/intel/socket_mPGA604 # cpu 1
+ device apic 6 on end
+ end
+ end
+end
diff --git a/src/mainboard/intel/mtarvon/devicetree.cb b/src/mainboard/intel/mtarvon/devicetree.cb
new file mode 100644
index 0000000..1a11859
--- /dev/null
+++ b/src/mainboard/intel/mtarvon/devicetree.cb
@@ -0,0 +1,44 @@
+chip northbridge/intel/i3100
+ device pci_domain 0 on
+ device pci 00.0 on end # IMCH
+ device pci 00.1 on end # IMCH error status
+ device pci 01.0 on end # IMCH EDMA engine
+ device pci 02.0 on end # PCIe port A/A0
+ device pci 03.0 on end # PCIe port A1
+ chip southbridge/intel/i3100
+ # PIRQ line -> legacy IRQ mappings
+ register "pirq_a_d" = "0x0b070a05"
+ register "pirq_e_h" = "0x0a808080"
+
+ device pci 1c.0 on end # PCIe port B0
+ device pci 1c.1 on end # PCIe port B1
+ device pci 1c.2 on end # PCIe port B2
+ device pci 1c.3 on end # PCIe port B3
+ device pci 1d.0 on end # USB (UHCI) 1
+ device pci 1d.1 on end # USB (UHCI) 2
+ device pci 1d.7 on end # USB (EHCI)
+ device pci 1e.0 on end # PCI bridge
+ device pci 1e.2 on end # audio
+ device pci 1e.3 on end # modem
+ device pci 1f.0 on # LPC bridge
+ chip superio/intel/i3100
+ device pnp 4e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.5 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ end
+ end
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMBus
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA479M
+ device apic 0 on end
+ end
+ end
+end
diff --git a/src/mainboard/intel/truxton/devicetree.cb b/src/mainboard/intel/truxton/devicetree.cb
new file mode 100644
index 0000000..7604bea
--- /dev/null
+++ b/src/mainboard/intel/truxton/devicetree.cb
@@ -0,0 +1,41 @@
+chip northbridge/intel/i3100
+ device pci_domain 0 on
+ device pci 00.0 on end # IMCH
+ device pci 00.1 on end # IMCH error status
+ device pci 01.0 on end # IMCH EDMA engine
+ device pci 02.0 on end # PCIe port A/A0
+ device pci 03.0 on end # PCIe port A1
+ device pci 04.0 on end # ?
+ device pci 08.0 off end # must be off to boot
+ device pci 0d.0 off end # must be off to boot
+ device pci 0d.1 off end # must be off to boot
+ chip southbridge/intel/i3100
+ # PIRQ line -> legacy IRQ mappings
+ register "pirq_a_d" = "0x0b070a05"
+ register "pirq_e_h" = "0x0a808080"
+
+ device pci 1d.0 on end # USB (UHCI)
+ device pci 1d.7 on end # USB (EHCI)
+ device pci 1f.0 on # LPC bridge
+ chip superio/intel/i3100
+ device pnp 4e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.5 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ end
+ end
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMBus
+ device pci 1f.4 on end # ?
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/intel/ep80579
+ device apic 0 on end
+ end
+ end
+end
diff --git a/src/mainboard/intel/xe7501devkit/devicetree.cb b/src/mainboard/intel/xe7501devkit/devicetree.cb
new file mode 100644
index 0000000..68d2b97
--- /dev/null
+++ b/src/mainboard/intel/xe7501devkit/devicetree.cb
@@ -0,0 +1,75 @@
+chip northbridge/intel/e7501
+ device pci_domain 0 on
+ device pci 0.0 on end # Chipset host controller
+ device pci 0.1 on end # Host RASUM controller
+ device pci 2.0 on # Hub interface B
+ chip southbridge/intel/i82870 # P64H2
+ device pci 1c.0 on end # IOAPIC - bus B
+ device pci 1d.0 on end # Hub to PCI-B bridge
+ device pci 1e.0 on end # IOAPIC - bus A
+ device pci 1f.0 on end # Hub to PCI-A bridge
+ end
+ end
+ device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)
+ device pci 4.0 on # Hub interface D
+ chip southbridge/intel/i82870 # P64H2
+ device pci 1c.0 on end # IOAPIC - bus B
+ device pci 1d.0 on end # Hub to PCI-B bridge
+ device pci 1e.0 on end # IOAPIC - bus A
+ device pci 1f.0 on end # Hub to PCI-A bridge
+ end
+ end
+ device pci 6.0 on end # E7501 Power management registers? (undocumented)
+ chip southbridge/intel/i82801ca
+ device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)
+ device pci 1d.1 off end # USB (not populated)
+ device pci 1d.2 off end # USB (not populated)
+ device pci 1e.0 on # Hub to PCI bridge
+ chip drivers/pci/onboard # VGA ROM
+ device pci 0.0 on end
+ register "rom_address" = "_vgarom_start"
+ end
+ end
+ device pci 1f.0 on # LPC bridge
+ chip superio/smsc/lpc47b272
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.7 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # Keyboard interrupt
+ irq 0x72 = 12 # Mouse interrupt
+ end
+ device pnp 2e.a off end # ACPI
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # AC97 Audio
+ device pci 1f.6 off end # AC97 Modem
+ end # SB
+ end # PCI_DOMAIN
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA604
+ device apic 0 on end
+ end
+ chip cpu/intel/socket_mPGA604
+ device apic 6 on end
+ end
+ end
+end
diff --git a/src/mainboard/iwill/Kconfig b/src/mainboard/iwill/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/iwill/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/iwill/dk8_htx/devicetree.cb b/src/mainboard/iwill/dk8_htx/devicetree.cb
new file mode 100644
index 0000000..0d02cc8
--- /dev/null
+++ b/src/mainboard/iwill/dk8_htx/devicetree.cb
@@ -0,0 +1,133 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.0 on # northbridge
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ #chip drivers/pci/onboard
+ # device pci 6.0 on end
+ # register "rom_address" = "0xfff80000"
+ #end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 on # GPIO2
+ io 0x07 = 0x08ff
+ io 0x30 = 0x01ff
+ io 0x2b = 0xd0ff
+ io 0xf0 = 0xef16
+ end
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ end # acpi
+ device pci 1.5 off end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+
+ end #pci_domain
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 off end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 off end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# end
+
+end
+
+
diff --git a/src/mainboard/iwill/dk8s2/devicetree.cb b/src/mainboard/iwill/dk8s2/devicetree.cb
new file mode 100644
index 0000000..5c389f2
--- /dev/null
+++ b/src/mainboard/iwill/dk8s2/devicetree.cb
@@ -0,0 +1,89 @@
+chip northbridge/amd/amdk8/root_complex
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # LDT 0
+ chip southbridge/amd/amd8131
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 on end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ register "com1" = "{1}"
+ # register "com1" = "{1, 0, 0x3f8, 4}"
+ # register "lpt" = "{1}"
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
+ end
+ end # LDT0
+ device pci 18.0 on end # LDT1
+ device pci 18.0 on end # LDT2
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/iwill/dk8x/devicetree.cb b/src/mainboard/iwill/dk8x/devicetree.cb
new file mode 100644
index 0000000..77c96aa
--- /dev/null
+++ b/src/mainboard/iwill/dk8x/devicetree.cb
@@ -0,0 +1,68 @@
+chip northbridge/amd/amdk8/root_complex
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 on end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627thf
+ device pnp 2e.0 on end
+ device pnp 2e.1 on end
+ device pnp 2e.2 on end
+ device pnp 2e.3 on end
+ device pnp 2e.4 on end
+ device pnp 2e.5 on end
+ device pnp 2e.6 on end
+ device pnp 2e.7 on end
+ device pnp 2e.8 on end
+ device pnp 2e.9 on end
+ device pnp 2e.a on end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
+ end
+ end # LDT0
+ device pci 18.0 on end # LDT1
+ device pci 18.0 on end # LDT2
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/jetway/Kconfig b/src/mainboard/jetway/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/jetway/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/jetway/j7f24/devicetree.cb b/src/mainboard/jetway/j7f24/devicetree.cb
new file mode 100644
index 0000000..4df377b
--- /dev/null
+++ b/src/mainboard/jetway/j7f24/devicetree.cb
@@ -0,0 +1,62 @@
+chip northbridge/via/cn700 # Northbridge
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # AGP Bridge
+ device pci 0.1 on end # Error Reporting
+ device pci 0.2 on end # Host Bus Control
+ device pci 0.3 on end # Memory Controller
+ device pci 0.4 on end # Power Management
+ device pci 0.7 on end # V-Link Controller
+ device pci 1.0 on end # PCI Bridge
+ chip southbridge/via/vt8237r # Southbridge
+ # Enable both IDE channels.
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ # Both cables are 40pin.
+ register "ide0_80pin_cable" = "0"
+ register "ide1_80pin_cable" = "0"
+ register "fn_ctrl_lo" = "0x80"
+ register "fn_ctrl_hi" = "0x1d"
+ device pci a.0 on end # Firewire
+ device pci f.0 on end # SATA
+ device pci f.1 on end # IDE
+ device pci 10.0 on end # OHCI
+ device pci 10.1 on end # OHCI
+ device pci 10.2 on end # OHCI
+ device pci 10.3 on end # OHCI
+ device pci 10.4 on end # EHCI
+ device pci 11.0 on # Southbridge LPC
+ chip superio/fintek/f71805f # Super I/O
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.b on # HWM
+ io 0x60 = 0xec00
+ end
+ end
+ end
+ device pci 11.5 on end # AC'97 audio
+ # device pci 11.6 off end # AC'97 Modem
+ device pci 12.0 on end # Ethernet
+ end
+ end
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/via/model_c7 # VIA C7
+ device apic 0 on end # APIC
+ end
+ end
+end
diff --git a/src/mainboard/kontron/986lcd-m/Makefile.inc b/src/mainboard/kontron/986lcd-m/Makefile.inc
new file mode 100644
index 0000000..6a021bf
--- /dev/null
+++ b/src/mainboard/kontron/986lcd-m/Makefile.inc
@@ -0,0 +1,77 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
+##
+
+driver-y += mainboard.o
+driver-y += rtl8168.o
+
+#obj-y += ../../../southbridge/intel/i82801gx/i82801gx_reset.c
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
+
+smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+MAINBOARD_OPTIONS=\
+ -DCONFIG_AP_IN_SIPI_WAIT=1 \
+ -DCONFIG_USE_PRINTK_IN_CAR=1 \
+ -DCONFIG_HAVE_HIGH_TABLES=1 \
+ -DCONFIG_MMCONF_SUPPORT=1 \
+ -DCONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+ iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+ mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+ perl -e 's/\.rodata/.rom.data/g' -pi $@
+ perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+
diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb
new file mode 100644
index 0000000..2a3615b
--- /dev/null
+++ b/src/mainboard/kontron/986lcd-m/devicetree.cb
@@ -0,0 +1,132 @@
+chip northbridge/intel/i945
+
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mFCPGA478
+ device apic 0 on end
+ end
+ end
+
+ device pci_domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 01.0 off end # i945 PCIe root port
+ chip drivers/pci/onboard
+ device pci 02.0 on end # vga controller
+ # register "rom_address" = "0xfffc0000" # 256 KB image
+ # register "rom_address" = "0xfff80000" # 512 KB image
+ register "rom_address" = "0xfff00000" # 1 MB image
+ end
+ device pci 02.1 on end # display controller
+
+ chip southbridge/intel/i82801gx
+ register "pirqa_routing" = "0x05"
+ register "pirqb_routing" = "0x07"
+ register "pirqc_routing" = "0x05"
+ register "pirqd_routing" = "0x07"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x06"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "gpi13_routing" = "1"
+
+ register "ide_legacy_combined" = "0x1"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x1"
+ register "sata_ahci" = "0x0"
+
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe
+ device pci 1c.1 on end # PCIe
+ device pci 1c.2 on end # PCIe
+ #device pci 1c.3 off end # PCIe port 4
+ #device pci 1c.4 off end # PCIe port 5
+ #device pci 1c.5 off end # PCIe port 6
+ device pci 1d.0 on end # USB UHCI
+ device pci 1d.1 on end # USB UHCI
+ device pci 1d.2 on end # USB UHCI
+ device pci 1d.3 on end # USB UHCI
+ device pci 1d.7 on end # USB2 EHCI
+ device pci 1e.0 on end # PCI bridge
+ #device pci 1e.2 off end # AC'97 Audio
+ #device pci 1e.3 off end # AC'97 Modem
+ device pci 1f.0 on # LPC bridge
+ chip superio/winbond/w83627thg
+ device pnp 2e.0 off # Floppy
+ end
+ device pnp 2e.1 off # Parport
+ end
+ device pnp 2e.2 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
+ end
+ device pnp 2e.5 on # Keyboard+Mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ irq 0xf0 = 0x82 # HW accel A20.
+ end
+ device pnp 2e.7 on # GPIO1, GAME, MIDI
+ io 0x62 = 0x330
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 on # GPIO2
+ # all default
+ end
+ device pnp 2e.9 on # GPIO3/4
+ irq 0x30 = 0x03 # does this work?
+ irq 0xf0 = 0xfb # set inputs/outputs
+ irq 0xf1 = 0x66
+ end
+ device pnp 2e.a off # ACPI
+ end
+ device pnp 2e.b on # HWM
+ io 0x60 = 0xa00
+ irq 0x70 = 0
+ end
+
+ end
+ chip superio/winbond/w83627thg
+ device pnp 4e.0 off # Floppy
+ end
+ device pnp 4e.1 off # Parport
+ end
+ device pnp 4e.2 on # COM3
+ io 0x60 = 0x3e8
+ irq 0x70 = 11
+ end
+ device pnp 4e.3 on # COM4
+ io 0x60 = 0x2e8
+ irq 0x70 = 10
+ end
+ device pnp 4e.5 off # Keyboard
+ end
+ device pnp 4e.7 off # GPIO1, GAME, MIDI
+ end
+ device pnp 4e.8 off # GPIO2
+ end
+ device pnp 4e.9 off # GPIO3/4
+ end
+ device pnp 4e.a off # ACPI
+ end
+ device pnp 4e.b off # HWM
+ end
+ end
+
+ end
+ #device pci 1f.1 off end # IDE
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMBus
+ #device pci 1f.4 off end # Realtek ID Codec
+ end
+ end
+end
diff --git a/src/mainboard/kontron/Kconfig b/src/mainboard/kontron/Kconfig
new file mode 100644
index 0000000..4a6a64f
--- /dev/null
+++ b/src/mainboard/kontron/Kconfig
@@ -0,0 +1,48 @@
+choice
+ prompt "Mainboard model"
+ depends on VENDOR_KONTRON
+
+config BOARD_KONTRON_986LCD_M
+ bool "986LCD-M"
+ select ARCH_X86
+ select CPU_INTEL_CORE
+ select CPU_INTEL_SOCKET_MFCPGA478
+ select NORTHBRIDGE_INTEL_I945
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_WINBOND_W83627THG
+ select PIRQ_TABLE
+ select MMCONF_SUPPORT
+ select USE_PRINTK_IN_CAR
+ help
+ Kontron 986LCD-M Series mainboards
+endchoice
+
+config MAINBOARD_DIR
+ string
+ default kontron/986lcd-m
+ depends on BOARD_KONTRON_986LCD_M
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffdf8000
+ depends on BOARD_KONTRON_986LCD_M
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+ depends on BOARD_KONTRON_986LCD_M
+
+config LB_CKS_RANGE_END
+ int
+ default 122
+ depends on BOARD_KONTRON_986LCD_M
+
+config LB_CKS_LOC
+ int
+ default 123
+ depends on BOARD_KONTRON_986LCD_M
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "986LCD-M"
+ depends on BOARD_KONTRON_986LCD_M
diff --git a/src/mainboard/lippert/Kconfig b/src/mainboard/lippert/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/lippert/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb
new file mode 100644
index 0000000..7f16174
--- /dev/null
+++ b/src/mainboard/lippert/frontrunner/devicetree.cb
@@ -0,0 +1,18 @@
+chip northbridge/amd/gx2
+ device pci_domain 0 on
+ device pci 0.0 on end
+ chip southbridge/amd/cs5535
+ device pci 12.0 on
+ device pci 12.1 off end # SMI
+ device pci 12.2 on end # IDE
+ device pci 12.3 off end # Audio
+ device pci 12.4 off end # VGA
+ end
+ end
+ end
+
+ chip cpu/amd/model_gx2
+ end
+
+end
+
diff --git a/src/mainboard/lippert/roadrunner-lx/devicetree.cb b/src/mainboard/lippert/roadrunner-lx/devicetree.cb
new file mode 100644
index 0000000..7201972
--- /dev/null
+++ b/src/mainboard/lippert/roadrunner-lx/devicetree.cb
@@ -0,0 +1,89 @@
+chip northbridge/amd/lx
+ device pci_domain 0 on
+ device pci 1.0 on end # Northbridge
+ device pci 1.1 on end # Graphics
+ device pci 1.2 on end # AES
+ chip southbridge/amd/cs5536 # Southbridge
+ # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power...
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
+ # UARTs, etc IRQs. OK
+ register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010
+ register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above
+ register "lpc_serirq_mode" = "1"
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" # 0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "0"
+ register "com1_address" = "0x3E8"
+ register "com1_irq" = "6"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2E8"
+ register "com2_irq" = "6"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci 8.0 on end # Slot4
+ device pci 9.0 on end # Slot3
+ device pci a.0 on end # Slot2
+ device pci b.0 on end # Slot1
+ device pci c.0 on end # IT8888
+ device pci e.0 on end # Ethernet
+ device pci f.0 on # ISA bridge
+ chip superio/ite/it8712f
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # EC
+ io 0x60 = 0x290
+ io 0x62 = 0x230
+ irq 0x70 = 9
+ end
+ device pnp 2e.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x62 = 0x1220
+ # io 0x64 = 0x1200
+ end
+ device pnp 2e.8 off # MIDI
+ io 0x60 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.9 off # Game port
+ io 0x60 = 0x220
+ end
+ device pnp 2e.a off end # CIR
+ end
+ end
+ device pci f.2 on end # IDE controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+ # APIC cluster is late CPU init.
+ device apic_cluster 0 on
+ chip cpu/amd/model_lx
+ device apic 0 on end
+ end
+ end
+end
diff --git a/src/mainboard/lippert/spacerunner-lx/devicetree.cb b/src/mainboard/lippert/spacerunner-lx/devicetree.cb
new file mode 100644
index 0000000..f6d5535
--- /dev/null
+++ b/src/mainboard/lippert/spacerunner-lx/devicetree.cb
@@ -0,0 +1,90 @@
+chip northbridge/amd/lx
+ device pci_domain 0 on
+ device pci 1.0 on end # Northbridge
+ device pci 1.1 on end # Graphics
+ device pci 1.2 on end # AES
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
+ # UARTs, etc IRQs. OK
+ register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010
+ register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above
+ register "lpc_serirq_mode" = "1"
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" # 0:host, 1:device
+ register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "0"
+ register "com1_address" = "0x3E8"
+ register "com1_irq" = "6"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2E8"
+ register "com2_irq" = "6"
+ register "unwanted_vpci[0]" = "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8
+ register "unwanted_vpci[1]" = "0" # End of list has a zero
+ device pci 8.0 on end # Slot4
+ device pci 9.0 on end # Slot3
+ device pci a.0 on end # Slot2
+ device pci b.0 on end # Slot1
+ device pci c.0 on end # IT8888
+ device pci e.0 on end # Ethernet
+ device pci f.0 on # ISA Bridge
+ chip superio/ite/it8712f
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # EC
+ io 0x60 = 0x290
+ io 0x62 = 0x230
+ irq 0x70 = 9
+ end
+ device pnp 2e.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x62 = 0x1220
+ io 0x64 = 0x1200
+ end
+ device pnp 2e.8 off # MIDI
+ io 0x60 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.9 off # Game port
+ io 0x60 = 0x220
+ end
+ device pnp 2e.a off end # CIR
+ end
+ end
+ device pci f.2 on end # IDE
+ device pci f.3 off end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+ # APIC cluster is late CPU init.
+ device apic_cluster 0 on
+ chip cpu/amd/model_lx
+ device apic 0 on end
+ end
+ end
+end
diff --git a/src/mainboard/mitac/Kconfig b/src/mainboard/mitac/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/mitac/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/motorola/Kconfig b/src/mainboard/motorola/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/motorola/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/motorola/sandpoint/devicetree.cb b/src/mainboard/motorola/sandpoint/devicetree.cb
new file mode 100644
index 0000000..5ed46bd
--- /dev/null
+++ b/src/mainboard/motorola/sandpoint/devicetree.cb
@@ -0,0 +1,30 @@
+##
+## Config file for the Motorola Sandpoint III development system.
+## Note that this has only been tested with the Altimus 7410 PMC.
+##
+
+##
+## Early board initialization, called from ppc_main()
+##
+initobject init.o
+initobject clock.o
+
+##
+## Stage 2 timer support
+##
+object clock.o
+
+##
+## Set our CONFIG_ARCH
+##
+arch ppc end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+dir nvram
+dir flash
+
+addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
+makedefine CFLAGS += -g
diff --git a/src/mainboard/motorola/sandpointx3_altimus_mpc7410/devicetree.cb b/src/mainboard/motorola/sandpointx3_altimus_mpc7410/devicetree.cb
new file mode 100644
index 0000000..bc13ca4
--- /dev/null
+++ b/src/mainboard/motorola/sandpointx3_altimus_mpc7410/devicetree.cb
@@ -0,0 +1,26 @@
+chip northbridge/motorola/mpc107
+ device pci_domain 0 on
+ device pci 0.0 on end
+ device pci b.0 on
+ chip southbridge/winbond/w83c553
+ chip superio/nsc/pc97307
+ device pnp 15c.0 on end # Kyeboard
+ device pnp 15c.1 on end # Mouse
+ device pnp 15c.2 on end # Real-time Clock
+ device pnp 15c.3 on end # Floppy
+ device pnp 15c.4 on end # Parallel port
+ device pnp 15c.5 on end # com2
+ device pnp 15c.6 on end # com1
+ device pnp 15c.7 on end # gpio
+ device pnp 15c.8 on end # Power management
+ end
+ end
+ end # pci to isa bridge
+ device pci b.1 on end # pci ide controller
+ end
+ device cpu_bus 0 on
+ chip cpu/ppc/mpc74xx
+ device cpu 0 on end
+ end
+ end
+end
diff --git a/src/mainboard/msi/Kconfig b/src/mainboard/msi/Kconfig
new file mode 100644
index 0000000..3a3a38a
--- /dev/null
+++ b/src/mainboard/msi/Kconfig
@@ -0,0 +1,41 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+choice
+ prompt "Mainboard model"
+ depends on VENDOR_MSI
+
+config BOARD_MSI_MS6178
+ bool "MS-6178"
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_PGA370
+ select NORTHBRIDGE_INTEL_I82810
+ select SOUTHBRIDGE_INTEL_I82801XX
+ select SUPERIO_WINBOND_W83627HF
+ select PIRQ_TABLE
+ help
+ MSI MS-6178 mainboard.
+endchoice
+
+config MAINBOARD_DIR
+ string
+ default msi/ms6178
+ depends on BOARD_MSI_MS6178
+
diff --git a/src/mainboard/msi/ms6119/devicetree.cb b/src/mainboard/msi/ms6119/devicetree.cb
new file mode 100644
index 0000000..e5b7bb3
--- /dev/null
+++ b/src/mainboard/msi/ms6119/devicetree.cb
@@ -0,0 +1,60 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 7.0 on # ISA bridge
+ chip superio/winbond/w83977tf # Super I/O
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.3 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.7 on # GPIO 1
+ end
+ device pnp 3f0.8 on # GPIO 2
+ end
+ device pnp 3f0.9 on # GPIO 3
+ end
+ device pnp 3f0.a on # ACPI
+ end
+ end
+ end
+ device pci 7.1 on end # IDE
+ device pci 7.2 on end # USB
+ device pci 7.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "0"
+ register "ide0_drive1_udma33_enable" = "0"
+ register "ide1_drive0_udma33_enable" = "0"
+ register "ide1_drive1_udma33_enable" = "0"
+ end
+ end
+end
diff --git a/src/mainboard/msi/ms6147/devicetree.cb b/src/mainboard/msi/ms6147/devicetree.cb
new file mode 100644
index 0000000..7eff7f4
--- /dev/null
+++ b/src/mainboard/msi/ms6147/devicetree.cb
@@ -0,0 +1,60 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 7.0 on # ISA bridge
+ chip superio/winbond/w83977tf # Super I/O
+ device pnp 3f0.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 3f0.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 3f0.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.3 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 3f0.7 on # GPIO 1
+ end
+ device pnp 3f0.8 on # GPIO 2
+ end
+ device pnp 3f0.9 off # GPIO 3
+ end
+ device pnp 3f0.a on # ACPI
+ end
+ end
+ end
+ device pci 7.1 on end # IDE
+ device pci 7.2 on end # USB
+ device pci 7.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "1"
+ register "ide0_drive1_udma33_enable" = "1"
+ register "ide1_drive0_udma33_enable" = "1"
+ register "ide1_drive1_udma33_enable" = "1"
+ end
+ end
+end
diff --git a/src/mainboard/msi/ms6178/Makefile.inc b/src/mainboard/msi/ms6178/Makefile.inc
new file mode 100644
index 0000000..bc322d4
--- /dev/null
+++ b/src/mainboard/msi/ms6178/Makefile.inc
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+driver-y += mainboard.o
+
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+
+initobj-y += ../../../arch/i386/init/entry.o
+initobj-y += ../../../cpu/intel/model_6ex/car.o # FIXME. romcc.
+# initobj-y += ../../../arch/i386/init/rombootstrap.o
+# initobj-y += ../../../cpu/intel/model_6ex/disable_car.o
+initobj-y += ../../../pc80/mc146818rtc_early.o
+initobj-y += ../../../arch/i386/lib/console.o
+initobj-y += ../../../arch/i386/lib/console_printk.o
+# initobj-y += ../../../ram/ramtest.o # FIXME
+initobj-y += ../../../southbridge/intel/i82801xx/i82801xx_early_smbus.o
+initobj-y += ../../../southbridge/intel/i82801xx/i82801xx_reset.o
+initobj-y += ../../../superio/winbond/w83627hf/w83627hf_early_serial.o
+initobj-y += ../../../northbridge/intel/i82810/raminit.o
+
+ifdef POST_EVALUATION
+
+# FIXME: Drop DCACHE_RAM_BASE/DCACHE_RAM_SIZE, only here to make it build.
+MAINBOARD_OPTIONS=\
+ -DCONFIG_USE_PRINTK_IN_CAR=1 \
+ -DCONFIG_HAVE_HIGH_TABLES=1 \
+ -DCONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0 \
+ -DCONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0 \
+ -DCONFIG_MAINBOARD_VENDOR=\"MSI\" \
+ -DCONFIG_MAINBOARD_PART_NUMBER=\"MS-6178\" \
+ -DCONFIG_DCACHE_RAM_BASE=0xffdf8000 \
+ -DCONFIG_DCACHE_RAM_SIZE=0x8000
+
+endif
+
diff --git a/src/mainboard/msi/ms6178/devicetree.cb b/src/mainboard/msi/ms6178/devicetree.cb
new file mode 100644
index 0000000..94ef95a
--- /dev/null
+++ b/src/mainboard/msi/ms6178/devicetree.cb
@@ -0,0 +1,69 @@
+chip northbridge/intel/i82810 # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_PGA370 # CPU
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 off # Onboard video
+ # chip drivers/pci/onboard
+ # device pci 1.0 on end
+ # register "rom_address" = "0xfff80000"
+ # end
+ end
+ chip southbridge/intel/i82801xx # Southbridge
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # ISA/LPC bridge
+ chip superio/winbond/w83627hf # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2 (only header on board)
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # PS/2 keyboard/mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # Keyboard interrupt
+ irq 0x72 = 12 # Mouse interrupt
+ end
+ device pnp 2e.6 on end # Consumer IR (TODO)
+ device pnp 2e.7 on # Game port / MIDI / GPIO 1
+ io 0x60 = 0x201
+ io 0x62 = 0x330
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 on end # GPIO 2
+ device pnp 2e.9 on end # GPIO 3
+ device pnp 2e.a on end # ACPI
+ device pnp 2e.b on # Hardware monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.2 on end # USB
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 on end # AC'97 audio
+ device pci 1f.6 on end # AC'97 modem
+ end
+ end
+end
+
diff --git a/src/mainboard/msi/ms7135/devicetree.cb b/src/mainboard/msi/ms7135/devicetree.cb
new file mode 100644
index 0000000..d11bd9e
--- /dev/null
+++ b/src/mainboard/msi/ms7135/devicetree.cb
@@ -0,0 +1,76 @@
+chip northbridge/amd/amdk8/root_complex # Root complex
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/amd/socket_754 # Socket 754 CPU
+ device apic 0 on end # APIC
+ end
+ end
+
+ device pci_domain 0 on # PCI domain
+ chip northbridge/amd/amdk8 # mc0
+ device pci 18.0 on # Northbridge
+ # Devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/ck804 # Southbridge
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/winbond/w83627thf # Super I/O
+ device pnp 4e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 4e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 4e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 4e.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 4e.7 off end # Game, MIDI, GPIO 1, GPIO 5
+ device pnp 4e.8 off end # GPIO 2
+ device pnp 4e.9 off end # GPIO 3, GPIO 4
+ device pnp 4e.a off end # ACPI
+ device pnp 4e.b on # Hardware monitor
+ io 0x60 = 0x290
+ irq 0x70 = 0
+ end
+ end
+ end
+ device pci 1.1 on end # SMbus
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # Onboard audio (ACI)
+ device pci 4.1 off end # Onboard modem (MCI) -- not wired out
+ device pci 6.0 on end # IDE
+ device pci 7.0 on end # SATA 1
+ device pci 8.0 on end # SATA 0
+ device pci 9.0 on end # PCI
+ device pci a.0 on end # NIC
+ device pci b.0 off end # PCI E 3 -- not wired out
+ device pci c.0 off end # PCI E 2 -- not wired out
+ device pci d.0 on end # PCI E 1
+ device pci e.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ # register "mac_eeprom_smbus" = "3"
+ # register "mac_eeprom_addr" = "0x51"
+ end
+ end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
diff --git a/src/mainboard/msi/ms7260/devicetree.cb b/src/mainboard/msi/ms7260/devicetree.cb
new file mode 100644
index 0000000..38b0338
--- /dev/null
+++ b/src/mainboard/msi/ms7260/devicetree.cb
@@ -0,0 +1,157 @@
+chip northbridge/amd/amdk8/root_complex # Root complex
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/amd/socket_AM2 # CPU
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ chip northbridge/amd/amdk8 # Northbridge / mc0
+ device pci 18.0 on
+ # Devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/mcp55 # Southbridge
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/winbond/w83627ehg # Super I/O
+ device pnp 4e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 4e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 4e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.3 on # Com2 / IrDA
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 4e.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard IRQ
+ irq 0x72 = 12 # PS/2 mouse IRQ
+ end
+ device pnp 4e.6 off # Serial flash interface
+ # io 0x62 = 0x100
+ end
+ device pnp 4e.7 off # GPIO1/6, game port, MIDI port
+ # io 0x60 = 0x220 # Datasheet: 0x201
+ # io 0x62 = 0x300 # Datasheet: 0x330
+ # irq 0x70 = 9
+ end
+ device pnp 4e.8 off # WDTO#, PLED
+ end
+ device pnp 4e.9 off # GPIO2/3/4/5, SUSLED
+ end
+ device pnp 4e.a off # ACPI
+ end
+ device pnp 4e.b on # HWM (for lm-sensors)
+ io 0x60 = 0xa10
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/generic/generic # DIMM 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic # DIMM 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-1
+ device i2c 53 on end
+ end
+ # TODO: Needed?
+ # chip drivers/generic/generic # DIMM 1-0-0
+ # device i2c 54 on end
+ # end
+ # chip drivers/generic/generic # DIMM 1-0-1
+ # device i2c 55 on end
+ # end
+ # chip drivers/generic/generic # DIMM 1-1-0
+ # device i2c 56 on end
+ # end
+ # chip drivers/generic/generic # DIMM 1-1-1
+ # device i2c 57 on end
+ # end
+ end
+ # TODO: Check if the stuff below is correct / needed.
+ device pci 1.1 on # SM 1
+ # PCI device SMBus address will depend on addon PCI device,
+ # do we need to scan_smbus_bus?
+
+ # chip drivers/generic/generic # PCIXA Slot1
+ # device i2c 50 on end
+ # end
+ # chip drivers/generic/generic # PCIXB Slot1
+ # device i2c 51 on end
+ # end
+ # chip drivers/generic/generic # PCIXB Slot2
+ # device i2c 52 on end
+ # end
+ # chip drivers/generic/generic # PCI Slot1
+ # device i2c 53 on end
+ # end
+ # chip drivers/generic/generic # Master MCP55 PCI-E
+ # device i2c 54 on end
+ # end
+ # chip drivers/generic/generic # Slave MCP55 PCI-E
+ # device i2c 55 on end
+ # end
+ chip drivers/generic/generic # MAC EEPROM
+ device i2c 51 on end
+ end
+ end
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # IDE
+ device pci 5.0 on end # SATA 0
+ device pci 5.1 on end # SATA 1
+ device pci 5.2 off end # SATA 2 (N/A on this board)
+ device pci 6.0 on end # PCI
+ device pci 6.1 on end # AZA (HD Audio)
+ device pci 8.0 on end # NIC
+ device pci 9.0 off end # NIC (N/A on this board)
+ device pci a.0 off end # PCI E 5 (N/A on this board?)
+ device pci b.0 on end # PCI E 4
+ device pci c.0 on end # PCI E 3
+ device pci d.0 on end # PCI E 2
+ device pci e.0 on end # PCI E 1
+ device pci f.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ # TODO: Check the two lines below.
+ register "mac_eeprom_smbus" = "3" # 1: SMBus under 2e.8, 2: SM0 3: SM1
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end
+ device pci 18.0 on end # Link 1
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+
+# TODO
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 on end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 on end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# device pnp 0.8 off end # io
+# device pnp 0.9 off end # io
+# end
+
+end
diff --git a/src/mainboard/msi/ms9185/devicetree.cb b/src/mainboard/msi/ms9185/devicetree.cb
new file mode 100644
index 0000000..23f6c87
--- /dev/null
+++ b/src/mainboard/msi/ms9185/devicetree.cb
@@ -0,0 +1,120 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_F
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.0 on # northbridge
+ # devices on link 0
+ chip southbridge/broadcom/bcm5780 # HT2000
+ device pci 0.0 on end # PXB 1 0x0130
+ device pci 1.0 on # PXB 2 0x0130
+ device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
+ device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
+ end
+ device pci 2.0 on end # PCI E 1 #0x0132
+ device pci 3.0 on end # PCI E 2
+ device pci 4.0 on end # PCI E 3
+ device pci 5.0 on end # PCI E 4
+ end
+ chip southbridge/broadcom/bcm5785 # HT1000
+ device pci 0.0 on # HT PXB 0x0036
+ device pci d.0 on end # PPBX 0x0104
+ device pci e.0 on end # SATA 0x024a
+ device pci e.1 on end # SATA 0x024a bx_a001
+ device pci e.2 on end # SATA 0x024a bx_a001
+ device pci e.3 on end # SATA 0x024a bx_a001
+ end
+ device pci 1.0 on # Legacy pci main 0x0205
+ end
+ device pci 1.1 on end # IDE 0x0214
+ device pci 1.2 on # LPC 0x0234
+ chip superio/nsc/pc87417
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 off # Com 2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Com 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 off end # SWC
+ device pnp 2e.5 off end # Mouse
+ device pnp 2e.6 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.f off end # XBUS
+ device pnp 2e.10 on #RTC
+ io 0x60 = 0x70
+ io 0x62 = 0x72
+ end
+ end
+ end
+ device pci 1.3 on end # WDTimer 0x0238
+ device pci 1.4 on end # XIOAPIC0 0x0235
+ device pci 1.5 on end # XIOAPIC1
+ device pci 1.6 on end # XIOAPIC2
+ device pci 2.0 on end # USB 0x0223
+ device pci 2.1 on end # USB
+ device pci 2.2 on end # USB
+ #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,),
+ chip drivers/pci/onboard
+ device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
+ # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3
+ register "rom_address" = "0xfff80000"
+ end
+ #bx_a013+ start
+ #chip drivers/pci/onboard #SATA2
+ # device pci 5.0 on end
+ # device pci 5.1 on end
+ # device pci 5.2 on end
+ # device pci 5.3 on end
+ #end
+ #bx_a013+ end
+
+ end
+ #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
+# chip drivers/pci/onboard
+# device pci 0.0 on end # fake, will be disabled
+# end
+# chip drivers/pci/onboard
+# device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
+# register "rom_address" = "0xfff80000"
+# end
+
+ end # device pci 18.0
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end # amdk8
+ end #pci_domain
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 off end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 off end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# end
+
+end
+
+
diff --git a/src/mainboard/msi/ms9282/devicetree.cb b/src/mainboard/msi/ms9282/devicetree.cb
new file mode 100644
index 0000000..6fd476b
--- /dev/null
+++ b/src/mainboard/msi/ms9282/devicetree.cb
@@ -0,0 +1,188 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_F
+ device apic 0 on end
+ end
+ end
+
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8 #mc0
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/mcp55
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/winbond/w83627ehg
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # SERIAL_FALSH
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # WDTO_PLED
+ device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/i2c/i2cmux2 # pca9554 smbus mux
+ device i2c 70 on #0 pca9554 1
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 57 on end
+ end
+ end
+ device i2c 70 on #0 pca9554 2
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 57 on end
+ end
+ end
+ end
+ end
+ device pci 1.1 on # SM 1
+ chip drivers/i2c/i2cmux2 # pca9554 smbus mux
+ device i2c 72 on #pca9554 channle1
+ chip drivers/i2c/adm1027 #HWM ADT7476 1
+ device i2c 2e on end
+ end
+ end
+ device i2c 72 on #pca9545 channel 2
+ chip drivers/i2c/adm1027 #HWM ADT7463
+ device i2c 2e on end
+ end
+ end
+ device i2c 72 on end #pca9545 channel 3
+ device i2c 72 on #pca9545 channel 4
+ chip drivers/i2c/adm1027 #HWM ADT7476 2
+ device i2c 2e on end
+ end
+ end
+ end
+ end
+
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # IDE
+ device pci 5.0 on end # SATA 0
+ device pci 5.1 on end # SATA 1
+ device pci 5.2 on end # SATA 2
+ device pci 6.0 on #P2P
+ chip drivers/pci/onboard
+ device pci 4.0 on end
+ register "rom_address" = "0xfff80000"
+ end
+ end # P2P
+ device pci 7.0 on end # reserve
+ device pci 8.0 on end # MAC0
+ device pci 9.0 on end # MAC1
+ device pci a.0 on
+ device pci 0.0 on
+ chip drivers/pci/onboard
+ device pci 4.0 on end #pci_E lan1
+ device pci 4.1 on end #pci_E lan2
+ end
+ end
+ end # 0x376
+ device pci b.0 on end # PCI E 0x374
+ device pci c.0 on end
+ device pci d.0 on #SAS
+ chip drivers/pci/onboard
+ device pci 0.0 on end
+ end
+ end # PCI E 1 0x378
+ device pci e.0 on end # PCI E 0 0x375
+ device pci f.0 on end #PCI E 0x377 pci_E slot
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ end
+ end # device pci 18.0
+ device pci 18.0 on end # Link 1
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end #mc0
+
+ end # pci_domain
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end
+# device pnp 0.1 off end
+# device pnp 0.2 off end
+# device pnp 0.3 off end
+# device pnp 0.4 off end
+# device pnp 0.5 on end
+# end
+end # root_complex
diff --git a/src/mainboard/nec/Kconfig b/src/mainboard/nec/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/nec/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/nec/powermate2000/devicetree.cb b/src/mainboard/nec/powermate2000/devicetree.cb
new file mode 100644
index 0000000..cbbc322
--- /dev/null
+++ b/src/mainboard/nec/powermate2000/devicetree.cb
@@ -0,0 +1,59 @@
+chip northbridge/intel/i82810 # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_PGA370 # CPU
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 off # Onboard video
+ # chip drivers/pci/onboard
+ # device pci 1.0 on end
+ # register "rom_address" = "0xfff80000"
+ # end
+ end
+ chip southbridge/intel/i82801xx # Southbridge
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # ISA/LPC bridge
+ chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47B27x)
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 off end # Com2 (N/A)
+ device pnp 2e.7 on # PS/2 keyboard
+ irq 0x70 = 1
+ irq 0x72 = 0
+ end
+ device pnp 2e.9 off end # Game port (N/A)
+ device pnp 2e.a on # Power-management events (PME)
+ io 0x60 = 0x800
+ end
+ device pnp 2e.b on # MIDI port
+ io 0x60 = 0x330
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.2 on end # USB
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 on end # AC'97 audio
+ device pci 1f.6 off end # AC'97 modem (N/A)
+ end
+ end
+end
+
diff --git a/src/mainboard/newisys/Kconfig b/src/mainboard/newisys/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/newisys/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/newisys/khepri/devicetree.cb b/src/mainboard/newisys/khepri/devicetree.cb
new file mode 100644
index 0000000..cb8f356
--- /dev/null
+++ b/src/mainboard/newisys/khepri/devicetree.cb
@@ -0,0 +1,92 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
+ end
+
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on end # LDT 0
+ device pci 18.0 on # LDT 1
+ chip southbridge/amd/amd8131
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 on end
+ device pci 1.0 on end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 on end
+ device pci 1.6 on end
+ end
+ end # LDT1
+ device pci 18.0 on end # LDT2
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/nvidia/Kconfig b/src/mainboard/nvidia/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/nvidia/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/nvidia/l1_2pvv/devicetree.cb b/src/mainboard/nvidia/l1_2pvv/devicetree.cb
new file mode 100644
index 0000000..5014f09
--- /dev/null
+++ b/src/mainboard/nvidia/l1_2pvv/devicetree.cb
@@ -0,0 +1,178 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_F
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8 #mc0
+ device pci 18.0 on
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/mcp55
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/winbond/w83627ehg
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # SFI
+ io 0x62 = 0x100
+ end
+ device pnp 2e.7 off # GPIO_GAME_MIDI
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # WDTO_PLED
+ device pnp 2e.9 off end # GPIO_SUSLED
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ end # SM
+ device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+# chip drivers/generic/generic #PCIXA Slot1
+# device i2c 50 on end
+# end
+# chip drivers/generic/generic #PCIXB Slot1
+# device i2c 51 on end
+# end
+# chip drivers/generic/generic #PCIXB Slot2
+# device i2c 52 on end
+# end
+# chip drivers/generic/generic #PCI Slot1
+# device i2c 53 on end
+# end
+# chip drivers/generic/generic #Master MCP55 PCI-E
+# device i2c 54 on end
+# end
+# chip drivers/generic/generic #Slave MCP55 PCI-E
+# device i2c 55 on end
+# end
+ chip drivers/generic/generic #MAC EEPROM
+ device i2c 51 on end
+ end
+
+ end # SM
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # IDE
+ device pci 5.0 on end # SATA 0
+ device pci 5.1 on end # SATA 1
+ device pci 5.2 on end # SATA 2
+ device pci 6.0 on end # PCI
+ device pci 6.1 on end # AZA
+ device pci 8.0 on end # NIC
+ device pci 9.0 on end # NIC
+ device pci a.0 on end # PCI E 5
+ device pci b.0 off end # PCI E 4
+ device pci c.0 off end # PCI E 3
+ device pci d.0 on end # PCI E 2
+ device pci e.0 off end # PCI E 1
+ device pci f.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end # device pci 18.0
+ device pci 18.0 on end # Link 1
+ device pci 18.0 on
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/nvidia/mcp55
+ device pci 0.0 on end # HT
+ device pci 1.0 on end # LPC
+ device pci 1.1 on end # SM 0
+ device pci 2.0 off end # USB 1.1
+ device pci 2.1 off end # USB 2
+ device pci 4.0 off end # IDE
+ device pci 5.0 on end # SATA 0
+ device pci 5.1 on end # SATA 1
+ device pci 5.2 on end # SATA 2
+ device pci 6.0 off end # PCI
+ device pci 6.1 off end # AZA
+ device pci 8.0 on end # NIC
+ device pci 9.0 on end # NIC
+ device pci a.0 on end # PCI E 5
+ device pci b.0 off end # PCI E 4
+ device pci c.0 off end # PCI E 3
+ device pci d.0 on end # PCI E 2
+ device pci e.0 on end # PCI E 1
+ device pci f.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end # device pci 18.0
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end # mc0
+
+ end # PCI domain
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 on end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 on end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# device pnp 0.8 off end # io
+# device pnp 0.9 off end # io
+# end
+end #root_complex
diff --git a/src/mainboard/olpc/Kconfig b/src/mainboard/olpc/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/olpc/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/olpc/btest/devicetree.cb b/src/mainboard/olpc/btest/devicetree.cb
new file mode 100644
index 0000000..e0da828
--- /dev/null
+++ b/src/mainboard/olpc/btest/devicetree.cb
@@ -0,0 +1,45 @@
+chip northbridge/amd/gx2
+ register "irqmap" = "0xaa5b"
+ register "setupflash" = "0"
+ device apic_cluster 0 on
+ chip cpu/amd/model_gx2
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ device pci 1.0 on end
+ device pci 1.1 on end
+ chip southbridge/amd/cs5536
+ # 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080.
+ # Frame Pulse Width = 4clocks
+ # IRQ Data Frames = 17Frames
+ # SIRQ Mode = continous , It would be better if the EC could operate in
+ # Active(Quiet) mode. Save power....
+ # SIRQ Enable = Enabled
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+ #register "lpc_irq" = "0x00001002"
+ #register "lpc_serirq_enable" = "0xEFFD0080"
+ #register "enable_gpio0_inta" = "1"
+ #register "enable_ide_nand_flash" = "1"
+ #register "enable_uarta" = "1"
+ #register "enable_USBP4_host" = "1"
+ #register "audio_irq" = "5"
+ #register "usbf4_irq" = "10"
+ #register "usbf5_irq" = "10"
+ #register "usbf6_irq" = "0"
+ #register "usbf7_irq" = "0"
+ device pci d.0 on end # Realtek 8139 LAN
+ device pci f.0 on end # ISA Bridge
+ device pci f.2 on end # IDE Controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC
+ register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG
+ register "unwanted_vpci[2]" = "0" # End of list has a zero
+ end
+ end
+end
+
diff --git a/src/mainboard/olpc/rev_a/devicetree.cb b/src/mainboard/olpc/rev_a/devicetree.cb
new file mode 100644
index 0000000..e0da828
--- /dev/null
+++ b/src/mainboard/olpc/rev_a/devicetree.cb
@@ -0,0 +1,45 @@
+chip northbridge/amd/gx2
+ register "irqmap" = "0xaa5b"
+ register "setupflash" = "0"
+ device apic_cluster 0 on
+ chip cpu/amd/model_gx2
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ device pci 1.0 on end
+ device pci 1.1 on end
+ chip southbridge/amd/cs5536
+ # 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080.
+ # Frame Pulse Width = 4clocks
+ # IRQ Data Frames = 17Frames
+ # SIRQ Mode = continous , It would be better if the EC could operate in
+ # Active(Quiet) mode. Save power....
+ # SIRQ Enable = Enabled
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+ #register "lpc_irq" = "0x00001002"
+ #register "lpc_serirq_enable" = "0xEFFD0080"
+ #register "enable_gpio0_inta" = "1"
+ #register "enable_ide_nand_flash" = "1"
+ #register "enable_uarta" = "1"
+ #register "enable_USBP4_host" = "1"
+ #register "audio_irq" = "5"
+ #register "usbf4_irq" = "10"
+ #register "usbf5_irq" = "10"
+ #register "usbf6_irq" = "0"
+ #register "usbf7_irq" = "0"
+ device pci d.0 on end # Realtek 8139 LAN
+ device pci f.0 on end # ISA Bridge
+ device pci f.2 on end # IDE Controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC
+ register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG
+ register "unwanted_vpci[2]" = "0" # End of list has a zero
+ end
+ end
+end
+
diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/pcengines/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb
new file mode 100644
index 0000000..34668d1
--- /dev/null
+++ b/src/mainboard/pcengines/alix1c/devicetree.cb
@@ -0,0 +1,86 @@
+chip northbridge/amd/lx
+ device pci_domain 0 on
+ device pci 1.0 on end
+ device pci 1.1 on end
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+ # How to get these? Boot linux and do this:
+ # rdmsr 0x51400025
+ register "lpc_serirq_enable" = "0x0000105a"
+ # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
+ register "lpc_serirq_polarity" = "0x0000EFA5"
+ # mode is high 10 bits (determined from code)
+ register "lpc_serirq_mode" = "1"
+ # Don't yet know how to find this.
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" #0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "0"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci f.0 on # ISA Bridge
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 on end # GPIO2
+ device pnp 2e.9 on end # GPIO3
+ device pnp 2e.a on end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci f.1 on end # Flash controller
+ device pci f.2 on end # IDE controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+
+ # APIC cluster is late CPU init.
+ device apic_cluster 0 on
+ chip cpu/amd/model_lx
+ device apic 0 on end
+ end
+ end
+
+end
+
diff --git a/src/mainboard/rca/Kconfig b/src/mainboard/rca/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/rca/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb
new file mode 100644
index 0000000..09d1e2b
--- /dev/null
+++ b/src/mainboard/rca/rm4100/devicetree.cb
@@ -0,0 +1,73 @@
+chip northbridge/intel/i82830 # Northbridge
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ chip drivers/pci/onboard # Onboard VGA
+ device pci 2.0 on end # VGA (Intel 82830 CGC)
+ register "rom_address" = "0xfff00000"
+ end
+ chip southbridge/intel/i82801xx # Southbridge
+ register "pirqa_routing" = "0x05"
+ register "pirqb_routing" = "0x06"
+ register "pirqc_routing" = "0x07"
+ register "pirqd_routing" = "0x09"
+ register "pirqe_routing" = "0x0a"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x0b"
+
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
+ device pci 1d.0 on end # USB UHCI Controller #1
+ device pci 1d.1 on end # USB UHCI Controller #2
+ device pci 1d.2 on end # USB UHCI Controller #3
+ device pci 1d.7 on end # USB2 EHCI Controller
+ device pci 1e.0 on # PCI bridge
+ device pci 08.0 on end # Intel 82801DB PRO/100 VE Ethernet
+ end
+ device pci 1f.0 on # ISA/LPC bridge
+ chip superio/smsc/smscsuperio # Super I/O
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 4
+ end
+ device pnp 2e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 on # Com2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.7 on # PS/2 keyboard/mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # Keyboard interrupt
+ irq 0x72 = 12 # Mouse interrupt
+ end
+ device pnp 2e.9 off end # Game port
+ device pnp 2e.a on # PME
+ io 0x60 = 0x800
+ end
+ device pnp 2e.b off end # MPU-401
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 on end # AC'97 audio
+ device pci 1f.6 on end # AC'97 modem
+ end
+ end
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_PGA370 # Mobile Celeron Micro-FCBGA Socket 479
+ device apic 0 on end # APIC
+ end
+ end
+end
+
diff --git a/src/mainboard/soyo/Kconfig b/src/mainboard/soyo/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/soyo/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/sunw/Kconfig b/src/mainboard/sunw/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/sunw/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/sunw/ultra40/devicetree.cb b/src/mainboard/sunw/ultra40/devicetree.cb
new file mode 100644
index 0000000..01a59f7
--- /dev/null
+++ b/src/mainboard/sunw/ultra40/devicetree.cb
@@ -0,0 +1,155 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8 #mc0
+ device pci 18.0 on end # link 0
+ device pci 18.0 on # link1
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/ck804
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/smsc/lpc47m10x
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.7 off # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ end # SM
+ device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+# chip drivers/generic/generic #PCIXA Slot1
+# device i2c 50 on end
+# end
+# chip drivers/generic/generic #PCIXB Slot1
+# device i2c 51 on end
+# end
+# chip drivers/generic/generic #PCIXB Slot2
+# device i2c 52 on end
+# end
+# chip drivers/generic/generic #PCI Slot1
+# device i2c 53 on end
+# end
+# chip drivers/generic/generic #Master CK804 PCI-E
+# device i2c 54 on end
+# end
+# chip drivers/generic/generic #Slave CK804 PCI-E
+# device i2c 55 on end
+# end
+ chip drivers/generic/generic #MAC EEPROM
+ device i2c 51 on end
+ end
+
+ end # SM
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # ACI
+ device pci 4.1 off end # MCI
+ device pci 6.0 on end # IDE
+ device pci 7.0 on end # SATA 1
+ device pci 8.0 on end # SATA 0
+ device pci 9.0 on end # PCI
+ device pci a.0 on end # NIC
+ device pci b.0 off end # PCI E 3
+ device pci c.0 off end # PCI E 2
+ device pci d.0 off end # PCI E 1
+ device pci e.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+# register "nic_rom_address" = "0xfff80000" # 64k
+# register "raid_rom_address" = "0xfff90000"
+ register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end # device pci 18.0
+ device pci 18.0 on end # link 2
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end # mc0
+
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end # link 0
+ device pci 19.0 on
+ # devices on link 1, link 1 == LDT 1
+ chip southbridge/nvidia/ck804
+ device pci 0.0 on end # HT
+ device pci 1.0 on end # LPC
+ device pci 1.1 off end # SM
+ device pci 2.0 off end # USB 1.1
+ device pci 2.1 off end # USB 2
+ device pci 4.0 off end # ACI
+ device pci 4.1 off end # MCI
+ device pci 6.0 off end # IDE
+ device pci 7.0 off end # SATA 1
+ device pci 8.0 off end # SATA 0
+ device pci 9.0 off end # PCI
+ device pci a.0 on end # NIC
+ device pci b.0 off end # PCI E 3
+ device pci c.0 off end # PCI E 2
+ device pci d.0 off end # PCI E 1
+ device pci e.0 on end # PCI E 0
+# register "nic_rom_address" = "0xfff80000" # 64k
+ register "mac_eeprom_smbus" = "3"
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end # device pci 19.0
+
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end # PCI domain
+
+end #root_complex
diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/supermicro/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/supermicro/h8dme/devicetree.cb b/src/mainboard/supermicro/h8dme/devicetree.cb
new file mode 100644
index 0000000..90491e4
--- /dev/null
+++ b/src/mainboard/supermicro/h8dme/devicetree.cb
@@ -0,0 +1,143 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_F
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8 #mc0
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.0 on
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/mcp55
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # SFI
+ io 0x62 = 0x100
+ end
+ device pnp 2e.7 off # GPIO_GAME_MIDI
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # WDTO_PLED
+ device pnp 2e.9 off end # GPIO_SUSLED
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/i2c/i2cmux2
+ device i2c 48 off end
+ device i2c 49 off end
+ end
+ end # SM
+ device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+# chip drivers/generic/generic #PCIXA Slot1
+# device i2c 50 on end
+# end
+# chip drivers/generic/generic #PCIXB Slot1
+# device i2c 51 on end
+# end
+# chip drivers/generic/generic #PCIXB Slot2
+# device i2c 52 on end
+# end
+# chip drivers/generic/generic #PCI Slot1
+# device i2c 53 on end
+# end
+# chip drivers/generic/generic #Master MCP55 PCI-E
+# device i2c 54 on end
+# end
+# chip drivers/generic/generic #Slave MCP55 PCI-E
+# device i2c 55 on end
+# end
+ chip drivers/generic/generic #MAC EEPROM
+ device i2c 51 on end
+ end
+
+ end # SM
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # IDE
+ device pci 5.0 on end # SATA 0
+ device pci 5.1 on end # SATA 1
+ device pci 5.2 on end # SATA 2
+ device pci 6.0 on # PCI
+ chip drivers/pci/onboard
+ device pci 6.0 on end
+ register "rom_address" = "0xfff00000" #for 1M
+# register "rom_address" = "0xfff80000" #for 512K
+ end
+ end
+ device pci 6.1 on end # AZA
+ device pci 8.0 on end # NIC
+ device pci 9.0 on end # NIC
+ device pci a.0 on # PCI E 5
+ device pci 0.0 on #nec pci-x
+ end
+ device pci 0.1 on #nec pci-x
+ device pci 4.0 on end #scsi
+ device pci 4.1 on end #scsi
+ end
+ end
+ device pci b.0 on end # PCI E 4
+ device pci c.0 on end # PCI E 3
+ device pci d.0 on end # PCI E 2
+ device pci e.0 on end # PCI E 1
+ device pci f.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end # device pci 18.0
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end # mc0
+
+ end # PCI domain
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 off end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 on end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# device pnp 0.8 off end # io
+# device pnp 0.9 on end # io
+# end
+end #root_complex
diff --git a/src/mainboard/supermicro/h8dmr/devicetree.cb b/src/mainboard/supermicro/h8dmr/devicetree.cb
new file mode 100644
index 0000000..9f5fd76
--- /dev/null
+++ b/src/mainboard/supermicro/h8dmr/devicetree.cb
@@ -0,0 +1,163 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_F
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8 #mc0
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.0 on
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/mcp55
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # SFI
+ io 0x62 = 0x100
+ end
+ device pnp 2e.7 off # GPIO_GAME_MIDI
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # WDTO_PLED
+ device pnp 2e.9 off end # GPIO_SUSLED
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ end # SM
+ device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+# chip drivers/generic/generic #PCIXA Slot1
+# device i2c 50 on end
+# end
+# chip drivers/generic/generic #PCIXB Slot1
+# device i2c 51 on end
+# end
+# chip drivers/generic/generic #PCIXB Slot2
+# device i2c 52 on end
+# end
+# chip drivers/generic/generic #PCI Slot1
+# device i2c 53 on end
+# end
+# chip drivers/generic/generic #Master MCP55 PCI-E
+# device i2c 54 on end
+# end
+# chip drivers/generic/generic #Slave MCP55 PCI-E
+# device i2c 55 on end
+# end
+ chip drivers/generic/generic #MAC EEPROM
+ device i2c 51 on end
+ end
+
+ end # SM
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # IDE
+ device pci 5.0 on end # SATA 0
+ device pci 5.1 on end # SATA 1
+ device pci 5.2 on end # SATA 2
+ device pci 6.0 on # PCI
+ chip drivers/pci/onboard
+ device pci 6.0 on end
+ register "rom_address" = "0xfff00000" #for 1M
+# register "rom_address" = "0xfff80000" #for 512K
+ end
+ end
+ device pci 6.1 on end # AZA
+ device pci 8.0 on end # NIC
+ device pci 9.0 on end # NIC
+ device pci a.0 on # PCI E 5
+ device pci 0.0 on #nec pci-x
+ end
+ device pci 0.1 on #nec pci-x
+ device pci 4.0 on end #scsi
+ device pci 4.1 on end #scsi
+ end
+ end
+ device pci b.0 on end # PCI E 4
+ device pci c.0 on end # PCI E 3
+ device pci d.0 on end # PCI E 2
+ device pci e.0 on end # PCI E 1
+ device pci f.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end # device pci 18.0
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end # mc0
+
+ end # PCI domain
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 off end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 on end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# device pnp 0.8 off end # io
+# device pnp 0.9 on end # io
+# end
+end #root_complex
diff --git a/src/mainboard/supermicro/x6dai_g/devicetree.cb b/src/mainboard/supermicro/x6dai_g/devicetree.cb
new file mode 100644
index 0000000..97176b9
--- /dev/null
+++ b/src/mainboard/supermicro/x6dai_g/devicetree.cb
@@ -0,0 +1,64 @@
+chip northbridge/intel/e7525 # mch
+ device pci_domain 0 on
+ chip southbridge/intel/esb6300 # esb6300
+ register "pirq_a_d" = "0x0b0a0a05"
+ register "pirq_e_h" = "0x0a0b0c80"
+
+ device pci 1c.0 on end
+
+ device pci 1d.0 on end
+ device pci 1d.1 on end
+ device pci 1d.4 on end
+ device pci 1d.5 on end
+ device pci 1d.7 on end
+
+ device pci 1e.0 on end
+
+ device pci 1f.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off end
+ device pnp 2e.1 off end
+ device pnp 2e.2 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.4 off end
+ device pnp 2e.5 off end
+ device pnp 2e.6 off end
+ device pnp 2e.7 off end
+ device pnp 2e.9 off end
+ device pnp 2e.a on end
+ device pnp 2e.b off end
+ device pnp 2e.f off end
+ device pnp 2e.10 off end
+ device pnp 2e.14 off end
+ end
+ end
+ device pci 1f.1 on end
+ device pci 1f.2 on end
+ device pci 1f.3 on end
+ device pci 1f.5 off end
+ device pci 1f.6 on end
+ end
+ device pci 00.0 on end
+ device pci 00.1 on end
+ device pci 00.2 on end
+ device pci 02.0 on end
+ device pci 03.0 on end
+ device pci 04.0 on end
+ device pci 08.0 on end
+ end
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA604 # cpu0
+ device apic 0 on end
+ end
+ chip cpu/intel/socket_mPGA604 # cpu1
+ device apic 6 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/supermicro/x6dhe_g/devicetree.cb b/src/mainboard/supermicro/x6dhe_g/devicetree.cb
new file mode 100644
index 0000000..d5625e4
--- /dev/null
+++ b/src/mainboard/supermicro/x6dhe_g/devicetree.cb
@@ -0,0 +1,86 @@
+chip northbridge/intel/e7520 # MCH
+ chip drivers/generic/debug # DEBUGGING
+ device pnp 00.0 on end
+ device pnp 00.1 off end
+ device pnp 00.2 off end
+ device pnp 00.3 off end
+ end
+ device pci_domain 0 on
+ chip southbridge/intel/esb6300 # ESB6300
+ register "pirq_a_d" = "0x0b070a05"
+ register "pirq_e_h" = "0x0a808080"
+
+ device pci 1c.0 on
+ chip drivers/generic/generic
+ device pci 01.0 on end # onboard gige1
+ device pci 02.0 on end # onboard gige2
+ end
+ end
+
+ # USB ports
+ device pci 1d.0 on end
+ device pci 1d.1 on end
+ device pci 1d.4 on end # Southbridge Watchdog timer
+ device pci 1d.5 on end # Southbridge I/O apic1
+ device pci 1d.7 on end
+
+ # VGA / PCI 32-bit
+ device pci 1e.0 on
+ chip drivers/generic/generic
+ device pci 01.0 on end
+ end
+ end
+
+
+ device pci 1f.0 on # ISA bridge
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off end
+ device pnp 2e.2 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.4 off end
+ device pnp 2e.5 off end
+ device pnp 2e.6 off end
+ device pnp 2e.7 off end
+ device pnp 2e.9 off end
+ device pnp 2e.a on end
+ device pnp 2e.b off end
+ end
+ end
+ device pci 1f.1 on end
+ device pci 1f.2 off end
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end
+ device pci 1f.6 off end
+ end
+
+ device pci 00.0 on end # Northbridge
+ device pci 00.1 on end # Northbridge Error reporting
+ device pci 01.0 on end
+ device pci 02.0 on
+ chip southbridge/intel/pxhd # PXHD 6700
+ device pci 00.0 on end # bridge
+ device pci 00.1 on end # I/O apic
+ device pci 00.2 on end # bridge
+ device pci 00.3 on end # I/O apic
+ end
+ end
+# device register "intrline" = "0x00070105"
+ device pci 04.0 on end
+ device pci 06.0 on end
+ end
+
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA604 # CPU 0
+ device apic 0 on end
+ end
+ chip cpu/intel/socket_mPGA604 # CPU 1
+ device apic 6 on end
+ end
+ end
+end
diff --git a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
new file mode 100644
index 0000000..4bb7207
--- /dev/null
+++ b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
@@ -0,0 +1,86 @@
+chip northbridge/intel/e7520 # MCH
+ chip drivers/generic/debug # DEBUGGING
+ device pnp 00.0 off end
+ device pnp 00.1 off end
+ device pnp 00.2 off end
+ device pnp 00.3 off end
+ end
+ device pci_domain 0 on
+ chip southbridge/intel/i82801er # ICH5R
+ register "pirq_a_d" = "0x0b070a05"
+ register "pirq_e_h" = "0x0a808080"
+
+ device pci 1c.0 on
+ chip drivers/generic/generic
+ device pci 01.0 on end # onboard gige1
+ device pci 02.0 on end # onboard gige2
+ end
+ end
+
+ # USB ports
+ device pci 1d.0 on end
+ device pci 1d.1 on end
+ device pci 1d.4 on end # Southbridge Watchdog timer
+ device pci 1d.5 on end # Southbridge I/O apic1
+ device pci 1d.7 on end
+
+ # VGA / PCI 32-bit
+ device pci 1e.0 on
+ chip drivers/generic/generic
+ device pci 01.0 on end
+ end
+ end
+
+
+ device pci 1f.0 on # ISA bridge
+ chip superio/nsc/pc87427
+ device pnp 2e.0 off end
+ device pnp 2e.2 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.4 off end
+ device pnp 2e.5 off end
+ device pnp 2e.6 off end
+ device pnp 2e.7 off end
+ device pnp 2e.9 off end
+ device pnp 2e.a on end
+ device pnp 2e.b off end
+ end
+ end
+ device pci 1f.1 on end
+ device pci 1f.2 on end
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end
+ device pci 1f.6 off end
+ end
+
+ device pci 00.0 on end # Northbridge
+ device pci 00.1 on end # Northbridge Error reporting
+ device pci 01.0 on end
+ device pci 02.0 on
+ chip southbridge/intel/pxhd # PXHD 6700
+ device pci 00.0 on end # bridge
+ device pci 00.1 on end # I/O apic
+ device pci 00.2 on end # bridge
+ device pci 00.3 on end # I/O apic
+ end
+ end
+# device register "intrline" = "0x00070105"
+ device pci 04.0 on end
+ device pci 06.0 on end
+ end
+
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA604 # CPU 0
+ device apic 0 on end
+ end
+ chip cpu/intel/socket_mPGA604 # CPU 1
+ device apic 6 on end
+ end
+ end
+end
diff --git a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
new file mode 100644
index 0000000..8a82ed7
--- /dev/null
+++ b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
@@ -0,0 +1,84 @@
+chip northbridge/intel/e7520 # mch
+ device pci_domain 0 on
+ chip southbridge/intel/i82801er # i82801er
+ # USB ports
+ device pci 1d.0 on end
+ device pci 1d.1 on end
+ device pci 1d.2 on end
+ device pci 1d.3 on end
+ device pci 1d.7 on end
+
+ # -> VGA
+ device pci 1e.0 on end
+
+ # -> IDE
+ device pci 1f.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off end
+ device pnp 2e.2 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.4 off end
+ device pnp 2e.5 off end
+ device pnp 2e.6 off end
+ device pnp 2e.7 off end
+ device pnp 2e.9 off end
+ device pnp 2e.a on end
+ device pnp 2e.b off end
+ end
+ end
+ device pci 1f.1 on end
+ device pci 1f.2 on end
+ device pci 1f.3 on end
+
+ register "pirq_a_d" = "0x0b070a05"
+ register "pirq_e_h" = "0x0a808080"
+ end
+ device pci 00.0 on end
+ device pci 00.1 on end
+ device pci 01.0 on end
+ device pci 02.0 on end
+ device pci 03.0 on
+ chip southbridge/intel/pxhd # pxhd1
+ # Bus bridges and ioapics usually bus 2
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 on
+ # On board gig e1000
+ chip drivers/generic/generic
+ device pci 02.0 on end
+ device pci 02.1 on end
+ end
+ end
+ device pci 0.3 on end
+ end
+ end
+ device pci 04.0 on
+ chip southbridge/intel/pxhd # pxhd2
+ # Bus bridges and ioapics usually bus 5
+ device pci 0.0 on end
+ # Slot 6 is usually 6:2.0
+ device pci 0.1 on end
+ device pci 0.2 on end
+ # Slot 7 is usually 7:2.0
+ device pci 0.3 on end
+ end
+ end
+ device pci 06.0 on end
+ end
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA604 # cpu 0
+ device apic 0 on end
+ end
+ chip cpu/intel/socket_mPGA604 # cpu 1
+ device apic 6 on end
+ end
+ end
+ register "intrline" = "0x00070105"
+end
+
diff --git a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
new file mode 100644
index 0000000..ab56509
--- /dev/null
+++ b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
@@ -0,0 +1,75 @@
+chip northbridge/intel/e7520 # mch
+ device pci_domain 0 on
+ chip southbridge/intel/i82801er # i82801er
+ # USB ports
+ device pci 1d.0 on end
+ device pci 1d.1 on end
+ device pci 1d.2 on end
+ device pci 1d.3 on end
+ device pci 1d.7 on end
+
+ # -> Bridge
+ device pci 1e.0 on end
+
+ # -> ISA
+ device pci 1f.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off end
+ device pnp 2e.2 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.4 off end
+ device pnp 2e.5 off end
+ device pnp 2e.6 off end
+ device pnp 2e.7 off end
+ device pnp 2e.9 off end
+ device pnp 2e.a on end
+ device pnp 2e.b off end
+ end
+ end
+ # -> IDE
+ device pci 1f.1 on end
+ # -> SATA
+ device pci 1f.2 on end
+ device pci 1f.3 on end
+
+ register "pirq_a_d" = "0x0b070a05"
+ register "pirq_e_h" = "0x0a808080"
+ end
+ device pci 00.0 on end
+ device pci 00.1 on end
+ device pci 01.0 on end
+ device pci 02.0 on
+ chip southbridge/intel/pxhd # pxhd1
+ # Bus bridges and ioapics usually bus 1
+ device pci 0.0 on
+ # On board gig e1000
+ chip drivers/generic/generic
+ device pci 03.0 on end
+ device pci 03.1 on end
+ end
+ end
+ device pci 0.1 on end
+ device pci 0.2 on end
+ device pci 0.3 on end
+ end
+ end
+ device pci 04.0 on end
+ device pci 06.0 on end
+ end
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA604 # cpu 0
+ device apic 0 on end
+ end
+ chip cpu/intel/socket_mPGA604 # cpu 1
+ device apic 6 on end
+ end
+ end
+ register "intrline" = "0x00070105"
+end
+
diff --git a/src/mainboard/technexion/Kconfig b/src/mainboard/technexion/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/technexion/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/technexion/tim8690/devicetree.cb b/src/mainboard/technexion/tim8690/devicetree.cb
new file mode 100644
index 0000000..cb06914
--- /dev/null
+++ b/src/mainboard/technexion/tim8690/devicetree.cb
@@ -0,0 +1,117 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_S1G1
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # southbridge
+ chip southbridge/amd/rs690
+ device pci 0.0 on end # HT 0x7910
+ device pci 1.0 on # Internal Graphics P2P bridge 0x7912
+ chip drivers/pci/onboard
+ device pci 5.0 on end # Internal Graphics 0x791F
+ register "rom_address" = "0xfff80000"
+ end
+ end
+ device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
+ device pci 3.0 off end # PCIE P2P bridge 0x791b
+ device pci 4.0 on end # PCIE P2P bridge 0x7914
+ device pci 5.0 on end # PCIE P2P bridge 0x7915
+ device pci 6.0 on end # PCIE P2P bridge 0x7916
+ device pci 7.0 on end # PCIE P2P bridge 0x7917
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ register "vga_rom_address" = "0xfff80000"
+ register "gpp_configuration" = "4"
+ register "port_enable" = "0xfc"
+ register "gfx_dev2_dev3" = "1"
+ register "gfx_dual_slot" = "0"
+ register "gfx_lane_reversal" = "0"
+ register "gfx_tmds" = "0"
+ register "gfx_compliance" = "0"
+ register "gfx_reconfiguration" = "1"
+ register "gfx_link_width" = "0"
+ end
+ chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
+ device pci 12.0 on end # SATA 0x4380
+ device pci 13.0 on end # USB 0x4387
+ device pci 13.1 on end # USB 0x4388
+ device pci 13.2 on end # USB 0x4389
+ device pci 13.3 on end # USB 0x438a
+ device pci 13.4 on end # USB 0x438b
+ device pci 13.5 on end # USB 2 0x4386
+ device pci 14.0 on # SM 0x4385
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ end # SM
+ device pci 14.1 on end # IDE 0x438c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x438d
+ chip superio/ite/it8712f
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 off end # EC
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 on # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
+ end
+ device pnp 2e.8 off # MIDI
+ io 0x60 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.9 off # GAME
+ io 0x60 = 0x220
+ end
+ device pnp 2e.a off end # CIR
+ end #superio/ite/it8712f
+ end #LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 on end # ACI 0x4382
+ device pci 14.6 on end # MCI 0x438e
+ register "ide0_enable" = "1"
+ register "sata0_enable" = "1"
+ register "hda_viddid" = "0x10ec0882"
+ end #southbridge/amd/sb600
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end #northbridge/amd/amdk8
+ end #pci_domain
+end #northbridge/amd/amdk8/root_complex
+
diff --git a/src/mainboard/technologic/Kconfig b/src/mainboard/technologic/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/technologic/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/technologic/ts5300/devicetree.cb b/src/mainboard/technologic/ts5300/devicetree.cb
new file mode 100644
index 0000000..4e75251
--- /dev/null
+++ b/src/mainboard/technologic/ts5300/devicetree.cb
@@ -0,0 +1,16 @@
+chip cpu/amd/sc520
+ device pci_domain 0 on
+ device pci 0.0 on end
+
+# chip drivers/pci/onboard
+# device pci 12.0 on end # enet
+# end
+# chip drivers/pci/onboard
+# device pci 14.0 on end # 69000
+# register "rom_address" = "0x2000000"
+# end
+# register "com1" = "{1}"
+# register "com1" = "{1, 0, 0x3f8, 4}"
+ end
+
+end
diff --git a/src/mainboard/televideo/Kconfig b/src/mainboard/televideo/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/televideo/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/televideo/tc7020/devicetree.cb b/src/mainboard/televideo/tc7020/devicetree.cb
new file mode 100644
index 0000000..bf89cf2
--- /dev/null
+++ b/src/mainboard/televideo/tc7020/devicetree.cb
@@ -0,0 +1,57 @@
+chip northbridge/amd/gx1 # Northbridge
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ chip southbridge/amd/cs5530 # Southbridge
+ device pci 12.0 on # ISA bridge
+ chip superio/nsc/pc97317 # Super I/O
+ device pnp 2e.0 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.1 on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.2 on # RTC, Advanced power control (APC)
+ io 0x60 = 0x70
+ irq 0x70 = 8
+ end
+ device pnp 2e.3 off # Floppy (N/A on this board)
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.4 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.5 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.6 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0xe0
+ end
+ device pnp 2e.8 on # Power management
+ io 0x60 = 0xe8
+ end
+ end
+ end
+ device pci 12.1 off end # SMI
+ device pci 12.2 on end # IDE
+ device pci 12.3 on end # Audio
+ device pci 12.4 on end # VGA (onboard)
+ device pci 13.0 on end # USB
+ device pci 14.0 on end # MiniPCI slot
+ device pci 15.0 on end # Ethernet (onboard)
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "0" # Not available/needed on this board
+ end
+ end
+ chip cpu/amd/model_gx1 # CPU
+ end
+end
diff --git a/src/mainboard/thomson/Kconfig b/src/mainboard/thomson/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/thomson/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/thomson/ip1000/devicetree.cb b/src/mainboard/thomson/ip1000/devicetree.cb
new file mode 100644
index 0000000..c3e0e7f
--- /dev/null
+++ b/src/mainboard/thomson/ip1000/devicetree.cb
@@ -0,0 +1,73 @@
+chip northbridge/intel/i82830 # Northbridge
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ chip drivers/pci/onboard # Onboard VGA
+ device pci 2.0 on end # VGA (Intel 82830 CGC)
+ register "rom_address" = "0xfff00000"
+ end
+ chip southbridge/intel/i82801xx # Southbridge
+ register "pirqa_routing" = "0x05"
+ register "pirqb_routing" = "0x06"
+ register "pirqc_routing" = "0x07"
+ register "pirqd_routing" = "0x09"
+ register "pirqe_routing" = "0x0a"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x0b"
+
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
+ device pci 1d.0 on end # USB UHCI Controller #1
+ device pci 1d.1 on end # USB UHCI Controller #2
+ device pci 1d.2 on end # USB UHCI Controller #3
+ device pci 1d.7 on end # USB2 EHCI Controller
+ device pci 1e.0 on # PCI bridge
+ device pci 08.0 on end # Intel 82801DB PRO/100 VE Ethernet
+ end
+ device pci 1f.0 on # ISA/LPC bridge
+ chip superio/smsc/smscsuperio # Super I/O
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 4
+ end
+ device pnp 2e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 on # Com2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.7 on # PS/2 keyboard/mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # Keyboard interrupt
+ irq 0x72 = 12 # Mouse interrupt
+ end
+ device pnp 2e.9 off end # Game port
+ device pnp 2e.a on # PME
+ io 0x60 = 0x800
+ end
+ device pnp 2e.b off end # MPU-401
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 on end # AC'97 audio
+ device pci 1f.6 off end # AC'97 modem
+ end
+ end
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_PGA370 # Low Voltage PIII Micro-FCBGA Socket 479
+ device apic 0 on end # APIC
+ end
+ end
+end
+
diff --git a/src/mainboard/totalimpact/Kconfig b/src/mainboard/totalimpact/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/totalimpact/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/totalimpact/briq/devicetree.cb b/src/mainboard/totalimpact/briq/devicetree.cb
new file mode 100644
index 0000000..ceb2787
--- /dev/null
+++ b/src/mainboard/totalimpact/briq/devicetree.cb
@@ -0,0 +1,22 @@
+chip northbridge/ibm/cpc710
+ device pci_domain 0 on # 32bit pci bridge
+ device pci 0.0 on
+ chip southbridge/winbond/w83c553
+ # FIXME The function numbers are ok but the device id is wrong here!
+ device pci 0.0 on end # pci to isa bridge
+ device pci 0.1 on end # pci ide controller
+ end
+ end
+ end
+ device cpu_bus 0 on
+ # chip cpu/ppc/ppc7xx
+ # device cpu 0 on end
+ # end
+ end
+end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
diff --git a/src/mainboard/tyan/Kconfig b/src/mainboard/tyan/Kconfig
new file mode 100644
index 0000000..792d600
--- /dev/null
+++ b/src/mainboard/tyan/Kconfig
@@ -0,0 +1 @@
+#
diff --git a/src/mainboard/tyan/s1846/devicetree.cb b/src/mainboard/tyan/s1846/devicetree.cb
new file mode 100644
index 0000000..b938fa3
--- /dev/null
+++ b/src/mainboard/tyan/s1846/devicetree.cb
@@ -0,0 +1,55 @@
+chip northbridge/intel/i440bx # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 7.0 on # ISA bridge
+ chip superio/nsc/pc87309 # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 on # Power management
+ end
+ device pnp 2e.5 on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.6 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ end
+ end
+ device pci 7.1 on end # IDE
+ device pci 7.2 on end # USB
+ device pci 7.3 on end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "0"
+ register "ide0_drive1_udma33_enable" = "0"
+ register "ide1_drive0_udma33_enable" = "0"
+ register "ide1_drive1_udma33_enable" = "0"
+ end
+ end
+end
diff --git a/src/mainboard/tyan/s2735/devicetree.cb b/src/mainboard/tyan/s2735/devicetree.cb
new file mode 100644
index 0000000..d491f6c
--- /dev/null
+++ b/src/mainboard/tyan/s2735/devicetree.cb
@@ -0,0 +1,91 @@
+chip northbridge/intel/e7501
+ device pci_domain 0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 2.0 on
+ chip southbridge/intel/i82870
+ device pci 1c.0 on end
+ device pci 1d.0 on
+ chip drivers/pci/onboard
+ device pci 1.0 on end # intel lan
+ device pci 1.1 on end
+ end
+ end
+ device pci 1e.0 on end
+ device pci 1f.0 on end
+ end
+ end
+ device pci 6.0 on end
+ chip southbridge/intel/i82801er
+ device pci 1d.0 on end
+ device pci 1d.1 on end
+ device pci 1d.2 on end
+ device pci 1d.3 on end
+ device pci 1d.7 on end
+ device pci 1e.0 on
+ chip drivers/pci/onboard
+ device pci 1.0 on end # intel lan 10/100
+ end
+ chip drivers/pci/onboard
+ device pci 2.0 on end # ati
+ end
+ end
+ device pci 1f.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1f.1 off end
+ device pci 1f.2 on end
+ device pci 1f.3 on end
+ device pci 1f.5 off end
+ device pci 1f.6 off end
+ end # SB
+ end # PCI_DOMAIN
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA604
+ device apic 0 on end
+ end
+ chip cpu/intel/socket_mPGA604
+ device apic 6 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/tyan/s2850/devicetree.cb b/src/mainboard/tyan/s2850/devicetree.cb
new file mode 100644
index 0000000..ebb4fe6
--- /dev/null
+++ b/src/mainboard/tyan/s2850/devicetree.cb
@@ -0,0 +1,98 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # LDT0
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ #chip drivers/ati/ragexl
+ chip drivers/pci/onboard
+ device pci b.0 on end
+ register "rom_address" = "0xfff80000"
+ end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ end
+ device pci 1.5 on end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+ device pci 18.0 on end
+ device pci 18.0 on end
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/tyan/s2875/devicetree.cb b/src/mainboard/tyan/s2875/devicetree.cb
new file mode 100644
index 0000000..1b4bb28
--- /dev/null
+++ b/src/mainboard/tyan/s2875/devicetree.cb
@@ -0,0 +1,90 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/amd/amd8151
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 1.0 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ chip drivers/pci/onboard
+ device pci 5.0 on end
+ register "rom_address" = "0xfff80000"
+ end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 on end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/tyan/s2880/devicetree.cb b/src/mainboard/tyan/s2880/devicetree.cb
new file mode 100644
index 0000000..9d1e44c
--- /dev/null
+++ b/src/mainboard/tyan/s2880/devicetree.cb
@@ -0,0 +1,105 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on
+ chip drivers/pci/onboard
+ device pci 9.0 on end #broadcom
+ device pci 9.1 on end
+ end
+# chip drivers/lsi/53c1030
+# device pci a.0 on end
+# device pci a.1 on end
+# register "fw_address" = "0xfff8c000"
+# end
+ end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ chip drivers/pci/onboard
+ device pci 5.0 on end #some sata
+ end
+ chip drivers/pci/onboard
+ device pci 6.0 on end #adti
+ register "rom_address" = "0xfff80000"
+ end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/tyan/s2881/devicetree.cb b/src/mainboard/tyan/s2881/devicetree.cb
new file mode 100644
index 0000000..57673a9
--- /dev/null
+++ b/src/mainboard/tyan/s2881/devicetree.cb
@@ -0,0 +1,140 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on end # LDT0
+ device pci 18.0 on end # LDT1
+ device pci 18.0 on # northbridge
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on
+ chip drivers/pci/onboard
+ device pci 9.0 on end # Broadcom 5704
+ device pci 9.1 on end
+ end
+ chip drivers/pci/onboard
+ device pci a.0 on end # Adaptic
+ device pci a.1 on end
+ end
+ end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ chip drivers/pci/onboard
+ device pci 5.0 on end # SiI
+ end
+ chip drivers/pci/onboard
+ device pci 6.0 on end
+ register "rom_address" = "0xfff80000"
+ end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ chip drivers/i2c/adm1027 # ADT7463A CPU0/1 temp, CPU1 vid, SYS FAN 1/2/3
+ device i2c 2d on end
+ end
+ chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 4,CPU0 vid, CPU0/1 FAN
+ device i2c 2a on end
+ end
+ chip drivers/generic/generic # Winbond HWM 0x92
+ device i2c 49 on end
+ end
+ chip drivers/generic/generic # Winbond HWM 0x94
+ device i2c 4a on end
+ end
+ end # acpi
+ device pci 1.5 off end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
+
diff --git a/src/mainboard/tyan/s2882/devicetree.cb b/src/mainboard/tyan/s2882/devicetree.cb
new file mode 100644
index 0000000..3c18bb6
--- /dev/null
+++ b/src/mainboard/tyan/s2882/devicetree.cb
@@ -0,0 +1,135 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on
+ chip drivers/pci/onboard
+ device pci 6.0 on end # adaptec
+ device pci 6.1 on end
+ end
+ chip drivers/pci/onboard
+ device pci 9.0 on end # broadcom 5704
+ device pci 9.1 on end
+ end
+ end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ chip drivers/pci/onboard
+ device pci 5.0 on end
+ end
+ # chip drivers/ati/ragexl
+ chip drivers/pci/onboard
+ device pci 6.0 on end
+ register "rom_address" = "0xfff00000"
+ end
+ chip drivers/pci/onboard
+ device pci 8.0 on end #intel 10/100
+ end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.3 on
+# chip drivers/generic/generic #dimm 0-0-0
+# device i2c 50 on end
+# end
+# chip drivers/generic/generic #dimm 0-0-1
+# device i2c 51 on end
+# end
+# chip drivers/generic/generic #dimm 0-1-0
+# device i2c 52 on end
+# end
+# chip drivers/generic/generic #dimm 0-1-1
+# device i2c 53 on end
+# end
+# chip drivers/generic/generic #dimm 1-0-0
+# device i2c 54 on end
+# end
+# chip drivers/generic/generic #dimm 1-0-1
+# device i2c 55 on end
+# end
+# chip drivers/generic/generic #dimm 1-1-0
+# device i2c 56 on end
+# end
+# chip drivers/generic/generic #dimm 1-1-1
+# device i2c 57 on end
+# end
+ end # acpi
+ device pci 1.5 off end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end # NB
+ end #pci_domain
+end
+
diff --git a/src/mainboard/tyan/s2885/devicetree.cb b/src/mainboard/tyan/s2885/devicetree.cb
new file mode 100644
index 0000000..8a98150
--- /dev/null
+++ b/src/mainboard/tyan/s2885/devicetree.cb
@@ -0,0 +1,135 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # LDT0
+ chip southbridge/amd/amd8151
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 1.0 on end
+ end
+ end
+ device pci 18.0 on end # LDT1
+ device pci 18.0 on # northbridge
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on
+ chip drivers/pci/onboard
+ device pci 9.0 on end # broadcom 5703
+ end
+ end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ chip drivers/pci/onboard
+ device pci b.0 on end # SiI 3114
+ end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ end # acpi
+ device pci 1.5 on end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+
+ end #pci_domain
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end
+# device pnp 0.1 off end
+# device pnp 0.2 off end
+# device pnp 0.3 off end
+# device pnp 0.4 off end
+# device pnp 0.5 on end
+# end
+end
+
diff --git a/src/mainboard/tyan/s2891/devicetree.cb b/src/mainboard/tyan/s2891/devicetree.cb
new file mode 100644
index 0000000..6f04732
--- /dev/null
+++ b/src/mainboard/tyan/s2891/devicetree.cb
@@ -0,0 +1,158 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8 #mc0
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/ck804
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b off # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+# chip drivers/generic/generic #dimm 0-0-0
+# device i2c 50 on end
+# end
+# chip drivers/generic/generic #dimm 0-0-1
+# device i2c 51 on end
+# end
+# chip drivers/generic/generic #dimm 0-1-0
+# device i2c 52 on end
+# end
+# chip drivers/generic/generic #dimm 0-1-1
+# device i2c 53 on end
+# end
+# chip drivers/generic/generic #dimm 1-0-0
+# device i2c 54 on end
+# end
+# chip drivers/generic/generic #dimm 1-0-1
+# device i2c 55 on end
+# end
+# chip drivers/generic/generic #dimm 1-1-0
+# device i2c 56 on end
+# end
+# chip drivers/generic/generic #dimm 1-1-1
+# device i2c 57 on end
+# end
+ end # SM
+# device pci 1.1 on # SM 1
+# chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
+# device i2c 2d on end
+# end
+# chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
+# device i2c 2e on end
+# end
+# chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
+# device i2c 2a on end
+# end
+# chip drivers/generic/generic # Winbond HWM 0x92
+# device i2c 49 on end
+# end
+# chip drivers/generic/generic # Winbond HWM 0x94
+# device i2c 4a on end
+# end
+# end #SM
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 off end # ACI
+ device pci 4.1 off end # MCI
+ device pci 6.0 on end # IDE
+ device pci 7.0 on end # SATA 1
+ device pci 8.0 on end # SATA 0
+ device pci 9.0 on # PCI
+ # chip drivers/ati/ragexl
+ chip drivers/pci/onboard
+ device pci 7.0 on end
+ #register "rom_address" = "0xfff80000" #for 512K
+ register "rom_address" = "0xfff00000" #for 1M
+ end
+ end
+ device pci a.0 off end # NIC
+ device pci b.0 off end # PCI E 3
+ device pci c.0 off end # PCI E 2
+ device pci d.0 on end # PCI E 1
+ device pci e.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ end
+ end # device pci 18.0
+ device pci 18.0 on end # Link 1
+ device pci 18.0 on
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on
+ chip drivers/pci/onboard
+ device pci 9.0 on end
+ device pci 9.1 on end
+ end
+ end
+ device pci 1.1 on end
+ end
+ end # device pci 18.0
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end #mc0
+
+ end # pci_domain
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 off end # pci_regs_all
+# device pnp 0.2 off end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 off end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# device pnp 0.8 on end # hard_reset
+# end
+end # root_complex
diff --git a/src/mainboard/tyan/s2892/devicetree.cb b/src/mainboard/tyan/s2892/devicetree.cb
new file mode 100644
index 0000000..b7b13b5
--- /dev/null
+++ b/src/mainboard/tyan/s2892/devicetree.cb
@@ -0,0 +1,158 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8 #mc0
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/ck804
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ end # SM
+ device pci 1.1 on # SM 1
+ chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
+ device i2c 2d on end
+ end
+ chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
+ device i2c 2e on end
+ end
+ chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
+ device i2c 2a on end
+ end
+ chip drivers/generic/generic # Winbond HWM 0x92
+ device i2c 49 on end
+ end
+ chip drivers/generic/generic # Winbond HWM 0x94
+ device i2c 4a on end
+ end
+ end #SM
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 off end # ACI
+ device pci 4.1 off end # MCI
+ device pci 6.0 on end # IDE
+ device pci 7.0 on end # SATA 1
+ device pci 8.0 on end # SATA 0
+ device pci 9.0 on # PCI
+ # chip drivers/ati/ragexl
+ chip drivers/pci/onboard
+ device pci 6.0 on end
+ register "rom_address" = "0xfff80000"
+ end
+ chip drivers/pci/onboard
+ device pci 8.0 on end
+ end
+ end
+ device pci a.0 off end # NIC
+ device pci b.0 off end # PCI E 3
+ device pci c.0 off end # PCI E 2
+ device pci d.0 on end # PCI E 1
+ device pci e.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ end
+ end # device pci 18.0
+ device pci 18.0 on end # Link 1
+ device pci 18.0 on
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on
+ chip drivers/pci/onboard
+ device pci 9.0 on end # broadcom 5704
+ device pci 9.1 on end
+ end
+ end
+ device pci 1.1 on end
+ end
+ end # device pci 18.0
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end #mc0
+
+ end # pci_domain
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end
+# device pnp 0.1 off end
+# device pnp 0.2 off end
+# device pnp 0.3 off end
+# device pnp 0.4 off end
+# device pnp 0.5 on end
+# end
+end # root_complex
diff --git a/src/mainboard/tyan/s2895/devicetree.cb b/src/mainboard/tyan/s2895/devicetree.cb
new file mode 100644
index 0000000..8ff77ee
--- /dev/null
+++ b/src/mainboard/tyan/s2895/devicetree.cb
@@ -0,0 +1,173 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8 #mc0
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/ck804
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/smsc/lpc47b397
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.3 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 4
+ end
+ device pnp 2e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.7 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.8 on # HW Monitor
+ io 0x60 = 0x480
+ chip drivers/generic/generic # LM95221 CPU temp
+ device i2c 2b on end
+ end
+ chip drivers/generic/generic # EMCT03
+ device i2c 54 on end
+ end
+ end
+ device pnp 2e.a on # RT
+ io 0x60 = 0x400
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ end # SM
+ device pci 1.1 on # SM 1
+ chip drivers/generic/generic #MAC EEPROM
+ device i2c 51 on end
+ end
+
+ end # SM
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # ACI
+ device pci 4.1 off end # MCI
+ device pci 6.0 on end # IDE
+ device pci 7.0 on end # SATA 1
+ device pci 8.0 on end # SATA 0
+ device pci 9.0 on end # PCI
+ device pci a.0 on end # NIC
+ device pci b.0 off end # PCI E 3
+ device pci c.0 off end # PCI E 2
+ device pci d.0 off end # PCI E 1
+ device pci e.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+# register "nic_rom_address" = "0xfff80000" # 64k
+# register "raid_rom_address" = "0xfff90000"
+ register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end # device pci 18.0
+ device pci 18.0 on end # Link 1
+ device pci 18.0 on
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on
+ chip drivers/pci/onboard
+ device pci 6.0 on end # lsi scsi
+ device pci 6.1 on end
+ end
+ end
+ device pci 1.1 on end
+ end
+ end # device pci 18.0
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end #mc0
+
+ chip northbridge/amd/amdk8
+ device pci 19.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/ck804
+ device pci 0.0 on end # HT
+ device pci 1.0 on end # LPC
+ device pci 1.1 off end # SM
+ device pci 2.0 off end # USB 1.1
+ device pci 2.1 off end # USB 2
+ device pci 4.0 off end # ACI
+ device pci 4.1 off end # MCI
+ device pci 6.0 off end # IDE
+ device pci 7.0 off end # SATA 1
+ device pci 8.0 off end # SATA 0
+ device pci 9.0 off end # PCI
+ device pci a.0 on end # NIC
+ device pci b.0 off end # PCI E 3
+ device pci c.0 off end # PCI E 2
+ device pci d.0 off end # PCI E 1
+ device pci e.0 on end # PCI E 0
+# register "nic_rom_address" = "0xfff80000" # 64k
+ register "mac_eeprom_smbus" = "3"
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end # device pci 19.0
+
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end # PCI domain
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 off end # pci_regs_all
+# device pnp 0.2 off end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 on end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# end
+end # root_complex
diff --git a/src/mainboard/tyan/s2912/devicetree.cb b/src/mainboard/tyan/s2912/devicetree.cb
new file mode 100644
index 0000000..530d06b
--- /dev/null
+++ b/src/mainboard/tyan/s2912/devicetree.cb
@@ -0,0 +1,150 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_F
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8 #mc0
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.0 on
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/mcp55
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # SFI
+ io 0x62 = 0x100
+ end
+ device pnp 2e.7 off # GPIO_GAME_MIDI
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # WDTO_PLED
+ device pnp 2e.9 off end # GPIO_SUSLED
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ end # SM
+ device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+# chip drivers/generic/generic #PCIXA Slot1
+# device i2c 50 on end
+# end
+# chip drivers/generic/generic #PCIXB Slot1
+# device i2c 51 on end
+# end
+# chip drivers/generic/generic #PCIXB Slot2
+# device i2c 52 on end
+# end
+# chip drivers/generic/generic #PCI Slot1
+# device i2c 53 on end
+# end
+# chip drivers/generic/generic #Master MCP55 PCI-E
+# device i2c 54 on end
+# end
+# chip drivers/generic/generic #Slave MCP55 PCI-E
+# device i2c 55 on end
+# end
+ chip drivers/generic/generic #MAC EEPROM
+ device i2c 51 on end
+ end
+
+ end # SM
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # IDE
+ device pci 5.0 on end # SATA 0
+ device pci 5.1 on end # SATA 1
+ device pci 5.2 on end # SATA 2
+ device pci 6.0 on end # PCI
+ device pci 6.1 off end # AZA
+ device pci 8.0 on end # NIC
+ device pci 9.0 on end # NIC
+ device pci a.0 on end # PCI E 5
+ device pci b.0 off end # PCI E 4
+ device pci c.0 off end # PCI E 3
+ device pci d.0 on end # PCI E 2
+ device pci e.0 off end # PCI E 1
+ device pci f.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end # device pci 18.0
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end # mc0
+
+ end # PCI domain
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 on end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 on end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# device pnp 0.8 off end # io
+# device pnp 0.9 off end # io
+# end
+end #root_complex
diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb
new file mode 100644
index 0000000..d02b81c
--- /dev/null
+++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb
@@ -0,0 +1,156 @@
+chip northbridge/amd/amdfam10/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_F_1207
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdfam10 #mc0
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.0 on
+ # SB on link 2.0.
+ chip southbridge/nvidia/mcp55
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # SFI
+ io 0x62 = 0x100
+ end
+ device pnp 2e.7 off # GPIO_GAME_MIDI
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # WDTO_PLED
+ device pnp 2e.9 off end # GPIO_SUSLED
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ end # SM
+ device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+# chip drivers/generic/generic #PCIXA Slot1
+# device i2c 50 on end
+# end
+# chip drivers/generic/generic #PCIXB Slot1
+# device i2c 51 on end
+# end
+# chip drivers/generic/generic #PCIXB Slot2
+# device i2c 52 on end
+# end
+# chip drivers/generic/generic #PCI Slot1
+# device i2c 53 on end
+# end
+# chip drivers/generic/generic #Master MCP55 PCI-E
+# device i2c 54 on end
+# end
+# chip drivers/generic/generic #Slave MCP55 PCI-E
+# device i2c 55 on end
+# end
+ chip drivers/generic/generic #MAC EEPROM
+ device i2c 51 on end
+ end
+
+ end # SM
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # IDE
+ device pci 5.0 on end # SATA 0
+ device pci 5.1 on end # SATA 1
+ device pci 5.2 on end # SATA 2
+ device pci 6.0 on
+ chip drivers/pci/onboard
+ device pci 4.0 on end
+ register "rom_address" = "0xfff00000"
+ end
+ end # PCI
+ device pci 6.1 off end # AZA
+ device pci 8.0 on end # NIC
+ device pci 9.0 on end # NIC
+ device pci a.0 on end # PCI E 5
+ device pci b.0 off end # PCI E 4
+ device pci c.0 off end # PCI E 3
+ device pci d.0 on end # PCI E 2
+ device pci e.0 off end # PCI E 1
+ device pci f.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end # device pci 18.0
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ end # mc0
+
+ end # PCI domain
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 on end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 on end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# device pnp 0.8 off end # io
+# device pnp 0.9 off end # io
+# end
+end #root_complex
diff --git a/src/mainboard/tyan/s4880/devicetree.cb b/src/mainboard/tyan/s4880/devicetree.cb
new file mode 100644
index 0000000..7dec1bcd
--- /dev/null
+++ b/src/mainboard/tyan/s4880/devicetree.cb
@@ -0,0 +1,103 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on end # LDT0
+ device pci 18.0 on end # LDT1
+ device pci 18.0 on # northbridge
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on
+# chip drivers/lsi/53c1030
+# device pci 4.0 on end
+# device pci 4.1 on end
+# register "fw_address" = "0xfff8c000"
+# end
+ chip drivers/pci/onboard
+ device pci 9.0 on end
+ device pci 9.1 on end
+ end
+ end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ chip drivers/pci/onboard
+ device pci 6.0 on end
+ register "rom_address" = "0xfff80000"
+ end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+
+ end #pci_domain
+end
+
diff --git a/src/mainboard/tyan/s4882/devicetree.cb b/src/mainboard/tyan/s4882/devicetree.cb
new file mode 100644
index 0000000..1524a84
--- /dev/null
+++ b/src/mainboard/tyan/s4882/devicetree.cb
@@ -0,0 +1,211 @@
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on end # LDT0
+ device pci 18.0 on # northbridge
+ # devices on link 1, link 1 == LDT 1
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on
+# chip drivers/lsi/53c1030
+# device pci 4.0 on end
+# device pci 4.1 on end
+# register "fw_address" = "0xfff8c000"
+# end
+ chip drivers/pci/onboard
+ device pci 9.0 on end #Broadcom
+ device pci 9.1 on end
+ end
+ end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ #chip drivers/ati/ragexl
+ chip drivers/pci/onboard
+ device pci 6.0 on end
+ register "rom_address" = "0xfff80000"
+ end
+ chip drivers/pci/onboard
+ device pci 5.0 on end #SiI
+ end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on
+# chip drivers/i2c/i2cmux # pca9556 smbus mux
+# device i2c 18 on #0 pca9516 2, 1
+# chip drivers/i2c/lm63 #cpu0 temp
+# device i2c 4c on end
+# end
+# end
+# device i2c 18 on #1 pca9516 1, 1
+# chip drivers/generic/generic #dimm 1-0-0
+# device i2c 50 on end
+# end
+# chip drivers/generic/generic #dimm 1-0-1
+# device i2c 51 on end
+# end
+# chip drivers/generic/generic #dimm 1-1-0
+# device i2c 52 on end
+# end
+# chip drivers/generic/generic #dimm 1-1-1
+# device i2c 53 on end
+# end
+# end
+# device i2c 18 on #2 pca9516 1, 2
+# chip drivers/generic/generic #dimm 0-0-0
+# device i2c 50 on end
+# end
+# chip drivers/generic/generic #dimm 0-0-1
+# device i2c 51 on end
+# end
+# chip drivers/generic/generic #dimm 0-1-0
+# device i2c 52 on end
+# end
+# chip drivers/generic/generic #dimm 0-1-1
+# device i2c 53 on end
+# end
+# end
+# device i2c 18 on #3 pca9516 1, 3
+# chip drivers/generic/generic #dimm 3-0-0
+# device i2c 50 on end
+# end
+# chip drivers/generic/generic #dimm 3-0-1
+# device i2c 51 on end
+# end
+# chip drivers/generic/generic #dimm 3-1-0
+# device i2c 52 on end
+# end
+# chip drivers/generic/generic #dimm 3-1-1
+# device i2c 53 on end
+# end
+# end
+# device i2c 18 on #4 pca9516 1, 4
+# chip drivers/generic/generic #dimm 2-0-0
+# device i2c 50 on end
+# end
+# chip drivers/generic/generic #dimm 2-0-1
+# device i2c 51 on end
+# end
+# chip drivers/generic/generic #dimm 2-1-0
+# device i2c 52 on end
+# end
+# chip drivers/generic/generic #dimm 2-1-1
+# device i2c 53 on end
+# end
+# end
+# device i2c 18 on #5 pca9516 2, 2
+# chip drivers/i2c/lm63 #cpu1 temp
+# device i2c 4c on end
+# end
+# end
+# device i2c 18 on #6 pca9516 2, 3
+# chip drivers/i2c/lm63 #cpu2 temp
+# device i2c 4c on end
+# end
+# end
+# device i2c 18 on #7 pca9516 2, 4
+# chip drivers/i2c/lm63 #cpu3 temp
+# device i2c 4c on end
+# end
+# end
+# end # i2cmux
+# chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN...
+# device i2c 2e on end
+# end
+# chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid
+# device i2c 2a on end
+# end
+# chip drivers/generic/generic # Winbond HWM 0x92
+# device i2c 49 on end
+# end
+# chip drivers/generic/generic # Winbond HWM 0x94
+# device i2c 4a on end
+# end
+# chip drivers/generic/generic # ??
+# device i2c 69 on end
+# end
+ end # acpi
+ device pci 1.5 off end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+
+ device pci 18.0 on end
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+
+ end
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 off end # pci_regs_all
+# device pnp 0.2 off end # mem
+# device pnp 0.3 on end # cpuid
+# device pnp 0.4 off end # smbus_regs_all
+# device pnp 0.5 on end # dual core msr
+# device pnp 0.6 on end # cache size
+# device pnp 0.7 on end # tsc
+# end
+end
+
diff --git a/src/mainboard/via/Kconfig b/src/mainboard/via/Kconfig
new file mode 100644
index 0000000..ba0f11b
--- /dev/null
+++ b/src/mainboard/via/Kconfig
@@ -0,0 +1,37 @@
+choice
+ prompt "Mainboard model"
+ depends on VENDOR_VIA
+
+config BOARD_VIA_VT8454C
+ bool "vt8454c"
+ select ARCH_X86
+ select CPU_VIA_C7
+ select NORTHBRIDGE_VIA_CX700
+# select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_VIA_VT1211
+ select PIRQ_TABLE
+# select MMCONF_SUPPORT
+ select USE_PRINTK_IN_CAR
+ help
+ Kontron 986LCD-M Series mainboards
+endchoice
+
+config MAINBOARD_DIR
+ string
+ default via/vt8454c
+ depends on BOARD_VIA_VT8454C
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffef0000
+ depends on BOARD_VIA_VT8454C
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+ depends on BOARD_VIA_VT8454C
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "VT8454C"
+ depends on BOARD_VIA_VT8454C
diff --git a/src/mainboard/via/epia-cn/devicetree.cb b/src/mainboard/via/epia-cn/devicetree.cb
new file mode 100644
index 0000000..6425239
--- /dev/null
+++ b/src/mainboard/via/epia-cn/devicetree.cb
@@ -0,0 +1,61 @@
+chip northbridge/via/cn700 # Northbridge
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # AGP Bridge
+ device pci 0.1 on end # Error Reporting
+ device pci 0.2 on end # Host Bus Control
+ device pci 0.3 on end # Memory Controller
+ device pci 0.4 on end # Power Management
+ device pci 0.7 on end # V-Link Controller
+ device pci 1.0 on end # PCI Bridge
+ chip southbridge/via/vt8237r # Southbridge
+ # Enable both IDE channels.
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ # Both cables are 40pin.
+ register "ide0_80pin_cable" = "0"
+ register "ide1_80pin_cable" = "0"
+ device pci f.0 on end # IDE
+ register "fn_ctrl_lo" = "0x80"
+ register "fn_ctrl_hi" = "0x1d"
+ device pci 10.0 on end # OHCI
+ device pci 10.1 on end # OHCI
+ device pci 10.2 on end # OHCI
+ device pci 10.3 on end # OHCI
+ device pci 10.4 on end # EHCI
+ device pci 10.5 on end # UDCI
+ device pci 11.0 on # Southbridge LPC
+ chip superio/via/vt1211 # Super I/O
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.b on # HWM
+ io 0x60 = 0xec00
+ end
+ end
+ end
+ device pci 11.5 on end # AC'97 audio
+ # device pci 11.6 off end # AC'97 Modem
+ device pci 12.0 on end # Ethernet
+ end
+ end
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/via/model_c7 # VIA C7
+ device apic 0 on end # APIC
+ end
+ end
+end
diff --git a/src/mainboard/via/epia-m/devicetree.cb b/src/mainboard/via/epia-m/devicetree.cb
new file mode 100644
index 0000000..2b9abec
--- /dev/null
+++ b/src/mainboard/via/epia-m/devicetree.cb
@@ -0,0 +1,57 @@
+chip northbridge/via/vt8623
+
+ device apic_cluster 0 on
+ chip cpu/via/model_c3
+ device apic 0 on end
+ end
+ end
+
+ device pci_domain 0 on
+ chip southbridge/via/vt8235
+
+ device pci 10.0 on end # USB 1.1
+ device pci 10.1 on end # USB 1.1
+ device pci 10.2 on end # USB 1.1
+ device pci 10.3 on end # USB 2
+
+ device pci 11.0 on # Southbridge
+ chip superio/via/vt1211
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.b on # HWM
+ io 0x60 = 0xec00
+ end
+
+ end
+ end
+
+ device pci 11.1 on end # IDE
+ # 2-4 non existant?
+ device pci 11.5 on end # AC97 Audio
+ device pci 11.6 off end # AC97 Modem
+ device pci 12.0 on end # Ethernet
+ end
+# This is on the EPIA MII, not the M.
+ chip southbridge/ricoh/rl5c476
+ register "enable_cf" = "1"
+ device pci 0a.0 on end
+ device pci 0a.1 on end
+ end
+ end
+end
diff --git a/src/mainboard/via/epia-m700/devicetree.cb b/src/mainboard/via/epia-m700/devicetree.cb
new file mode 100644
index 0000000..008399a
--- /dev/null
+++ b/src/mainboard/via/epia-m700/devicetree.cb
@@ -0,0 +1,24 @@
+chip northbridge/via/vx800 # Northbridge
+ device pci_domain 0 on
+ device pci 0.0 on end # AGP Bridge
+ device pci 0.1 on end # Error Reporting
+ device pci 0.2 on end # Host Bus Control
+ device pci 0.3 on end # Memory Controller
+ device pci 0.4 on end # Power Management
+ device pci 0.7 on end # V-Link Controller
+ device pci 1.0 on end # PCI Bridge
+ # device pci f.0 on end # IDE/SATA
+ # device pci f.1 on end # IDE
+ # device pci 10.0 on end # USB 1.1
+ # device pci 10.1 on end # USB 1.1
+ # device pci 10.2 on end # USB 1.1
+ # device pci 10.4 on end # USB 2.0
+ # device pci 11.0 on # Southbridge LPC
+ # end
+ end
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/via/model_c7 # VIA C7
+ device apic 0 on end # APIC
+ end
+ end
+end
diff --git a/src/mainboard/via/epia/devicetree.cb b/src/mainboard/via/epia/devicetree.cb
new file mode 100644
index 0000000..b75ee58
--- /dev/null
+++ b/src/mainboard/via/epia/devicetree.cb
@@ -0,0 +1,65 @@
+chip northbridge/via/vt8601
+ device pci_domain 0 on
+ device pci 0.0 on end # Northbridge
+# device pci 0.1 on # AGP bridge
+ # chip drivers/pci/onboard # Integrated VGA
+ # device pci 0.0 on end
+ # register "rom_adress" = "0xfff80000"
+ # end
+# end
+ chip southbridge/via/vt8231
+ register "enable_native_ide" = "0"
+ register "enable_com_ports" = "1"
+ register "enable_keyboard" = "0"
+ device pci 11.0 on # Southbrdge
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ register "com1" = "{CONFIG_TTYS0_BAUD}"
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ end
+ device pci 11.1 on end # Ide
+ device pci 11.2 off end # Usb port 0-1
+ device pci 11.3 off end # Usb port 2-3
+ device pci 11.4 off end # ACPI
+ device pci 11.5 off end # AC97 Audio
+ device pci 11.6 on end # AC97 Modem
+ device pci 12.0 on end # Ethernet
+ end
+ end
+
+ device apic_cluster 0 on
+ chip cpu/via/model_c3
+ device apic 0 on end
+ end
+ end
+end
diff --git a/src/mainboard/via/pc2500e/devicetree.cb b/src/mainboard/via/pc2500e/devicetree.cb
new file mode 100644
index 0000000..c03d000
--- /dev/null
+++ b/src/mainboard/via/pc2500e/devicetree.cb
@@ -0,0 +1,88 @@
+chip northbridge/via/cn700 # Northbridge
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # AGP Bridge
+ device pci 0.1 on end # Error Reporting
+ device pci 0.2 on end # Host Bus Control
+ device pci 0.3 on end # Memory Controller
+ device pci 0.4 on end # Power Management
+ device pci 0.7 on end # V-Link Controller
+ device pci 1.0 on end # PCI Bridge
+ chip southbridge/via/vt8237r # Southbridge
+ # Enable both IDE channels.
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ # Both cables are 40pin.
+ register "ide0_80pin_cable" = "0"
+ register "ide1_80pin_cable" = "0"
+ device pci f.0 on end # SATA
+ device pci f.1 on end # IDE
+ register "fn_ctrl_lo" = "0x80"
+ register "fn_ctrl_hi" = "0x1d"
+ device pci 10.0 on end # UHCI
+ device pci 10.1 on end # UHCI
+ device pci 10.2 on end # UHCI
+ device pci 10.3 on end # UHCI
+ device pci 10.4 on end # EHCI
+ device pci 10.5 on end # UDCI
+ device pci 11.0 on # Southbridge LPC
+ chip superio/ite/it8716f # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # COM2 (N/A on this board)
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.4 on # Environment controller
+ io 0x60 = 0x290
+ io 0x62 = 0x0000
+ irq 0x70 = 9
+ end
+ device pnp 2e.5 off # PS/2 keyboard (not used)
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 off # PS/2 mouse (not used)
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x0000
+ io 0x62 = 0x0800
+ io 0x64 = 0x0000
+ end
+ device pnp 2e.8 off # MIDI port (N/A)
+ io 0x60 = 0x300
+ irq 0x70 = 10
+ end
+ device pnp 2e.9 off # Game port (N/A)
+ io 0x60 = 0x201
+ end
+ device pnp 2e.a on # Consumer IR
+ io 0x60 = 0x310
+ irq 0x70 = 11
+ end
+ end
+ end
+ device pci 11.5 on end # AC'97 audio
+ # device pci 11.6 off end # AC'97 modem (N/A)
+ device pci 12.0 on end # Ethernet
+ end
+ end
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/via/model_c7 # VIA C7
+ device apic 0 on end # APIC
+ end
+ end
+end
diff --git a/src/mainboard/via/vt8454c/Makefile.inc b/src/mainboard/via/vt8454c/Makefile.inc
new file mode 100644
index 0000000..d74c632
--- /dev/null
+++ b/src/mainboard/via/vt8454c/Makefile.inc
@@ -0,0 +1,64 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
+##
+
+driver-y += mainboard.o
+
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/via/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+ iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+ mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+ perl -e 's/\.rodata/.rom.data/g' -pi $@
+ perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+
diff --git a/src/mainboard/via/vt8454c/devicetree.cb b/src/mainboard/via/vt8454c/devicetree.cb
new file mode 100644
index 0000000..02f9514
--- /dev/null
+++ b/src/mainboard/via/vt8454c/devicetree.cb
@@ -0,0 +1,59 @@
+chip northbridge/via/cx700
+ device apic_cluster 0 on
+ chip cpu/via/model_c7
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ device pci 0.0 on end # AGP Bridge
+ device pci 0.1 on end # Error Reporting
+ device pci 0.2 on end # Host Bus Control
+ device pci 0.3 on end # Memory Controller
+ device pci 0.4 on end # Power Management
+ device pci 0.7 on end # V-Link Controller
+ device pci 1.0 on # PCI Bridge
+ chip drivers/pci/onboard
+ device pci 0.0 on end
+ #register "rom_address" = "0xfffc0000" #256k image
+ register "rom_address" = "0xfff80000" #512k image
+ #register "rom_address" = "0xfff00000" #1024k image
+ end # Onboard Video
+ end # PCI Bridge
+ device pci f.0 on end # IDE/SATA
+ #device pci f.1 on end # IDE
+ device pci 10.0 on end # USB 1.1
+ device pci 10.1 on end # USB 1.1
+ device pci 10.2 on end # USB 1.1
+ device pci 10.4 on end # USB 2.0
+ device pci 11.0 on # Southbridge LPC
+ chip superio/via/vt1211
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.b on # HWM
+ io 0x60 = 0xec00
+ end
+ end # superio
+ end # pci 11.0
+ # 1-4 non existant
+ #device pci 11.5 on end # AC97 Audio
+ #device pci 11.6 off end # AC97 Modem
+ #device pci 12.0 on end # Ethernet
+ end # pci domain 0
+end # cx700
+
diff --git a/src/northbridge/Kconfig b/src/northbridge/Kconfig
new file mode 100644
index 0000000..666ff4d
--- /dev/null
+++ b/src/northbridge/Kconfig
@@ -0,0 +1,5 @@
+#source src/northbridge/amd/Kconfig
+#source src/northbridge/ibm/Kconfig
+source src/northbridge/intel/Kconfig
+#source src/northbridge/motorola/Kconfig
+source src/northbridge/via/Kconfig
diff --git a/src/northbridge/Makefile.inc b/src/northbridge/Makefile.inc
new file mode 100644
index 0000000..8aac9b9
--- /dev/null
+++ b/src/northbridge/Makefile.inc
@@ -0,0 +1,5 @@
+#subdirs-y += amd
+#subdirs-y += ibm
+subdirs-y += intel
+#subdirs-y += motorola
+subdirs-y += via
diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig
new file mode 100644
index 0000000..30c9070
--- /dev/null
+++ b/src/northbridge/amd/Kconfig
@@ -0,0 +1,7 @@
+#source src/northbridge/amd/amdfam10/Kconfig
+#source src/northbridge/amd/amdht/Kconfig
+source src/northbridge/amd/amdk8/Kconfig
+#source src/northbridge/amd/amdmct/Kconfig
+#source src/northbridge/amd/gx1/Kconfig
+#source src/northbridge/amd/gx2/Kconfig
+#source src/northbridge/amd/lx/Kconfig
diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc
new file mode 100644
index 0000000..06e9314
--- /dev/null
+++ b/src/northbridge/amd/Makefile.inc
@@ -0,0 +1,8 @@
+subdirs-$(CPU_AMD_K10) += amdfam10
+subdirs-$(CPU_AMD_HT) += amdht
+subdirs-$(CPU_AMD_K8) += amdk8
+subdirs-$(CPU_AMD_MCT) += amdmct
+subdirs-$(CPU_AMD_GX1) += gx1
+subdirs-$(CPU_AMD_GX2) += gx2
+subdirs-$(CPU_AMD_LX) += lx
+
diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig
new file mode 100644
index 0000000..171f1f5
--- /dev/null
+++ b/src/northbridge/amd/amdk8/Kconfig
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+config NORTHBRIDGE_AMD_AMDK8
+ bool
+ default n
diff --git a/src/northbridge/amd/amdk8/root_complex/Kconfig b/src/northbridge/amd/amdk8/root_complex/Kconfig
new file mode 100644
index 0000000..a1cd24e
--- /dev/null
+++ b/src/northbridge/amd/amdk8/root_complex/Kconfig
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+config NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+ bool
+ default n
diff --git a/src/northbridge/ibm/Kconfig b/src/northbridge/ibm/Kconfig
new file mode 100644
index 0000000..7f893b0
--- /dev/null
+++ b/src/northbridge/ibm/Kconfig
@@ -0,0 +1,2 @@
+#source src/northbridge/ibm/cpc710/Kconfig
+#source src/northbridge/ibm/cpc925/Kconfig
diff --git a/src/northbridge/ibm/Makefile.inc b/src/northbridge/ibm/Makefile.inc
new file mode 100644
index 0000000..aebf07c
--- /dev/null
+++ b/src/northbridge/ibm/Makefile.inc
@@ -0,0 +1,2 @@
+subdirs-y += cpc710
+subdirs-y += cpc925
diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig
new file mode 100644
index 0000000..61a832e
--- /dev/null
+++ b/src/northbridge/intel/Kconfig
@@ -0,0 +1,10 @@
+#source src/northbridge/intel/e7501/Kconfig
+#source src/northbridge/intel/e7520/Kconfig
+#source src/northbridge/intel/e7525/Kconfig
+#source src/northbridge/intel/i3100/Kconfig
+#source src/northbridge/intel/i440bx/Kconfig
+source src/northbridge/intel/i82810/Kconfig
+#source src/northbridge/intel/i82830/Kconfig
+#source src/northbridge/intel/i855gme/Kconfig
+#source src/northbridge/intel/i855pm/Kconfig
+source src/northbridge/intel/i945/Kconfig
diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc
new file mode 100644
index 0000000..34ed9aa
--- /dev/null
+++ b/src/northbridge/intel/Makefile.inc
@@ -0,0 +1,10 @@
+#subdirs-y += e7501
+#subdirs-y += e7520
+#subdirs-y += e7525
+#subdirs-y += i3100
+#subdirs-y += i440bx
+subdirs-y += i82810
+#subdirs-y += i82830
+#subdirs-y += i855gme
+#subdirs-y += i855pm
+subdirs-y += i945
diff --git a/src/northbridge/intel/i82810/Kconfig b/src/northbridge/intel/i82810/Kconfig
new file mode 100644
index 0000000..62f3705
--- /dev/null
+++ b/src/northbridge/intel/i82810/Kconfig
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config HAVE_HIGH_TABLES
+ bool "Do we have high tables"
+ default y
+
+config NORTHBRIDGE_INTEL_I82810
+ bool
+ default n
+
diff --git a/src/northbridge/intel/i82810/Makefile.inc b/src/northbridge/intel/i82810/Makefile.inc
new file mode 100644
index 0000000..6c8ffe9
--- /dev/null
+++ b/src/northbridge/intel/i82810/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+driver-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += northbridge.o
+
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
new file mode 100644
index 0000000..468602d
--- /dev/null
+++ b/src/northbridge/intel/i945/Kconfig
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+config NORTHBRIDGE_INTEL_I945
+ bool
+ default n
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
new file mode 100644
index 0000000..290ea0c
--- /dev/null
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -0,0 +1,24 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+driver-$(CONFIG_NORTHBRIDGE_INTEL_I945) += northbridge.o
+driver-$(CONFIG_NORTHBRIDGE_INTEL_I945) += gma.o
+ifeq ($(CONFIG_HAVE_ACPI_TABLES),y)
+ obj-$(CONFIG_NORTHBRIDGE_INTEL_I945) += acpi.o
+endif
diff --git a/src/northbridge/motorola/Kconfig b/src/northbridge/motorola/Kconfig
new file mode 100644
index 0000000..9e1258a
--- /dev/null
+++ b/src/northbridge/motorola/Kconfig
@@ -0,0 +1 @@
+#source src/northbridge/motorola/mpc107/Kconfig
diff --git a/src/northbridge/motorola/Makefile.inc b/src/northbridge/motorola/Makefile.inc
new file mode 100644
index 0000000..8ad991b0
--- /dev/null
+++ b/src/northbridge/motorola/Makefile.inc
@@ -0,0 +1 @@
+subdirs-y += mpc107
diff --git a/src/northbridge/via/Kconfig b/src/northbridge/via/Kconfig
new file mode 100644
index 0000000..0ed85e6
--- /dev/null
+++ b/src/northbridge/via/Kconfig
@@ -0,0 +1,5 @@
+#source src/northbridge/via/cn700/Kconfig
+source src/northbridge/via/cx700/Kconfig
+#source src/northbridge/via/vt8601/Kconfig
+#source src/northbridge/via/vt8623/Kconfig
+#source src/northbridge/via/vx800/Kconfig
diff --git a/src/northbridge/via/Makefile.inc b/src/northbridge/via/Makefile.inc
new file mode 100644
index 0000000..7062ea5
--- /dev/null
+++ b/src/northbridge/via/Makefile.inc
@@ -0,0 +1,6 @@
+#subdirs-y += vt8601
+#subdirs-y += vt8623
+#subdirs-y += cn700
+subdirs-y += cx700
+#subdirs-y += vx800
+
diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig
new file mode 100644
index 0000000..d103dd1
--- /dev/null
+++ b/src/northbridge/via/cx700/Kconfig
@@ -0,0 +1,3 @@
+config NORTHBRIDGE_VIA_CX700
+ bool
+ default n
diff --git a/src/northbridge/via/cx700/Makefile.inc b/src/northbridge/via/cx700/Makefile.inc
new file mode 100644
index 0000000..1f9e50e9
--- /dev/null
+++ b/src/northbridge/via/cx700/Makefile.inc
@@ -0,0 +1,25 @@
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
+obj-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_reset.o
+obj-$(CONFIG_NORTHBRIDGE_VIA_CX700) += northbridge.o
+obj-$(CONFIG_NORTHBRIDGE_VIA_CX700) += vgabios.o
+
+driver-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_agp.o
+driver-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_lpc.o
+driver-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_sata.o
+driver-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_vga.o
diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc
new file mode 100644
index 0000000..a54c5ee
--- /dev/null
+++ b/src/pc80/Makefile.inc
@@ -0,0 +1,9 @@
+obj-y += mc146818rtc.o
+obj-y += isa-dma.o
+obj-y += i8259.o
+#obj-y += udelay_timer2.o CONFIG_UDELAY_TIMER2
+obj-$(CONFIG_UDELAY_IO) += udelay_io.o
+obj-y += keyboard.o
+
+#initobj-y += serial.o
+
diff --git a/src/pc80/serial.c b/src/pc80/serial.c
index 4157364..6048d8b 100644
--- a/src/pc80/serial.c
+++ b/src/pc80/serial.c
@@ -71,7 +71,7 @@
uart_wait_until_sent();
}
-static void uart_init(void)
+void uart_init(void)
{
/* disable interrupts */
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
diff --git a/src/southbridge/Kconfig b/src/southbridge/Kconfig
new file mode 100644
index 0000000..51a4fb5
--- /dev/null
+++ b/src/southbridge/Kconfig
@@ -0,0 +1,8 @@
+#source src/southbridge/amd/Kconfig
+#source src/southbridge/broadcom/Kconfig
+source src/southbridge/intel/Kconfig
+#source src/southbridge/nvidia/Kconfig
+#source src/southbridge/ricoh/Kconfig
+#source src/southbridge/sis/Kconfig
+#source src/southbridge/via/Kconfig
+#source src/southbridge/winbond/Kconfig
diff --git a/src/southbridge/Makefile.inc b/src/southbridge/Makefile.inc
new file mode 100644
index 0000000..8f795a2
--- /dev/null
+++ b/src/southbridge/Makefile.inc
@@ -0,0 +1,8 @@
+#subdirs-y += amd
+#subdirs-y += broadcom
+subdirs-y += intel
+#subdirs-y += nvidia
+#subdirs-y += ricoh
+#subdirs-y += sis
+#subdirs-y += via
+#subdirs-y += winbond
diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig
new file mode 100644
index 0000000..d451deb
--- /dev/null
+++ b/src/southbridge/amd/Kconfig
@@ -0,0 +1,10 @@
+source src/southbridge/amd/amd8111/Kconfig
+source src/southbridge/amd/amd8131/Kconfig
+source src/southbridge/amd/amd8131-disable/Kconfig
+source src/southbridge/amd/amd8132/Kconfig
+source src/southbridge/amd/amd8151/Kconfig
+source src/southbridge/amd/cs5530/Kconfig
+source src/southbridge/amd/cs5535/Kconfig
+source src/southbridge/amd/cs5536/Kconfig
+source src/southbridge/amd/rs690/Kconfig
+source src/southbridge/amd/sb600/Kconfig
diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
new file mode 100644
index 0000000..caf5e42
--- /dev/null
+++ b/src/southbridge/amd/Makefile.inc
@@ -0,0 +1,11 @@
+subdirs-$(SOUTHBRIDGE_AMD_AMD8111) += amd8111
+subdirs-$(SOUTHBRIDGE_AMD_AMD8131) += amd8131
+subdirs-$(SOUTHBRIDGE_AMD_AMD8112) += amd8132
+subdirs-$(SOUTHBRIDGE_AMD_AMD8151) += amd8151
+subdirs-$(SOUTHBRIDGE_AMD_RS690) += rs690
+subdirs-$(SOUTHBRIDGE_AMD_SB600) += sb600
+
+subdirs-$(SOUTHBRIDGE_AMD_CS5530) += cs5530
+subdirs-$(SOUTHBRIDGE_AMD_CS5535) += cs5535
+subdirs-$(SOUTHBRIDGE_AMD_CS5536) += cs5536
+
diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig
new file mode 100644
index 0000000..f0e3b1d
--- /dev/null
+++ b/src/southbridge/amd/amd8111/Kconfig
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config SOUTHBRIDGE_AMD_AMD8111
+ bool
+ default n
+
diff --git a/src/southbridge/broadcom/Kconfig b/src/southbridge/broadcom/Kconfig
new file mode 100644
index 0000000..38ff222
--- /dev/null
+++ b/src/southbridge/broadcom/Kconfig
@@ -0,0 +1,3 @@
+source src/southbridge/broadcom/bcm21000/Kconfig
+source src/southbridge/broadcom/bcm5780/Kconfig
+source src/southbridge/broadcom/bcm5785/Kconfig
diff --git a/src/southbridge/broadcom/Makefile.inc b/src/southbridge/broadcom/Makefile.inc
new file mode 100644
index 0000000..e928b36
--- /dev/null
+++ b/src/southbridge/broadcom/Makefile.inc
@@ -0,0 +1,4 @@
+subdirs-y += bcm21000
+subdirs-y += bcm5780
+subdirs-y += bcm5785
+
diff --git a/src/southbridge/intel/Kconfig b/src/southbridge/intel/Kconfig
new file mode 100644
index 0000000..25adf84
--- /dev/null
+++ b/src/southbridge/intel/Kconfig
@@ -0,0 +1,10 @@
+#source src/southbridge/intel/esb6300/Kconfig
+#source src/southbridge/intel/i3100/Kconfig
+source src/southbridge/intel/i82371eb/Kconfig
+#source src/southbridge/intel/i82801ca/Kconfig
+#source src/southbridge/intel/i82801dbm/Kconfig
+#source src/southbridge/intel/i82801er/Kconfig
+source src/southbridge/intel/i82801gx/Kconfig
+source src/southbridge/intel/i82801xx/Kconfig
+#source src/southbridge/intel/i82870/Kconfig
+#source src/southbridge/intel/pxhd/Kconfig
diff --git a/src/southbridge/intel/Makefile.inc b/src/southbridge/intel/Makefile.inc
new file mode 100644
index 0000000..d69f0ab
--- /dev/null
+++ b/src/southbridge/intel/Makefile.inc
@@ -0,0 +1,11 @@
+#subdirs-y += esb6300
+#subdirs-y += i3100
+subdirs-y += i82371eb
+#subdirs-y += i82801ca
+#subdirs-y += i82801dbm
+#subdirs-y += i82801er
+subdirs-y += i82801gx
+subdirs-y += i82801xx
+#subdirs-y += i82870
+#subdirs-y += pxhd
+
diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig
new file mode 100644
index 0000000..e1c2044
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/Kconfig
@@ -0,0 +1,3 @@
+config SOUTHBRIDGE_INTEL_I82371EB
+ boolean
+
diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc
new file mode 100644
index 0000000..1ddd4c9
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/Makefile.inc
@@ -0,0 +1,27 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_isa.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_ide.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_usb.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_smbus.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_reset.o
+
+#initobj-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_early_rom.o
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
new file mode 100644
index 0000000..111c561
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config SOUTHBRIDGE_INTEL_I82801GX
+ bool
+ default n
+
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc
new file mode 100644
index 0000000..387ed10
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/Makefile.inc
@@ -0,0 +1,40 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_ac97.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_azalia.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_ide.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_lpc.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_nic.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_pci.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_pcie.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_sata.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_smbus.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_usb.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_usb_ehci.o
+
+object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_reset.o
+object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_watchdog.o
+
+# arg. How does the linux kconfig handle compound conditionals?
+ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
+ object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_smi.o
+ smmobj-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx_smihandler.o
+endif
diff --git a/src/southbridge/intel/i82801xx/Kconfig b/src/southbridge/intel/i82801xx/Kconfig
new file mode 100644
index 0000000..ce4ab30
--- /dev/null
+++ b/src/southbridge/intel/i82801xx/Kconfig
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config SOUTHBRIDGE_INTEL_I82801XX
+ bool
+ default n
+
diff --git a/src/southbridge/intel/i82801xx/Makefile.inc b/src/southbridge/intel/i82801xx/Makefile.inc
new file mode 100644
index 0000000..337b4e8
--- /dev/null
+++ b/src/southbridge/intel/i82801xx/Makefile.inc
@@ -0,0 +1,36 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_ac97.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_ide.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_lpc.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_nic.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_pci.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_sata.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_smbus.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_usb.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_usb_ehci.o
+
+object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_reset.o
+object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_watchdog.o
+
+# TODO: What about cmos_failover.c?
+
diff --git a/src/southbridge/nvidia/Kconfig b/src/southbridge/nvidia/Kconfig
new file mode 100644
index 0000000..59fc8ed
--- /dev/null
+++ b/src/southbridge/nvidia/Kconfig
@@ -0,0 +1,2 @@
+source src/southbridge/nvidia/ck804/Kconfig
+source src/southbridge/nvidia/mcp55/Kconfig
diff --git a/src/southbridge/nvidia/Makefile.inc b/src/southbridge/nvidia/Makefile.inc
new file mode 100644
index 0000000..cb3bc70
--- /dev/null
+++ b/src/southbridge/nvidia/Makefile.inc
@@ -0,0 +1,3 @@
+subdirs-y += ck804
+subdirs-y += mcp55
+
diff --git a/src/southbridge/ricoh/Kconfig b/src/southbridge/ricoh/Kconfig
new file mode 100644
index 0000000..2d25e9e
--- /dev/null
+++ b/src/southbridge/ricoh/Kconfig
@@ -0,0 +1 @@
+source src/southbridge/ricoh/rl5c476/Kconfig
diff --git a/src/southbridge/ricoh/Makefile.inc b/src/southbridge/ricoh/Makefile.inc
new file mode 100644
index 0000000..81051c9
--- /dev/null
+++ b/src/southbridge/ricoh/Makefile.inc
@@ -0,0 +1 @@
+subdirs-y += rl5c476
diff --git a/src/southbridge/sis/Kconfig b/src/southbridge/sis/Kconfig
new file mode 100644
index 0000000..4d11384
--- /dev/null
+++ b/src/southbridge/sis/Kconfig
@@ -0,0 +1 @@
+source src/southbridge/sis/sis966/Kconfig
diff --git a/src/southbridge/sis/Makefile.inc b/src/southbridge/sis/Makefile.inc
new file mode 100644
index 0000000..741df1c
--- /dev/null
+++ b/src/southbridge/sis/Makefile.inc
@@ -0,0 +1,2 @@
+subdirs-y += sis966
+
diff --git a/src/southbridge/via/Kconfig b/src/southbridge/via/Kconfig
new file mode 100644
index 0000000..fb19cbc
--- /dev/null
+++ b/src/southbridge/via/Kconfig
@@ -0,0 +1,5 @@
+source src/southbridge/via/k8t890/Kconfig
+source src/southbridge/via/vt8231/Kconfig
+source src/southbridge/via/vt8235/Kconfig
+source src/southbridge/via/vt8237r/Kconfig
+source src/southbridge/via/vt82c686/Kconfig
diff --git a/src/southbridge/via/Makefile.inc b/src/southbridge/via/Makefile.inc
new file mode 100644
index 0000000..12357e9
--- /dev/null
+++ b/src/southbridge/via/Makefile.inc
@@ -0,0 +1,5 @@
+subdirs-y += k8t890
+subdirs-y += vt8231
+subdirs-y += vt8235
+subdirs-y += vt8237r
+subdirs-y += vt82c686
diff --git a/src/southbridge/winbond/Kconfig b/src/southbridge/winbond/Kconfig
new file mode 100644
index 0000000..9ca0c3e
--- /dev/null
+++ b/src/southbridge/winbond/Kconfig
@@ -0,0 +1 @@
+source src/southbridge/winbond/w83c553/Kconfig
diff --git a/src/southbridge/winbond/Makefile.inc b/src/southbridge/winbond/Makefile.inc
new file mode 100644
index 0000000..004313a
--- /dev/null
+++ b/src/southbridge/winbond/Makefile.inc
@@ -0,0 +1 @@
+subdirs-y += w83c553
diff --git a/src/superio/Kconfig b/src/superio/Kconfig
new file mode 100644
index 0000000..65ebf4a
--- /dev/null
+++ b/src/superio/Kconfig
@@ -0,0 +1,8 @@
+source src/superio/fintek/Kconfig
+source src/superio/intel/Kconfig
+source src/superio/ite/Kconfig
+source src/superio/nsc/Kconfig
+source src/superio/serverengines/Kconfig
+source src/superio/smsc/Kconfig
+source src/superio/via/Kconfig
+source src/superio/winbond/Kconfig
diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc
new file mode 100644
index 0000000..c6f0888
--- /dev/null
+++ b/src/superio/Makefile.inc
@@ -0,0 +1,10 @@
+
+subdirs-y += fintek
+subdirs-y += intel
+subdirs-y += ite
+subdirs-y += nsc
+#subdirs-y += serverengine
+subdirs-y += smsc
+subdirs-y += via
+subdirs-y += winbond
+
diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig
new file mode 100644
index 0000000..540e18e
--- /dev/null
+++ b/src/superio/fintek/Kconfig
@@ -0,0 +1,2 @@
+config SUPERIO_FINTEK_F71805F
+ bool
diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc
new file mode 100644
index 0000000..0d1ca79
--- /dev/null
+++ b/src/superio/fintek/Makefile.inc
@@ -0,0 +1 @@
+subdirs-y += f71805f
diff --git a/src/superio/fintek/f71805f/Makefile.inc b/src/superio/fintek/f71805f/Makefile.inc
new file mode 100644
index 0000000..8dc10a6
--- /dev/null
+++ b/src/superio/fintek/f71805f/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_FINTEK_F71805F) += superio.o
+
diff --git a/src/superio/intel/Kconfig b/src/superio/intel/Kconfig
new file mode 100644
index 0000000..39652b0
--- /dev/null
+++ b/src/superio/intel/Kconfig
@@ -0,0 +1,2 @@
+config SUPERIO_FINTEK_I3100
+ bool
diff --git a/src/superio/intel/Makefile.inc b/src/superio/intel/Makefile.inc
new file mode 100644
index 0000000..5416eea
--- /dev/null
+++ b/src/superio/intel/Makefile.inc
@@ -0,0 +1 @@
+subdirs-y += i3100
diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc
new file mode 100644
index 0000000..9cf0033
--- /dev/null
+++ b/src/superio/intel/i3100/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Arastra, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_INTEL_I3100) += superio.o
+
diff --git a/src/superio/ite/Kconfig b/src/superio/ite/Kconfig
new file mode 100644
index 0000000..0664981
--- /dev/null
+++ b/src/superio/ite/Kconfig
@@ -0,0 +1,14 @@
+config SUPERIO_ITE_IT8661F
+ bool
+config SUPERIO_ITE_IT8671F
+ bool
+config SUPERIO_ITE_IT8673F
+ bool
+config SUPERIO_ITE_IT8705F
+ bool
+config SUPERIO_ITE_IT8712F
+ bool
+config SUPERIO_ITE_IT8716F
+ bool
+config SUPERIO_ITE_IT8718F
+ bool
diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc
new file mode 100644
index 0000000..9e92ce0
--- /dev/null
+++ b/src/superio/ite/Makefile.inc
@@ -0,0 +1,7 @@
+subdirs-y += it8661f
+subdirs-y += it8671f
+subdirs-y += it8673f
+subdirs-y += it8705f
+subdirs-y += it8712f
+subdirs-y += it8716f
+subdirs-y += it8718f
diff --git a/src/superio/ite/it8661f/Makefile.inc b/src/superio/ite/it8661f/Makefile.inc
new file mode 100644
index 0000000..d37f3ea
--- /dev/null
+++ b/src/superio/ite/it8661f/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_ITE_IT8661F) += superio.o
+
diff --git a/src/superio/ite/it8671f/Makefile.inc b/src/superio/ite/it8671f/Makefile.inc
new file mode 100644
index 0000000..6f047ca
--- /dev/null
+++ b/src/superio/ite/it8671f/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_ITE_IT8671F) += superio.o
+
diff --git a/src/superio/ite/it8673f/Makefile.inc b/src/superio/ite/it8673f/Makefile.inc
new file mode 100644
index 0000000..4d89bce
--- /dev/null
+++ b/src/superio/ite/it8673f/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_ITE_IT8673F) += superio.o
+
diff --git a/src/superio/ite/it8705f/Makefile.inc b/src/superio/ite/it8705f/Makefile.inc
new file mode 100644
index 0000000..db495c9
--- /dev/null
+++ b/src/superio/ite/it8705f/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_ITE_IT8705F) += superio.o
+
diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc
new file mode 100644
index 0000000..7f293b4
--- /dev/null
+++ b/src/superio/ite/it8712f/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.o
+
diff --git a/src/superio/ite/it8716f/Makefile.inc b/src/superio/ite/it8716f/Makefile.inc
new file mode 100644
index 0000000..bf0a70c
--- /dev/null
+++ b/src/superio/ite/it8716f/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.o
+
diff --git a/src/superio/ite/it8718f/Makefile.inc b/src/superio/ite/it8718f/Makefile.inc
new file mode 100644
index 0000000..00ef744
--- /dev/null
+++ b/src/superio/ite/it8718f/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_ITE_IT8718F) += superio.o
+
diff --git a/src/superio/nsc/Kconfig b/src/superio/nsc/Kconfig
new file mode 100644
index 0000000..68a1df8
--- /dev/null
+++ b/src/superio/nsc/Kconfig
@@ -0,0 +1,18 @@
+config SUPERIO_NSC_PC8374
+ bool
+config SUPERIO_NSC_PC87309
+ bool
+config SUPERIO_NSC_PC87351
+ bool
+config SUPERIO_NSC_PC87360
+ bool
+config SUPERIO_NSC_PC87366
+ bool
+config SUPERIO_NSC_PC87417
+ bool
+config SUPERIO_NSC_PC87427
+ bool
+config SUPERIO_NSC_PC97307
+ bool
+config SUPERIO_NSC_PC97317
+ bool
diff --git a/src/superio/nsc/Makefile.inc b/src/superio/nsc/Makefile.inc
new file mode 100644
index 0000000..8cd0442
--- /dev/null
+++ b/src/superio/nsc/Makefile.inc
@@ -0,0 +1,9 @@
+subdirs-y += pc8374
+subdirs-y += pc87309
+subdirs-y += pc87351
+subdirs-y += pc87360
+subdirs-y += pc87366
+subdirs-y += pc87417
+subdirs-y += pc87427
+subdirs-y += pc97307
+subdirs-y += pc97317
diff --git a/src/superio/nsc/pc8374/Makefile.inc b/src/superio/nsc/pc8374/Makefile.inc
new file mode 100644
index 0000000..d001b57
--- /dev/null
+++ b/src/superio/nsc/pc8374/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC8374) += superio.o
diff --git a/src/superio/nsc/pc87309/Makefile.inc b/src/superio/nsc/pc87309/Makefile.inc
new file mode 100644
index 0000000..9fde44e
--- /dev/null
+++ b/src/superio/nsc/pc87309/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC87309) += superio.o
+
diff --git a/src/superio/nsc/pc87351/Makefile.inc b/src/superio/nsc/pc87351/Makefile.inc
new file mode 100644
index 0000000..93206adb
--- /dev/null
+++ b/src/superio/nsc/pc87351/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC87351) += superio.o
diff --git a/src/superio/nsc/pc87360/Makefile.inc b/src/superio/nsc/pc87360/Makefile.inc
new file mode 100644
index 0000000..0cb7abc
--- /dev/null
+++ b/src/superio/nsc/pc87360/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC87360) += superio.o
diff --git a/src/superio/nsc/pc87366/Makefile.inc b/src/superio/nsc/pc87366/Makefile.inc
new file mode 100644
index 0000000..7251d8c
--- /dev/null
+++ b/src/superio/nsc/pc87366/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC87366) += superio.o
diff --git a/src/superio/nsc/pc87417/Makefile.inc b/src/superio/nsc/pc87417/Makefile.inc
new file mode 100644
index 0000000..6572744
--- /dev/null
+++ b/src/superio/nsc/pc87417/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC87417) += superio.o
diff --git a/src/superio/nsc/pc87427/Makefile.inc b/src/superio/nsc/pc87427/Makefile.inc
new file mode 100644
index 0000000..a5e47ba
--- /dev/null
+++ b/src/superio/nsc/pc87427/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC87427) += superio.o
diff --git a/src/superio/nsc/pc97307/Makefile.inc b/src/superio/nsc/pc97307/Makefile.inc
new file mode 100644
index 0000000..548504c
--- /dev/null
+++ b/src/superio/nsc/pc97307/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC97307) += superio.o
diff --git a/src/superio/nsc/pc97317/Makefile.inc b/src/superio/nsc/pc97317/Makefile.inc
new file mode 100644
index 0000000..feda33b
--- /dev/null
+++ b/src/superio/nsc/pc97317/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC97317) += superio.o
diff --git a/src/superio/serverengines/Kconfig b/src/superio/serverengines/Kconfig
new file mode 100644
index 0000000..5fb2304
--- /dev/null
+++ b/src/superio/serverengines/Kconfig
@@ -0,0 +1,2 @@
+config SERVERENGINES_ITE_PILOT
+ bool
diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig
new file mode 100644
index 0000000..5cbd0d1
--- /dev/null
+++ b/src/superio/smsc/Kconfig
@@ -0,0 +1,12 @@
+config SUPERIO_SMCSC_FDC37M60X
+ bool
+config SUPERIO_SMCSC_LPC47B272
+ bool
+config SUPERIO_SMCSC_LPC47B397
+ bool
+config SUPERIO_SMCSC_LPC47M10X
+ bool
+config SUPERIO_SMCSC_LPC47N217
+ bool
+config SUPERIO_SMCSC_SMSCSUPERIO
+ bool
diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc
new file mode 100644
index 0000000..db59651
--- /dev/null
+++ b/src/superio/smsc/Makefile.inc
@@ -0,0 +1,6 @@
+subdirs-y += fdc37m60x
+subdirs-y += lpc47b272
+subdirs-y += lpc47b397
+subdirs-y += lpc47m10x
+subdirs-y += lpc47n217
+subdirs-y += smscsuperio
diff --git a/src/superio/smsc/fdc37m60x/Makefile.inc b/src/superio/smsc/fdc37m60x/Makefile.inc
new file mode 100644
index 0000000..a2bf480
--- /dev/null
+++ b/src/superio/smsc/fdc37m60x/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_SMSC_FDC37M60X) += superio.o
+
diff --git a/src/superio/smsc/lpc47b272/Makefile.inc b/src/superio/smsc/lpc47b272/Makefile.inc
new file mode 100644
index 0000000..031d5df
--- /dev/null
+++ b/src/superio/smsc/lpc47b272/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2005 Digital Design Corporation
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_SMSC_DEVICE) += superio.o
+
diff --git a/src/superio/smsc/lpc47b397/Makefile.inc b/src/superio/smsc/lpc47b397/Makefile.inc
new file mode 100644
index 0000000..ff7f93f
--- /dev/null
+++ b/src/superio/smsc/lpc47b397/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.o
diff --git a/src/superio/smsc/lpc47m10x/Makefile.inc b/src/superio/smsc/lpc47m10x/Makefile.inc
new file mode 100644
index 0000000..47cbf6b
--- /dev/null
+++ b/src/superio/smsc/lpc47m10x/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += superio.o
diff --git a/src/superio/smsc/lpc47n217/Makefile.inc b/src/superio/smsc/lpc47n217/Makefile.inc
new file mode 100644
index 0000000..edde762
--- /dev/null
+++ b/src/superio/smsc/lpc47n217/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2005 Digital Design Corporation
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_SMSC_LPC47N217) += superio.o
diff --git a/src/superio/smsc/smscsuperio/Makefile.inc b/src/superio/smsc/smscsuperio/Makefile.inc
new file mode 100644
index 0000000..f5d42787
--- /dev/null
+++ b/src/superio/smsc/smscsuperio/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) += superio.o
+
diff --git a/src/superio/via/Kconfig b/src/superio/via/Kconfig
new file mode 100644
index 0000000..36b7f47
--- /dev/null
+++ b/src/superio/via/Kconfig
@@ -0,0 +1,2 @@
+config SUPERIO_VIA_VT1211
+ bool
diff --git a/src/superio/via/Makefile.inc b/src/superio/via/Makefile.inc
new file mode 100644
index 0000000..350101a
--- /dev/null
+++ b/src/superio/via/Makefile.inc
@@ -0,0 +1 @@
+subdirs-y += vt1211
diff --git a/src/superio/via/vt1211/Makefile.inc b/src/superio/via/vt1211/Makefile.inc
new file mode 100644
index 0000000..827c9f9
--- /dev/null
+++ b/src/superio/via/vt1211/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_VIA_VT1211) += vt1211.o
diff --git a/src/superio/winbond/Kconfig b/src/superio/winbond/Kconfig
new file mode 100644
index 0000000..24825a7
--- /dev/null
+++ b/src/superio/winbond/Kconfig
@@ -0,0 +1,18 @@
+config SUPERIO_WINBOND_W83627DHG
+ boolean
+config SUPERIO_WINBOND_W83627EHG
+ boolean
+config SUPERIO_WINBOND_W83627HF
+ boolean
+config SUPERIO_WINBOND_W83627THF
+ boolean
+config SUPERIO_WINBOND_W83627THG
+ boolean
+config SUPERIO_WINBOND_W83627UHG
+ boolean
+config SUPERIO_WINBOND_W83697HF
+ boolean
+config SUPERIO_WINBOND_W83977F
+ boolean
+config SUPERIO_WINBOND_W83977TF
+ boolean
diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc
new file mode 100644
index 0000000..e8dbad9
--- /dev/null
+++ b/src/superio/winbond/Makefile.inc
@@ -0,0 +1,9 @@
+subdirs-y += w83627dhg
+subdirs-y += w83627ehg
+subdirs-y += w83627hf
+subdirs-y += w83627thf
+subdirs-y += w83627thg
+subdirs-y += w83627uhg
+subdirs-y += w83697hf
+subdirs-y += w83977f
+subdirs-y += w83977tf
diff --git a/src/superio/winbond/w83627dhg/Makefile.inc b/src/superio/winbond/w83627dhg/Makefile.inc
new file mode 100644
index 0000000..168d803
--- /dev/null
+++ b/src/superio/winbond/w83627dhg/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += superio.o
+
diff --git a/src/superio/winbond/w83627ehg/Makefile.inc b/src/superio/winbond/w83627ehg/Makefile.inc
new file mode 100644
index 0000000..d52c5eb
--- /dev/null
+++ b/src/superio/winbond/w83627ehg/Makefile.inc
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += superio.o
+
diff --git a/src/superio/winbond/w83627hf/Makefile.inc b/src/superio/winbond/w83627hf/Makefile.inc
new file mode 100644
index 0000000..7f393c1
--- /dev/null
+++ b/src/superio/winbond/w83627hf/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83627HF) += superio.o
diff --git a/src/superio/winbond/w83627thf/Makefile.inc b/src/superio/winbond/w83627thf/Makefile.inc
new file mode 100644
index 0000000..2c74921
--- /dev/null
+++ b/src/superio/winbond/w83627thf/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83627THF) += superio.o
diff --git a/src/superio/winbond/w83627thg/Makefile.inc b/src/superio/winbond/w83627thg/Makefile.inc
new file mode 100644
index 0000000..ea60c2f
--- /dev/null
+++ b/src/superio/winbond/w83627thg/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83627THG) += superio.o
diff --git a/src/superio/winbond/w83627uhg/Makefile.inc b/src/superio/winbond/w83627uhg/Makefile.inc
new file mode 100644
index 0000000..58dd621
--- /dev/null
+++ b/src/superio/winbond/w83627uhg/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Dynon Avionics
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 $
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83627UHG) += superio.o
diff --git a/src/superio/winbond/w83697hf/Makefile.inc b/src/superio/winbond/w83697hf/Makefile.inc
new file mode 100644
index 0000000..72fb90d
--- /dev/null
+++ b/src/superio/winbond/w83697hf/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Sean Nelson <snelson@nmt.edu>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83697HF) += superio.o
diff --git a/src/superio/winbond/w83977f/Makefile.inc b/src/superio/winbond/w83977f/Makefile.inc
new file mode 100644
index 0000000..7f394cb
--- /dev/null
+++ b/src/superio/winbond/w83977f/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83977F) += superio.o
diff --git a/src/superio/winbond/w83977tf/Makefile.inc b/src/superio/winbond/w83977tf/Makefile.inc
new file mode 100644
index 0000000..07fc338
--- /dev/null
+++ b/src/superio/winbond/w83977tf/Makefile.inc
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83977TF) += superio.o