mb/google/hatch: Switch USB2 port1 and port3 on Noibat

Switch USB2 port1 and port3 for noibat due to circuit change.

BUG=b:154585046,b:156429564
BRANCH=none
TEST=none

Change-Id: I711038624f3efe397be73c29a940b3e17802598f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42296
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb
index 050a75a..ed5fab2 100644
--- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb
@@ -21,9 +21,6 @@
 	}"
 
 	# USB configuration
-	# NOTE: This only applies to Puff,
-	# usb2_ports[1] and usb2_ports[3] were swapped on
-	# reference schematics after Puff has been built.
 	register "usb2_ports[0]" = "{
 		.enable = 1,
 		.ocpin = OC2,
@@ -32,7 +29,14 @@
 		.pre_emp_bias  = USB2_BIAS_11P25MV,
 		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
 	}" # Type-A Port 2
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
+	register "usb2_ports[1]" = "{
+		.enable = 1,
+		.ocpin = OC1,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_PRE_EMP_ON,
+		.pre_emp_bias  = USB2_BIAS_28P15MV,
+		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
+	}" # Type-A Port 1
 	register "usb2_ports[2]" = "{
 		.enable = 1,
 		.ocpin = OC3,
@@ -41,14 +45,7 @@
 		.pre_emp_bias  = USB2_BIAS_28P15MV,
 		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
 	}" # Type-A Port 3
-	register "usb2_ports[3]" = "{
-		.enable = 1,
-		.ocpin = OC1,
-		.tx_bias = USB2_BIAS_0MV,
-		.tx_emp_enable = USB2_PRE_EMP_ON,
-		.pre_emp_bias  = USB2_BIAS_28P15MV,
-		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
-	}" # Type-A Port 1
+	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
 	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[5]" = "{
 		.enable = 1,
@@ -125,7 +122,7 @@
 	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
 	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515"
 
-	# Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them.
+	# Intel HDA - disable I2S Audio SSP1 and DMIC0 as noibat variant does not have them.
 	register "PchHdaAudioLinkSsp1" = "0"
 	register "PchHdaAudioLinkDmic0" = "0"