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review.coreboot.org / coreboot / ad78553f5d2456f1a7c22f9e9694b8c3c7e30693
commitad78553f5d2456f1a7c22f9e9694b8c3c7e30693[log] [tgz]
authorFurquan Shaikh <furquan@google.com>Thu Jun 11 13:46:09 2020 -0700
committerFurquan Shaikh <furquan@google.com>Sun Jun 14 00:47:15 2020 +0000
tree237e685e6cf3cfe4558e3645cdd1a676b2534151
parent80c555d7a82e6b2e4b8d2e46cbd5b21220b16116 [diff]
soc/amd/picasso/acpi: Add a wrapper method WAL1 for calling ALIB function 1

ALIB function 1 needs to be called every time there is a change in
AC/DC state of the system. This change adds a wrapper method that can
be called by PNOT (method to notify system power state change) to
report to ALIB that system power state has changed i.e. AC <-> DC.

Additionally, this change drops the call to ALIB from _INI method
since the PWRS object might not be initialized correctly at that
point. Instead EC makes a call to PNOT when PWRS is initialized.

This wrapper also fixes the value of power state being passed into
ALIB. ALIB expects 0 = AC and 1 = DC. On the other hand, PWRS reports
1 as AC and 0 as DC. WAL1() takes care of inverting the PWRS state
before passing into ALIB.

BUG=b:157752693
TEST=Verified that WAL1() gets called on AC connect/disconnect.

Steps followed:
$ echo 1 > /sys/module/acpi/parameters/aml_debug_output
$ dmesg -w | grep ACPI
[   76.306947] ACPI Debug:  "EC: AC DISCONNECTED"
[   76.307064] ACPI Debug:  "ALIB call: func 1 params 0x03 0x00 0x01"
[   82.264946] ACPI Debug:  "EC: GOT PD EVENT"
[   82.539833] ACPI Debug:  "EC: GOT PD EVENT"
[   82.753721] ACPI Debug:  "EC: GOT PD EVENT"
[   82.843676] ACPI Debug:  "EC: GOT PD EVENT"
[   82.970596] ACPI Debug:  "EC: AC CONNECTED"
[   82.970659] ACPI Debug:  "ALIB call: func 1 params 0x03 0x00 0x00"
[   83.047598] ACPI Debug:  "EC: GOT PD EVENT"
[   84.804733] ACPI Debug:  "EC: GOT PD EVENT"
[   86.317934] ACPI Debug:  "EC: GOT PD EVENT"
[   86.385920] ACPI Debug:  "EC: GOT PD EVENT"
[   86.515830] ACPI Debug:  "EC: AC DISCONNECTED"
[   86.515922] ACPI Debug:  "ALIB call: func 1 params 0x03 0x00 0x01"
[   90.089062] ACPI Debug:  "EC: GOT PD EVENT"
[   90.357914] ACPI Debug:  "EC: GOT PD EVENT"
[   90.573812] ACPI Debug:  "EC: GOT PD EVENT"
[   90.662744] ACPI Debug:  "EC: GOT PD EVENT"
[   90.788706] ACPI Debug:  "EC: AC CONNECTED"
[   90.788835] ACPI Debug:  "ALIB call: func 1 params 0x03 0x00 0x00"
[   90.865675] ACPI Debug:  "EC: GOT PD EVENT"
[   92.621793] ACPI Debug:  "EC: GOT PD EVENT"

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I1f2ade28ca35378ebf4647d8df3d2ea4d0b08096
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2 files changed
tree: 237e685e6cf3cfe4558e3645cdd1a676b2534151
  1. 3rdparty/
  2. configs/
  3. Documentation/
  4. LICENSES/
  5. payloads/
  6. src/
  7. tests/
  8. util/
  9. .checkpatch.conf
  10. .clang-format
  11. .editorconfig
  12. .gitignore
  13. .gitmodules
  14. .gitreview
  15. AUTHORS
  16. COPYING
  17. gnat.adc
  18. MAINTAINERS
  19. Makefile
  20. Makefile.inc
  21. README.md
  22. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.