| Paul Menzel | 2628571 | 2017-04-17 10:57:51 +0200 | [diff] [blame] | 1 | # This image was built using git revision 43673dd4b9c87cd5d44af7caa29e9d3cf06c82f2 |
| 2 | CONFIG_LOCALVERSION="" |
| 3 | CONFIG_CBFS_PREFIX="fallback" |
| 4 | CONFIG_COMPILER_GCC=y |
| 5 | CONFIG_CCACHE=y |
| 6 | CONFIG_COMPRESS_RAMSTAGE=y |
| 7 | CONFIG_INCLUDE_CONFIG_FILE=y |
| 8 | CONFIG_EARLY_CBMEM_INIT=y |
| 9 | CONFIG_DYNAMIC_CBMEM=y |
| 10 | CONFIG_COLLECT_TIMESTAMPS=y |
| 11 | CONFIG_VENDOR_INTEL=y |
| 12 | CONFIG_BOARD_SPECIFIC_OPTIONS=y |
| 13 | CONFIG_MAINBOARD_DIR="intel/d945gclf" |
| 14 | CONFIG_MAINBOARD_PART_NUMBER="D945GCLF" |
| 15 | CONFIG_IRQ_SLOT_COUNT=18 |
| 16 | CONFIG_MAINBOARD_VENDOR="Intel" |
| 17 | CONFIG_MAX_CPUS=4 |
| 18 | CONFIG_RAMTOP=0x200000 |
| 19 | CONFIG_HEAP_SIZE=0x4000 |
| 20 | CONFIG_RAMBASE=0x100000 |
| 21 | CONFIG_VGA_BIOS_ID="8086,27a2" |
| 22 | CONFIG_DRIVERS_PS2_KEYBOARD=y |
| 23 | CONFIG_DCACHE_RAM_BASE=0xffaf8000 |
| 24 | CONFIG_DCACHE_RAM_SIZE=0x8000 |
| 25 | CONFIG_ACPI_SSDTX_NUM=0 |
| 26 | CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 |
| 27 | CONFIG_UART_FOR_CONSOLE=0 |
| 28 | CONFIG_ID_SECTION_OFFSET=0x80 |
| 29 | CONFIG_STACK_SIZE=0x1000 |
| 30 | CONFIG_BOARD_INTEL_D945GCLF=y |
| 31 | CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 |
| 32 | CONFIG_CBFS_SIZE=0x80000 |
| 33 | CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel" |
| 34 | CONFIG_MAINBOARD_VERSION="1.0" |
| 35 | CONFIG_CPU_ADDR_BITS=32 |
| 36 | CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 |
| 37 | CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 |
| 38 | CONFIG_BOARD_ROMSIZE_KB_512=y |
| 39 | CONFIG_COREBOOT_ROMSIZE_KB_512=y |
| 40 | CONFIG_COREBOOT_ROMSIZE_KB=512 |
| 41 | CONFIG_ROM_SIZE=0x80000 |
| 42 | CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" |
| 43 | CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF" |
| 44 | CONFIG_ARCH_X86=y |
| 45 | CONFIG_ARCH_BOOTBLOCK_X86_32=y |
| 46 | CONFIG_ARCH_ROMSTAGE_X86_32=y |
| 47 | CONFIG_ARCH_RAMSTAGE_X86_32=y |
| 48 | CONFIG_AP_IN_SIPI_WAIT=y |
| 49 | CONFIG_SIPI_VECTOR_IN_ROM=y |
| 50 | CONFIG_NUM_IPI_STARTS=2 |
| 51 | CONFIG_PC80_SYSTEM=y |
| 52 | CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" |
| 53 | CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" |
| 54 | CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y |
| 55 | CONFIG_HPET_ADDRESS=0xfed00000 |
| 56 | CONFIG_BOOTBLOCK_SIMPLE=y |
| 57 | CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" |
| 58 | CONFIG_SOCKET_SPECIFIC_OPTIONS=y |
| 59 | CONFIG_XIP_ROM_SIZE=0x10000 |
| 60 | CONFIG_CPU_INTEL_MODEL_106CX=y |
| 61 | CONFIG_SMM_TSEG_SIZE=0 |
| 62 | CONFIG_SSE2=y |
| 63 | CONFIG_CPU_INTEL_SOCKET_441=y |
| 64 | CONFIG_UDELAY_LAPIC=y |
| 65 | CONFIG_LAPIC_MONOTONIC_TIMER=y |
| 66 | CONFIG_TSC_SYNC_MFENCE=y |
| 67 | CONFIG_LOGICAL_CPUS=y |
| 68 | CONFIG_CACHE_AS_RAM=y |
| 69 | CONFIG_SMP=y |
| 70 | CONFIG_AP_SIPI_VECTOR=0xfffff000 |
| 71 | CONFIG_MMX=y |
| 72 | CONFIG_SSE=y |
| 73 | CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y |
| 74 | CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD=y |
| 75 | CONFIG_CPU_MICROCODE_CBFS_GENERATE=y |
| 76 | CONFIG_VIDEO_MB=0 |
| 77 | CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y |
| 78 | CONFIG_NORTHBRIDGE_INTEL_I945=y |
| 79 | CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y |
| 80 | CONFIG_CHANNEL_XOR_RANDOMIZATION=y |
| 81 | CONFIG_CHECK_SLFRCS_ON_RESUME=y |
| 82 | CONFIG_HPET_MIN_TICKS=0x80 |
| 83 | CONFIG_MAX_PIRQ_LINKS=4 |
| 84 | CONFIG_EHCI_BAR=0xfef00000 |
| 85 | CONFIG_SOUTHBRIDGE_INTEL_COMMON=y |
| 86 | CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y |
| 87 | CONFIG_SUPERIO_SMSC_LPC47M15X=y |
| 88 | CONFIG_PCI=y |
| 89 | CONFIG_PCIX_PLUGIN_SUPPORT=y |
| 90 | CONFIG_PCIEXP_PLUGIN_SUPPORT=y |
| 91 | CONFIG_AGP_PLUGIN_SUPPORT=y |
| 92 | CONFIG_CARDBUS_PLUGIN_SUPPORT=y |
| 93 | CONFIG_PCI_BUS_SEGN_BITS=0 |
| 94 | CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 |
| 95 | CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 |
| 96 | CONFIG_DRIVERS_UART=y |
| 97 | CONFIG_DRIVERS_UART_8250IO=y |
| 98 | CONFIG_HAVE_USBDEBUG=y |
| 99 | CONFIG_MMCONF_SUPPORT_DEFAULT=y |
| 100 | CONFIG_MMCONF_SUPPORT=y |
| 101 | CONFIG_SQUELCH_EARLY_SMP=y |
| 102 | CONFIG_CONSOLE_SERIAL=y |
| 103 | CONFIG_TTYS0_BASE=0x3f8 |
| 104 | CONFIG_CONSOLE_SERIAL_115200=y |
| 105 | CONFIG_TTYS0_BAUD=115200 |
| 106 | CONFIG_TTYS0_LCS=3 |
| 107 | CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y |
| 108 | CONFIG_NO_POST=y |
| 109 | CONFIG_HAVE_ACPI_RESUME=y |
| 110 | CONFIG_HAVE_HARD_RESET=y |
| 111 | CONFIG_HAVE_MONOTONIC_TIMER=y |
| 112 | CONFIG_HAVE_OPTION_TABLE=y |
| 113 | CONFIG_HAVE_SMI_HANDLER=y |
| 114 | CONFIG_IOAPIC=y |
| 115 | CONFIG_USE_WATCHDOG_ON_BOOT=y |
| 116 | CONFIG_HAVE_ACPI_TABLES=y |
| 117 | CONFIG_HAVE_MP_TABLE=y |
| 118 | CONFIG_HAVE_PIRQ_TABLE=y |
| 119 | CONFIG_GENERATE_ACPI_TABLES=y |
| 120 | CONFIG_GENERATE_MP_TABLE=y |
| 121 | CONFIG_GENERATE_PIRQ_TABLE=y |
| 122 | CONFIG_GENERATE_SMBIOS_TABLES=y |
| 123 | CONFIG_PAYLOAD_SEABIOS=y |
| 124 | CONFIG_SEABIOS_STABLE=y |
| 125 | CONFIG_PAYLOAD_FILE="$(obj)/seabios/out/bios.bin.elf" |
| 126 | CONFIG_COMPRESSED_PAYLOAD_LZMA=y |
| 127 | CONFIG_HAVE_DEBUG_RAM_SETUP=y |
| 128 | CONFIG_DEBUG_SMI=y |
| 129 | CONFIG_DEBUG_SMM_RELOCATION=y |
| 130 | CONFIG_WARNINGS_ARE_ERRORS=y |
| 131 | CONFIG_REG_SCRIPT=y |
| 132 | CONFIG_MAX_REBOOT_CNT=3 |