Michał Kopeć | fa65082 | 2019-12-16 04:26:51 +0100 | [diff] [blame] | 1 | *** Pre-CBMEM romstage console overflowed, log truncated! *** |
| 2 | atible clock, CAS pair. |
| 3 | Selected DRAM frequency: 800 MHz |
| 4 | Selected CAS latency : 11T |
| 5 | PLL busy... done in 30 us |
| 6 | MCU frequency is set at : 800 MHz |
| 7 | Done dimm mapping |
| 8 | Update PCI-E configuration space: |
| 9 | PCI(0, 0, 0)[a0] = 0 |
| 10 | PCI(0, 0, 0)[a4] = 2 |
| 11 | PCI(0, 0, 0)[bc] = c2a00000 |
| 12 | PCI(0, 0, 0)[a8] = 3d600000 |
| 13 | PCI(0, 0, 0)[ac] = 2 |
| 14 | PCI(0, 0, 0)[b8] = c0000000 |
| 15 | PCI(0, 0, 0)[b0] = c0a00000 |
| 16 | PCI(0, 0, 0)[b4] = c0800000 |
| 17 | Done memory map |
| 18 | Done io registers |
| 19 | t123: 1767, 6000, 7620 |
| 20 | ME: FW Partition Table : OK |
| 21 | ME: Bringup Loader Failure : NO |
| 22 | ME: Firmware Init Complete : NO |
| 23 | ME: Manufacturing Mode : YES |
| 24 | ME: Boot Options Present : NO |
| 25 | ME: Update In Progress : NO |
| 26 | ME: Current Working State : Initializing |
| 27 | ME: Current Operation State : Bring up |
| 28 | ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| 29 | ME: Error Code : No Error |
| 30 | ME: Progress Phase : BUP Phase |
| 31 | ME: Power Management Event : Pseudo-global reset |
| 32 | ME: Progress Phase State : Check to see if straps say ME DISABLED |
| 33 | ME: Wrong mode : 2 |
| 34 | ME: FWS2: 0x160a0140 |
| 35 | ME: Bist in progress: 0x0 |
| 36 | ME: ICC Status : 0x0 |
| 37 | ME: Invoke MEBx : 0x0 |
| 38 | ME: CPU replaced : 0x0 |
| 39 | ME: MBP ready : 0x0 |
| 40 | ME: MFS failure : 0x1 |
| 41 | ME: Warm reset req : 0x0 |
| 42 | ME: CPU repl valid : 0x1 |
| 43 | ME: (Reserved) : 0x0 |
| 44 | ME: FW update req : 0x0 |
| 45 | ME: (Reserved) : 0x0 |
| 46 | ME: Current state : 0xa |
| 47 | ME: Current PM event: 0x6 |
| 48 | ME: Progress code : 0x1 |
| 49 | PASSED! Tell ME that DRAM is ready |
| 50 | ME: ME is reporting as disabled, so not waiting for a response. |
| 51 | ME: FWS2: 0x160a0140 |
| 52 | ME: Bist in progress: 0x0 |
| 53 | ME: ICC Status : 0x0 |
| 54 | ME: Invoke MEBx : 0x0 |
| 55 | ME: CPU replaced : 0x0 |
| 56 | ME: MBP ready : 0x0 |
| 57 | ME: MFS failure : 0x1 |
| 58 | ME: Warm reset req : 0x0 |
| 59 | ME: CPU repl valid : 0x1 |
| 60 | ME: (Reserved) : 0x0 |
| 61 | ME: FW update req : 0x0 |
| 62 | ME: (Reserved) : 0x0 |
| 63 | ME: Current state : 0xa |
| 64 | ME: Current PM event: 0x6 |
| 65 | ME: Progress code : 0x1 |
| 66 | ME: Requested BIOS Action: No DID Ack received |
| 67 | ME: FW Partition Table : OK |
| 68 | ME: Bringup Loader Failure : NO |
| 69 | ME: Firmware Init Complete : NO |
| 70 | ME: Manufacturing Mode : YES |
| 71 | ME: Boot Options Present : NO |
| 72 | ME: Update In Progress : NO |
| 73 | ME: Current Working State : Initializing |
| 74 | ME: Current Operation State : Bring up |
| 75 | ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| 76 | ME: Error Code : No Error |
| 77 | ME: Progress Phase : BUP Phase |
| 78 | ME: Power Management Event : Pseudo-global reset |
| 79 | ME: Progress Phase State : Check to see if straps say ME DISABLED |
| 80 | memcfg DDR3 ref clock 133 MHz |
| 81 | memcfg DDR3 clock 1596 MHz |
| 82 | memcfg channel assignment: A: 0, B 1, C 2 |
| 83 | memcfg channel[0] config (00620010): |
| 84 | ECC inactive |
| 85 | enhanced interleave mode on |
| 86 | rank interleave on |
| 87 | DIMMA 4096 MB width x8 dual rank, selected |
| 88 | DIMMB 0 MB width x8 single rank |
| 89 | memcfg channel[1] config (00600010): |
| 90 | ECC inactive |
| 91 | enhanced interleave mode on |
| 92 | rank interleave on |
| 93 | DIMMA 4096 MB width x8 single rank, selected |
| 94 | DIMMB 0 MB width x8 single rank |
| 95 | CBMEM: |
| 96 | IMD: root @ 0xbffff000 254 entries. |
| 97 | IMD: root @ 0xbfffec00 62 entries. |
| 98 | External stage cache: |
| 99 | IMD: root @ 0xc03ff000 254 entries. |
| 100 | IMD: root @ 0xc03fec00 62 entries. |
| 101 | CBMEM entry for DIMM info: 0xbfffe920 |
| 102 | SMM Memory Map |
| 103 | SMRAM : 0xc0000000 0x800000 |
| 104 | Subregion 0: 0xc0000000 0x300000 |
| 105 | Subregion 1: 0xc0300000 0x100000 |
| 106 | Subregion 2: 0xc0400000 0x400000 |
| 107 | MTRR Range: Start=bf800000 End=c0000000 (Size 800000) |
| 108 | MTRR Range: Start=c0000000 End=c0800000 (Size 800000) |
| 109 | MTRR Range: Start=ff000000 End=0 (Size 1000000) |
| 110 | FMAP: area COREBOOT found @ 650200 (5963264 bytes) |
| 111 | CBFS: 'COREBOOT Locator' located CBFS at [650200:c00000) |
| 112 | CBFS: Locating 'fallback/postcar' |
| 113 | CBFS: Found @ offset 38480 size 4a38 |
| 114 | Decompressing stage fallback/postcar @ 0xbffd2fc0 (35408 bytes) |
| 115 | Loading module at 0xbffd3000 with entry 0xbffd3000. filesize: 0x4710 memsize: 0x8a10 |
| 116 | Processing 179 relocs. Offset value of 0xbdfd3000 |
| 117 | Accumulated console time in romstage 1 ms |
| 118 | |
| 119 | |
| 120 | coreboot-4.11-427-gb320bc5e0e Sun Dec 15 17:11:47 UTC 2019 postcar starting (log level: 7)... |
| 121 | FMAP: area COREBOOT found @ 650200 (5963264 bytes) |
| 122 | CBFS: 'COREBOOT Locator' located CBFS at [650200:c00000) |
| 123 | CBFS: Locating 'fallback/ramstage' |
| 124 | CBFS: Found @ offset 1a0c0 size 1cea5 |
| 125 | Decompressing stage fallback/ramstage @ 0xbff7efc0 (339192 bytes) |
| 126 | Loading module at 0xbff7f000 with entry 0xbff7f000. filesize: 0x3ddf8 memsize: 0x52cb8 |
| 127 | Processing 4120 relocs. Offset value of 0xbf17f000 |
| 128 | Accumulated console time in postcar 0 ms |
| 129 | |
| 130 | |
| 131 | coreboot-4.11-427-gb320bc5e0e Sun Dec 15 17:11:47 UTC 2019 ramstage starting (log level: 7)... |
| 132 | Normal boot. |
| 133 | BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0 |
| 134 | BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0 |
| 135 | Enumerating buses... |
| 136 | CPU_CLUSTER: 0 enabled |
| 137 | DOMAIN: 0000 enabled |
| 138 | PCI: pci_scan_bus for bus 00 |
| 139 | PCI: 00:00.0 [8086/0154] enabled |
| 140 | PCI: 00:01.0 [8086/0151] disabled |
| 141 | PCI: 00:02.0 [8086/0166] enabled |
| 142 | PCI: 00:04.0 [8086/0153] enabled |
| 143 | PCI: 00:14.0 [8086/1e31] enabled |
| 144 | PCI: 00:16.0 [8086/1e3a] enabled |
| 145 | PCI: 00:16.1: Disabling device |
| 146 | PCI: 00:16.2: Disabling device |
| 147 | PCI: 00:16.3: Disabling device |
| 148 | PCI: 00:19.0 [8086/1502] enabled |
| 149 | PCI: 00:1a.0 [8086/1e2d] enabled |
| 150 | PCI: 00:1b.0 [8086/1e20] enabled |
| 151 | PCH: PCIe Root Port coalescing is enabled |
| 152 | PCI: 00:1c.0 [8086/1e10] enabled |
| 153 | PCI: 00:1c.1 [8086/1e12] enabled |
| 154 | PCI: 00:1c.2 [8086/1e14] enabled |
| 155 | PCI: 00:1c.3: Disabling device |
| 156 | PCI: 00:1c.3 [8086/1e16] disabled |
| 157 | PCI: 00:1c.4: Disabling device |
| 158 | PCI: 00:1c.4: check set enabled |
| 159 | PCI: 00:1c.5: Disabling device |
| 160 | PCI: 00:1c.6: Disabling device |
| 161 | PCI: 00:1c.7: Disabling device |
| 162 | PCI: 00:1d.0 [8086/1e26] enabled |
| 163 | PCI: 00:1e.0: Disabling device |
| 164 | PCI: 00:1e.0 [8086/2448] disabled |
| 165 | PCI: 00:1f.0 [8086/1e55] enabled |
| 166 | PCI: 00:1f.2 [8086/1e01] enabled |
| 167 | PCI: 00:1f.3 [8086/1e22] enabled |
| 168 | PCI: 00:1f.5: Disabling device |
| 169 | PCI: 00:1f.5 [8086/1e09] disabled No operations |
| 170 | PCI: 00:1f.6 [8086/1e24] enabled |
| 171 | PCI: Leftover static devices: |
| 172 | PCI: 00:16.1 |
| 173 | PCI: 00:16.2 |
| 174 | PCI: 00:16.3 |
| 175 | PCI: 00:1c.4 |
| 176 | PCI: 00:1c.5 |
| 177 | PCI: 00:1c.6 |
| 178 | PCI: 00:1c.7 |
| 179 | PCI: Check your devicetree.cb. |
| 180 | PCI: pci_scan_bus for bus 01 |
| 181 | PCI: 01:00.0 [1180/e823] enabled |
| 182 | Enabling Common Clock Configuration |
| 183 | ASPM: Enabled L0s and L1 |
| 184 | Failed to enable LTR for dev = PCI: 01:00.0 |
| 185 | scan_bus: scanning of bus PCI: 00:1c.0 took 239 usecs |
| 186 | PCI: pci_scan_bus for bus 02 |
| 187 | PCI: 02:00.0 [8086/24f3] enabled |
| 188 | Enabling Common Clock Configuration |
| 189 | ASPM: Enabled L1 |
| 190 | scan_bus: scanning of bus PCI: 00:1c.1 took 261 usecs |
| 191 | PCI: pci_scan_bus for bus 03 |
| 192 | scan_bus: scanning of bus PCI: 00:1c.2 took 47 usecs |
| 193 | PMH7: ID 05 Revision 12 |
| 194 | PNP: 00ff.1 enabled |
| 195 | PNP: 0c31.0 enabled |
| 196 | EC Firmware ID G2HT35WW-3.22, Version 4.01B |
| 197 | H8: WWAN not installed |
| 198 | PNP: 00ff.2 enabled |
| 199 | scan_bus: scanning of bus PCI: 00:1f.0 took 4633 usecs |
| 200 | bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled |
| 201 | bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled |
| 202 | bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled |
| 203 | bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled |
| 204 | bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled |
| 205 | bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled |
| 206 | bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled |
| 207 | bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled |
| 208 | scan_bus: scanning of bus PCI: 00:1f.3 took 18 usecs |
| 209 | scan_bus: scanning of bus DOMAIN: 0000 took 5606 usecs |
| 210 | scan_bus: scanning of bus Root Device took 5611 usecs |
| 211 | done |
| 212 | FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes) |
| 213 | MRC: No data in cbmem for 'RW_MRC_CACHE'. |
| 214 | BS: BS_DEV_ENUMERATE times (ms): entry 0 run 6 exit 0 |
| 215 | found VGA at PCI: 00:02.0 |
| 216 | Setting up VGA for PCI: 00:02.0 |
| 217 | Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| 218 | Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| 219 | Allocating resources... |
| 220 | Reading resources... |
| 221 | Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| 222 | PNP: 00ff.1 missing read_resources |
| 223 | PNP: 00ff.2 missing read_resources |
| 224 | Done reading resources. |
| 225 | skipping PNP: 00ff.2@60 fixed resource, size=0! |
| 226 | skipping PNP: 00ff.2@62 fixed resource, size=0! |
| 227 | skipping PNP: 00ff.2@64 fixed resource, size=0! |
| 228 | skipping PNP: 00ff.2@66 fixed resource, size=0! |
| 229 | Setting resources... |
| 230 | TOUUD 0x23d600000 TOLUD 0xc2a00000 TOM 0x200000000 |
| 231 | MEBASE 0x7ffff00000 |
| 232 | IGD decoded, subtracting 32M UMA and 2M GTT |
| 233 | TSEG base 0xc0000000 size 8M |
| 234 | Available memory below 4GB: 3072M |
| 235 | Available memory above 4GB: 5078M |
| 236 | PCI: 00:02.0 10 <- [0x00e1000000 - 0x00e13fffff] size 0x00400000 gran 0x16 mem64 |
| 237 | PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 |
| 238 | PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io |
| 239 | PCI: 00:04.0 10 <- [0x00e1630000 - 0x00e1637fff] size 0x00008000 gran 0x0f mem64 |
| 240 | PCI: 00:14.0 10 <- [0x00e1620000 - 0x00e162ffff] size 0x00010000 gran 0x10 mem64 |
| 241 | PCI: 00:16.0 10 <- [0x00e1642000 - 0x00e164200f] size 0x00000010 gran 0x04 mem64 |
| 242 | PCI: 00:19.0 10 <- [0x00e1600000 - 0x00e161ffff] size 0x00020000 gran 0x11 mem |
| 243 | PCI: 00:19.0 14 <- [0x00e163c000 - 0x00e163cfff] size 0x00001000 gran 0x0c mem |
| 244 | PCI: 00:19.0 18 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io |
| 245 | PCI: 00:1a.0 10 <- [0x00e163f000 - 0x00e163f3ff] size 0x00000400 gran 0x0a mem |
| 246 | PCI: 00:1b.0 10 <- [0x00e1638000 - 0x00e163bfff] size 0x00004000 gran 0x0e mem64 |
| 247 | PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| 248 | PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| 249 | PCI: 00:1c.0 20 <- [0x00e1400000 - 0x00e14fffff] size 0x00100000 gran 0x14 bus 01 mem |
| 250 | PCI: 01:00.0 10 <- [0x00e1400000 - 0x00e14000ff] size 0x00000100 gran 0x08 mem |
| 251 | PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| 252 | PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| 253 | PCI: 00:1c.1 20 <- [0x00e1500000 - 0x00e15fffff] size 0x00100000 gran 0x14 bus 02 mem |
| 254 | PCI: 02:00.0 10 <- [0x00e1500000 - 0x00e1501fff] size 0x00002000 gran 0x0d mem64 |
| 255 | PCI: 00:1c.2 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io |
| 256 | PCI: 00:1c.2 24 <- [0x00e0000000 - 0x00e07fffff] size 0x00800000 gran 0x14 bus 03 prefmem |
| 257 | PCI: 00:1c.2 20 <- [0x00e0800000 - 0x00e0ffffff] size 0x00800000 gran 0x14 bus 03 mem |
| 258 | NONE missing set_resources |
| 259 | PCI: 00:1d.0 10 <- [0x00e1640000 - 0x00e16403ff] size 0x00000400 gran 0x0a mem |
| 260 | PNP: 00ff.1 missing set_resources |
| 261 | PNP: 00ff.2 missing set_resources |
| 262 | PCI: 00:1f.2 10 <- [0x0000003080 - 0x0000003087] size 0x00000008 gran 0x03 io |
| 263 | PCI: 00:1f.2 14 <- [0x0000003090 - 0x0000003093] size 0x00000004 gran 0x02 io |
| 264 | PCI: 00:1f.2 18 <- [0x0000003088 - 0x000000308f] size 0x00000008 gran 0x03 io |
| 265 | PCI: 00:1f.2 1c <- [0x0000003094 - 0x0000003097] size 0x00000004 gran 0x02 io |
| 266 | PCI: 00:1f.2 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io |
| 267 | PCI: 00:1f.2 24 <- [0x00e163e000 - 0x00e163e7ff] size 0x00000800 gran 0x0b mem |
| 268 | PCI: 00:1f.3 10 <- [0x00e1641000 - 0x00e16410ff] size 0x00000100 gran 0x08 mem64 |
| 269 | PCI: 00:1f.6 10 <- [0x00e163d000 - 0x00e163dfff] size 0x00001000 gran 0x0c mem64 |
| 270 | Done setting resources. |
| 271 | Done allocating resources. |
| 272 | BS: BS_DEV_RESOURCES times (ms): entry 0 run 1 exit 0 |
| 273 | Enabling resources... |
| 274 | PCI: 00:00.0 subsystem <- 17aa/21fa |
| 275 | PCI: 00:00.0 cmd <- 06 |
| 276 | PCI: 00:02.0 subsystem <- 17aa/21fa |
| 277 | PCI: 00:02.0 cmd <- 03 |
| 278 | PCI: 00:04.0 cmd <- 02 |
| 279 | PCI: 00:14.0 subsystem <- 17aa/21fa |
| 280 | PCI: 00:14.0 cmd <- 102 |
| 281 | PCI: 00:16.0 subsystem <- 17aa/21fa |
| 282 | PCI: 00:16.0 cmd <- 02 |
| 283 | PCI: 00:19.0 subsystem <- 17aa/21f3 |
| 284 | PCI: 00:19.0 cmd <- 103 |
| 285 | PCI: 00:1a.0 subsystem <- 17aa/21fa |
| 286 | PCI: 00:1a.0 cmd <- 102 |
| 287 | PCI: 00:1b.0 subsystem <- 17aa/21fa |
| 288 | PCI: 00:1b.0 cmd <- 102 |
| 289 | PCI: 00:1c.0 bridge ctrl <- 0013 |
| 290 | PCI: 00:1c.0 subsystem <- 17aa/21fa |
| 291 | PCI: 00:1c.0 cmd <- 106 |
| 292 | PCI: 00:1c.1 bridge ctrl <- 0013 |
| 293 | PCI: 00:1c.1 subsystem <- 17aa/21fa |
| 294 | PCI: 00:1c.1 cmd <- 106 |
| 295 | PCI: 00:1c.2 bridge ctrl <- 0013 |
| 296 | PCI: 00:1c.2 subsystem <- 17aa/21fa |
| 297 | PCI: 00:1c.2 cmd <- 107 |
| 298 | PCI: 00:1d.0 subsystem <- 17aa/21fa |
| 299 | PCI: 00:1d.0 cmd <- 102 |
| 300 | PCI: 00:1f.0 subsystem <- 17aa/21fa |
| 301 | PCI: 00:1f.0 cmd <- 107 |
| 302 | PCI: 00:1f.2 subsystem <- 17aa/21fa |
| 303 | PCI: 00:1f.2 cmd <- 03 |
| 304 | PCI: 00:1f.3 subsystem <- 17aa/21fa |
| 305 | PCI: 00:1f.3 cmd <- 103 |
| 306 | PCI: 00:1f.6 subsystem <- 17aa/21fa |
| 307 | PCI: 00:1f.6 cmd <- 02 |
| 308 | PCI: 01:00.0 subsystem <- 17aa/21fa |
| 309 | PCI: 01:00.0 cmd <- 06 |
| 310 | PCI: 02:00.0 cmd <- 02 |
| 311 | done. |
| 312 | BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0 |
| 313 | Found TPM ST33ZP24 by ST Microelectronics |
| 314 | TPM: Startup |
| 315 | TPM: command 0x99 returned 0x0 |
| 316 | TPM: Asserting physical presence |
| 317 | TPM: command 0x4000000a returned 0x0 |
| 318 | TPM: command 0x65 returned 0x0 |
| 319 | TPM: flags disable=0, deactivated=0, nvlocked=1 |
| 320 | TPM: setup succeeded |
| 321 | Initializing devices... |
| 322 | Root Device init ... |
| 323 | Root Device init finished in 1 usecs |
| 324 | CPU_CLUSTER: 0 init ... |
| 325 | MTRR: Physical address space: |
| 326 | 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 327 | 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 328 | 0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6 |
| 329 | 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0 |
| 330 | 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 |
| 331 | 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 |
| 332 | 0x0000000100000000 - 0x000000023d600000 size 0x13d600000 type 6 |
| 333 | MTRR: Fixed MSR 0x250 0x0606060606060606 |
| 334 | MTRR: Fixed MSR 0x258 0x0606060606060606 |
| 335 | MTRR: Fixed MSR 0x259 0x0000000000000000 |
| 336 | MTRR: Fixed MSR 0x268 0x0606060606060606 |
| 337 | MTRR: Fixed MSR 0x269 0x0606060606060606 |
| 338 | MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| 339 | MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| 340 | MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| 341 | MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| 342 | MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| 343 | MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| 344 | CPU physical address size: 36 bits |
| 345 | MTRR: default type WB/UC MTRR counts: 3/5. |
| 346 | MTRR: WB selected as default type. |
| 347 | MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 |
| 348 | MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 |
| 349 | MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 |
| 350 | |
| 351 | MTRR check |
| 352 | Fixed MTRRs : Enabled |
| 353 | Variable MTRRs: Enabled |
| 354 | |
| 355 | CPU has 2 cores, 4 threads enabled. |
| 356 | Setting up SMI for CPU |
| 357 | Will perform SMM setup. |
| 358 | FMAP: area COREBOOT found @ 650200 (5963264 bytes) |
| 359 | CBFS: 'COREBOOT Locator' located CBFS at [650200:c00000) |
| 360 | CBFS: Locating 'cpu_microcode_blob.bin' |
| 361 | CBFS: Found @ offset 13840 size 6800 |
| 362 | microcode: sig=0x306a9 pf=0x10 revision=0x21 |
| 363 | CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz. |
| 364 | Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170 |
| 365 | Processing 16 relocs. Offset value of 0x00030000 |
| 366 | Attempting to start 3 APs |
| 367 | Waiting for 10ms after sending INIT. |
| 368 | Waiting for 1st SIPI to complete...done. |
| 369 | Waiting for 2nd SIPI to complete...AP: slot 1 apic_id 1. |
| 370 | done. |
| 371 | AP: slot 2 apic_id 3. |
| 372 | AP: slot 3 apic_id 2. |
| 373 | Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a8 memsize: 0x1a8 |
| 374 | Processing 13 relocs. Offset value of 0x00038000 |
| 375 | SMM Module: stub loaded at 0x00038000. Will call 0xbff9f328(0x00000000) |
| 376 | Installing SMM handler to 0xc0000000 |
| 377 | Loading module at 0xc0010000 with entry 0xc0010cc0. filesize: 0x5d10 memsize: 0x9e48 |
| 378 | Processing 446 relocs. Offset value of 0xc0010000 |
| 379 | Loading module at 0xc0008000 with entry 0xc0008000. filesize: 0x1a8 memsize: 0x1a8 |
| 380 | Processing 13 relocs. Offset value of 0xc0008000 |
| 381 | SMM Module: placing jmp sequence at 0xc0007c00 rel16 0x03fd |
| 382 | SMM Module: placing jmp sequence at 0xc0007800 rel16 0x07fd |
| 383 | SMM Module: placing jmp sequence at 0xc0007400 rel16 0x0bfd |
| 384 | SMM Module: stub loaded at 0xc0008000. Will call 0xc0010cc0(0x00000000) |
| 385 | Initializing Southbridge SMI... |
| 386 | |
| 387 | New SMBASE 0xc0000000 |
| 388 | In relocation handler: cpu 0 |
| 389 | New SMBASE=0xc0000000 IEDBASE=0xc0400000 |
| 390 | Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| 391 | Relocation complete. |
| 392 | microcode: Update skipped, already up-to-date |
| 393 | New SMBASE 0xbffffc00 |
| 394 | In relocation handler: cpu 1 |
| 395 | New SMBASE=0xbffffc00 IEDBASE=0xc0400000 |
| 396 | Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| 397 | Relocation complete. |
| 398 | microcode: Update skipped, already up-to-date |
| 399 | New SMBASE 0xbffff800 |
| 400 | In relocation handler: cpu 2 |
| 401 | New SMBASE=0xbffff800 IEDBASE=0xc0400000 |
| 402 | Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| 403 | Relocation complete. |
| 404 | microcode: Update skipped, already up-to-date |
| 405 | New SMBASE 0xbffff400 |
| 406 | In relocation handler: cpu 3 |
| 407 | New SMBASE=0xbffff400 IEDBASE=0xc0400000 |
| 408 | Writing SMRR. base = 0xc0000006, mask=0xff800800 |
| 409 | Relocation complete. |
| 410 | microcode: Update skipped, already up-to-date |
| 411 | Initializing CPU #0 |
| 412 | CPU: vendor Intel device 306a9 |
| 413 | CPU: family 06, model 3a, stepping 09 |
| 414 | Enabling cache |
| 415 | CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz. |
| 416 | CPU: platform id 4 |
| 417 | CPU: cpuid(1) 0x306a9 |
| 418 | CPU: AES supported |
| 419 | CPU: TXT supported |
| 420 | CPU: VT supported |
| 421 | Setting up local APIC... |
| 422 | apic_id: 0x00 done. |
| 423 | IA32_FEATURE_CONTROL already locked; VMX status: enabled |
| 424 | IA32_FEATURE_CONTROL already locked |
| 425 | model_x06ax: energy policy set to 6 |
| 426 | model_x06ax: frequency set to 2600 |
| 427 | Turbo is available but hidden |
| 428 | Turbo is available and visible |
| 429 | CPU #0 initialized |
| 430 | Initializing CPU #1 |
| 431 | Initializing CPU #2 |
| 432 | Initializing CPU #3 |
| 433 | CPU: vendor Intel device 306a9 |
| 434 | CPU: family 06, model 3a, stepping 09 |
| 435 | CPU: vendor Intel device 306a9 |
| 436 | CPU: family 06, model 3a, stepping 09 |
| 437 | Enabling cache |
| 438 | Enabling cache |
| 439 | CPU: vendor Intel device 306a9 |
| 440 | CPU: family 06, model 3a, stepping 09 |
| 441 | Enabling cache |
| 442 | CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz. |
| 443 | CPU: platform id 4 |
| 444 | CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz. |
| 445 | CPU: cpuid(1) 0x306a9 |
| 446 | CPU: platform id 4 |
| 447 | CPU: AES supported |
| 448 | CPU: TXT supported |
| 449 | CPU: VT supported |
| 450 | CPU: cpuid(1) 0x306a9 |
| 451 | Setting up local APIC... |
| 452 | CPU: AES supported |
| 453 | CPU: TXT supported |
| 454 | CPU: VT supported |
| 455 | CPU: Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz. |
| 456 | Setting up local APIC... |
| 457 | apic_id: 0x03 CPU: platform id 4 |
| 458 | done. |
| 459 | apic_id: 0x02 done. |
| 460 | IA32_FEATURE_CONTROL already locked; VMX status: enabled |
| 461 | IA32_FEATURE_CONTROL already locked; VMX status: enabled |
| 462 | IA32_FEATURE_CONTROL already locked |
| 463 | IA32_FEATURE_CONTROL already locked |
| 464 | CPU: cpuid(1) 0x306a9 |
| 465 | CPU: AES supported |
| 466 | CPU: TXT supported |
| 467 | CPU: VT supported |
| 468 | Setting up local APIC... |
| 469 | apic_id: 0x01 done. |
| 470 | IA32_FEATURE_CONTROL already locked; VMX status: enabled |
| 471 | IA32_FEATURE_CONTROL already locked |
| 472 | model_x06ax: energy policy set to 6 |
| 473 | model_x06ax: energy policy set to 6 |
| 474 | model_x06ax: frequency set to 2600 |
| 475 | model_x06ax: frequency set to 2600 |
| 476 | CPU #2 initialized |
| 477 | CPU #3 initialized |
| 478 | model_x06ax: energy policy set to 6 |
| 479 | model_x06ax: frequency set to 2600 |
| 480 | CPU #1 initialized |
| 481 | bsp_do_flight_plan done after 8 msecs. |
| 482 | Initializing southbridge SMI... |
| 483 | SMI_STS: |
| 484 | GPE0_STS: GPIO15 GPIO14 GPIO11 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO0 |
| 485 | ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0 |
| 486 | TCO_STS: |
| 487 | Locking SMM. |
| 488 | CPU_CLUSTER: 0 init finished in 21828 usecs |
| 489 | PCI: 00:00.0 init ... |
| 490 | Disabling PEG12. |
| 491 | Disabling PEG11. |
| 492 | Disabling PEG10. |
| 493 | Disabling PEG60. |
| 494 | Disabling Device 7. |
| 495 | Disabling PEG IO clock. |
| 496 | Set BIOS_RESET_CPL |
| 497 | CPU TDP: 35 Watts |
| 498 | PCI: 00:00.0 init finished in 1012 usecs |
| 499 | PCI: 00:02.0 init ... |
| 500 | GT Power Management Init |
| 501 | IVB GT2 25W-35W Power Meter Weights |
| 502 | GT Power Management Init (post VBIOS) |
| 503 | |
| 504 | [0.605017] CONFIG => |
| 505 | [0.605017] (Primary => |
| 506 | [0.605018] (Port => Internal, |
| 507 | [0.605018] Framebuffer => |
| 508 | [0.605019] (Width => 1366, |
| 509 | [0.605019] Height => 768, |
| 510 | [0.605020] Start_X => 0, |
| 511 | [0.605020] Start_Y => 0, |
| 512 | [0.605021] Stride => 1376, |
| 513 | [0.605021] V_Stride => 768, |
| 514 | [0.605022] Tiling => Linear , |
| 515 | [0.605022] Rotation => No_Rotation, |
| 516 | [0.605023] Offset => 0x00000000, |
| 517 | [0.605023] BPC => 8), |
| 518 | [0.605024] Mode => |
| 519 | [0.605024] (Dotclock => 69700000, |
| 520 | [0.605025] H_Visible => 1366, |
| 521 | [0.605025] H_Sync_Begin => 1414, |
| 522 | [0.605026] H_Sync_End => 1446, |
| 523 | [0.605026] H_Total => 1470, |
| 524 | [0.605027] V_Visible => 768, |
| 525 | [0.605027] V_Sync_Begin => 770, |
| 526 | [0.605028] V_Sync_End => 775, |
| 527 | [0.605028] V_Total => 790, |
| 528 | [0.605029] H_Sync_Active_High => True, |
| 529 | [0.605029] V_Sync_Active_High => False, |
| 530 | [0.605030] BPC => 5)), |
| 531 | [0.605030] Secondary => |
| 532 | [0.605031] (Port => Disabled, |
| 533 | [0.605031] Framebuffer => |
| 534 | [0.605032] (Width => 1, |
| 535 | [0.605032] Height => 1, |
| 536 | [0.605033] Start_X => 0, |
| 537 | [0.605033] Start_Y => 0, |
| 538 | [0.605034] Stride => 1, |
| 539 | [0.605034] V_Stride => 1, |
| 540 | [0.605035] Tiling => Linear , |
| 541 | [0.605035] Rotation => No_Rotation, |
| 542 | [0.605036] Offset => 0x00000000, |
| 543 | [0.605036] BPC => 8), |
| 544 | [0.605037] Mode => |
| 545 | [0.605037] (Dotclock => 1000000, |
| 546 | [0.605038] H_Visible => 1, |
| 547 | [0.605038] H_Sync_Begin => 1, |
| 548 | [0.605039] H_Sync_End => 1, |
| 549 | [0.605039] H_Total => 1, |
| 550 | [0.605040] V_Visible => 1, |
| 551 | [0.605040] V_Sync_Begin => 1, |
| 552 | [0.605041] V_Sync_End => 1, |
| 553 | [0.605041] V_Total => 1, |
| 554 | [0.605042] H_Sync_Active_High => False, |
| 555 | [0.605042] V_Sync_Active_High => False, |
| 556 | [0.605043] BPC => 5)), |
| 557 | [0.605043] Tertiary => |
| 558 | [0.605044] (Port => Disabled, |
| 559 | [0.605044] Framebuffer => |
| 560 | [0.605045] (Width => 1, |
| 561 | [0.605045] Height => 1, |
| 562 | [0.605046] Start_X => 0, |
| 563 | [0.605046] Start_Y => 0, |
| 564 | [0.605047] Stride => 1, |
| 565 | [0.605047] V_Stride => 1, |
| 566 | [0.605048] Tiling => Linear , |
| 567 | [0.605048] Rotation => No_Rotation, |
| 568 | [0.605049] Offset => 0x00000000, |
| 569 | [0.605049] BPC => 8), |
| 570 | [0.605050] Mode => |
| 571 | [0.605050] (Dotclock => 1000000, |
| 572 | [0.605051] H_Visible => 1, |
| 573 | [0.605051] H_Sync_Begin => 1, |
| 574 | [0.605052] H_Sync_End => 1, |
| 575 | [0.605052] H_Total => 1, |
| 576 | [0.605053] V_Visible => 1, |
| 577 | [0.605053] V_Sync_Begin => 1, |
| 578 | [0.605054] V_Sync_End => 1, |
| 579 | [0.605054] V_Total => 1, |
| 580 | [0.605055] H_Sync_Active_High => False, |
| 581 | [0.605055] V_Sync_Active_High => False, |
| 582 | [0.605056] BPC => 5))); |
| 583 | PCI: 00:02.0 init finished in 515428 usecs |
| 584 | PCI: 00:04.0 init ... |
| 585 | PCI: 00:04.0 init finished in 0 usecs |
| 586 | PCI: 00:14.0 init ... |
| 587 | XHCI: Setting up controller.. done. |
| 588 | PCI: 00:14.0 init finished in 7 usecs |
| 589 | PCI: 00:16.0 init ... |
| 590 | ME: FW Partition Table : OK |
| 591 | ME: Bringup Loader Failure : NO |
| 592 | ME: Firmware Init Complete : NO |
| 593 | ME: Manufacturing Mode : YES |
| 594 | ME: Boot Options Present : NO |
| 595 | ME: Update In Progress : NO |
| 596 | ME: Current Working State : Initializing |
| 597 | ME: Current Operation State : Bring up |
| 598 | ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| 599 | ME: Error Code : No Error |
| 600 | ME: Progress Phase : BUP Phase |
| 601 | ME: Power Management Event : Pseudo-global reset |
| 602 | ME: Progress Phase State : Check to see if straps say ME DISABLED |
| 603 | intel_me_path: mbp is not ready! |
| 604 | ME: BIOS path: Error |
| 605 | PCI: 00:16.0 init finished in 18 usecs |
| 606 | PCI: 00:19.0 init ... |
| 607 | PCI: 00:19.0 init finished in 0 usecs |
| 608 | PCI: 00:1a.0 init ... |
| 609 | EHCI: Setting up controller.. done. |
| 610 | PCI: 00:1a.0 init finished in 11 usecs |
| 611 | PCI: 00:1b.0 init ... |
| 612 | Azalia: base = e1638000 |
| 613 | Azalia: codec_mask = 09 |
| 614 | Azalia: Initializing codec #3 |
| 615 | Azalia: codec viddid: 80862806 |
| 616 | Azalia: verb_size: 16 |
| 617 | Azalia: verb loaded. |
| 618 | Azalia: Initializing codec #0 |
| 619 | Azalia: codec viddid: 10ec0269 |
| 620 | Azalia: verb_size: 76 |
| 621 | Azalia: verb loaded. |
| 622 | PCI: 00:1b.0 init finished in 5968 usecs |
| 623 | PCI: 00:1c.0 init ... |
| 624 | Initializing PCH PCIe bridge. |
| 625 | PCI: 00:1c.0 init finished in 8 usecs |
| 626 | PCI: 00:1c.1 init ... |
| 627 | Initializing PCH PCIe bridge. |
| 628 | PCI: 00:1c.1 init finished in 10 usecs |
| 629 | PCI: 00:1c.2 init ... |
| 630 | Initializing PCH PCIe bridge. |
| 631 | PCI: 00:1c.2 init finished in 12 usecs |
| 632 | PCI: 00:1d.0 init ... |
| 633 | EHCI: Setting up controller.. done. |
| 634 | PCI: 00:1d.0 init finished in 12 usecs |
| 635 | PCI: 00:1f.0 init ... |
| 636 | pch: lpc_init |
| 637 | PCH: detected QM77, device id: 0x1e55, rev id 0x4 |
| 638 | IOAPIC: Initializing IOAPIC at 0xfec00000 |
| 639 | IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| 640 | IOAPIC: ID = 0x02 |
| 641 | Set power off after power failure. |
| 642 | NMI sources enabled. |
| 643 | PantherPoint PM init |
| 644 | RTC: failed = 0x0 |
| 645 | RTC Init |
| 646 | Disabling ACPI via APMC: |
| 647 | done. |
| 648 | pch_spi_init |
| 649 | PCI: 00:1f.0 init finished in 701 usecs |
| 650 | PCI: 00:1f.2 init ... |
| 651 | SATA: Initializing... |
| 652 | SATA: Controller in AHCI mode. |
| 653 | ABAR: 0xe163e000 |
| 654 | PCI: 00:1f.2 init finished in 235 usecs |
| 655 | PCI: 00:1f.3 init ... |
| 656 | PCI: 00:1f.3 init finished in 7 usecs |
| 657 | PCI: 00:1f.6 init ... |
| 658 | PCI: 00:1f.6 init finished in 1 usecs |
| 659 | PCI: 01:00.0 init ... |
| 660 | PCI: 01:00.0 init finished in 15 usecs |
| 661 | PCI: 02:00.0 init ... |
| 662 | PCI: 02:00.0 init finished in 1 usecs |
| 663 | PNP: 00ff.2 init ... |
| 664 | PNP: 00ff.2 init finished in 0 usecs |
| 665 | smbus: PCI: 00:1f.3[0]->I2C: 01:54 init ... |
| 666 | I2C: 01:54 init finished in 1 usecs |
| 667 | smbus: PCI: 00:1f.3[0]->I2C: 01:55 init ... |
| 668 | I2C: 01:55 init finished in 1 usecs |
| 669 | smbus: PCI: 00:1f.3[0]->I2C: 01:56 init ... |
| 670 | I2C: 01:56 init finished in 1 usecs |
| 671 | smbus: PCI: 00:1f.3[0]->I2C: 01:57 init ... |
| 672 | I2C: 01:57 init finished in 2 usecs |
| 673 | smbus: PCI: 00:1f.3[0]->I2C: 01:5c init ... |
| 674 | Locking EEPROM RFID |
| 675 | init EEPROM done |
| 676 | I2C: 01:5c init finished in 24362 usecs |
| 677 | smbus: PCI: 00:1f.3[0]->I2C: 01:5d init ... |
| 678 | I2C: 01:5d init finished in 1 usecs |
| 679 | smbus: PCI: 00:1f.3[0]->I2C: 01:5e init ... |
| 680 | I2C: 01:5e init finished in 1 usecs |
| 681 | smbus: PCI: 00:1f.3[0]->I2C: 01:5f init ... |
| 682 | I2C: 01:5f init finished in 1 usecs |
| 683 | Devices initialized |
| 684 | BS: BS_DEV_INIT times (ms): entry 61 run 569 exit 0 |
| 685 | Finalize devices... |
| 686 | PCI: 00:1f.0 final |
| 687 | flash size 0xc00000 bytes |
| 688 | SF: Detected Opaque HW-sequencing with sector size 0x1000, total 0xc00000 |
| 689 | Devices finalized |
| 690 | BS: BS_POST_DEVICE times (ms): entry 0 run 0 exit 0 |
| 691 | BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0 |
| 692 | FMAP: area COREBOOT found @ 650200 (5963264 bytes) |
| 693 | CBFS: 'COREBOOT Locator' located CBFS at [650200:c00000) |
| 694 | CBFS: Locating 'fallback/dsdt.aml' |
| 695 | CBFS: Found @ offset 3cf00 size 39b0 |
| 696 | FMAP: area COREBOOT found @ 650200 (5963264 bytes) |
| 697 | CBFS: 'COREBOOT Locator' located CBFS at [650200:c00000) |
| 698 | CBFS: Locating 'fallback/slic' |
| 699 | CBFS: 'fallback/slic' not found. |
| 700 | ACPI: Writing ACPI tables at bff42000. |
| 701 | ACPI: * FACS |
| 702 | ACPI: * DSDT |
| 703 | ACPI: * FADT |
| 704 | ACPI: added table 1/32, length now 40 |
| 705 | ACPI: * SSDT |
| 706 | Found 1 CPU(s) with 4 core(s) each. |
| 707 | PSS: 2601MHz power 35000 control 0x2100 status 0x2100 |
| 708 | PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00 |
| 709 | PSS: 2400MHz power 31561 control 0x1800 status 0x1800 |
| 710 | PSS: 2200MHz power 28247 control 0x1600 status 0x1600 |
| 711 | PSS: 2000MHz power 25084 control 0x1400 status 0x1400 |
| 712 | PSS: 1800MHz power 22064 control 0x1200 status 0x1200 |
| 713 | PSS: 1600MHz power 19135 control 0x1000 status 0x1000 |
| 714 | PSS: 1400MHz power 16344 control 0xe00 status 0xe00 |
| 715 | PSS: 1200MHz power 13666 control 0xc00 status 0xc00 |
| 716 | PSS: 2601MHz power 35000 control 0x2100 status 0x2100 |
| 717 | PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00 |
| 718 | PSS: 2400MHz power 31561 control 0x1800 status 0x1800 |
| 719 | PSS: 2200MHz power 28247 control 0x1600 status 0x1600 |
| 720 | PSS: 2000MHz power 25084 control 0x1400 status 0x1400 |
| 721 | PSS: 1800MHz power 22064 control 0x1200 status 0x1200 |
| 722 | PSS: 1600MHz power 19135 control 0x1000 status 0x1000 |
| 723 | PSS: 1400MHz power 16344 control 0xe00 status 0xe00 |
| 724 | PSS: 1200MHz power 13666 control 0xc00 status 0xc00 |
| 725 | PSS: 2601MHz power 35000 control 0x2100 status 0x2100 |
| 726 | PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00 |
| 727 | PSS: 2400MHz power 31561 control 0x1800 status 0x1800 |
| 728 | PSS: 2200MHz power 28247 control 0x1600 status 0x1600 |
| 729 | PSS: 2000MHz power 25084 control 0x1400 status 0x1400 |
| 730 | PSS: 1800MHz power 22064 control 0x1200 status 0x1200 |
| 731 | PSS: 1600MHz power 19135 control 0x1000 status 0x1000 |
| 732 | PSS: 1400MHz power 16344 control 0xe00 status 0xe00 |
| 733 | PSS: 1200MHz power 13666 control 0xc00 status 0xc00 |
| 734 | PSS: 2601MHz power 35000 control 0x2100 status 0x2100 |
| 735 | PSS: 2600MHz power 35000 control 0x1a00 status 0x1a00 |
| 736 | PSS: 2400MHz power 31561 control 0x1800 status 0x1800 |
| 737 | PSS: 2200MHz power 28247 control 0x1600 status 0x1600 |
| 738 | PSS: 2000MHz power 25084 control 0x1400 status 0x1400 |
| 739 | PSS: 1800MHz power 22064 control 0x1200 status 0x1200 |
| 740 | PSS: 1600MHz power 19135 control 0x1000 status 0x1000 |
| 741 | PSS: 1400MHz power 16344 control 0xe00 status 0xe00 |
| 742 | PSS: 1200MHz power 13666 control 0xc00 status 0xc00 |
| 743 | Generating ACPI PIRQ entries |
| 744 | \_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0 |
| 745 | ACPI: * H8 |
| 746 | H8: BDC detection not implemented. Assuming BDC installed |
| 747 | H8: WWAN not installed |
| 748 | \_SB.PCI0.RP02.WF00: PCI: 02:00.0 |
| 749 | ACPI: added table 2/32, length now 44 |
| 750 | ACPI: * MCFG |
| 751 | ACPI: added table 3/32, length now 48 |
| 752 | ACPI: * TCPA |
| 753 | TCPA log created at 0xbff31000 |
| 754 | ACPI: added table 4/32, length now 52 |
| 755 | ACPI: * MADT |
| 756 | ACPI: added table 5/32, length now 56 |
| 757 | current = bff47a90 |
| 758 | ACPI: * DMAR |
| 759 | ACPI: added table 6/32, length now 60 |
| 760 | current = bff47b60 |
| 761 | FMAP: area COREBOOT found @ 650200 (5963264 bytes) |
| 762 | CBFS: 'COREBOOT Locator' located CBFS at [650200:c00000) |
| 763 | CBFS: Locating 'vbt.bin' |
| 764 | CBFS: Found @ offset 37700 size 599 |
| 765 | Found a VBT of 4281 bytes after decompression |
| 766 | GMA: Found VBT in CBFS |
| 767 | GMA: Found valid VBT in CBFS |
| 768 | ACPI: * HPET |
| 769 | ACPI: added table 7/32, length now 64 |
| 770 | ACPI: done. |
| 771 | ACPI tables: 31648 bytes. |
| 772 | smbios_write_tables: bff30000 |
| 773 | Create SMBIOS type 17 |
| 774 | PCI: 02:00.0 (unknown) |
| 775 | SMBIOS tables: 906 bytes. |
| 776 | Writing table forward entry at 0x00000500 |
| 777 | Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum dfe7 |
| 778 | Writing coreboot table at 0xbff66000 |
| 779 | FMAP: area COREBOOT found @ 650200 (5963264 bytes) |
| 780 | CBFS: 'COREBOOT Locator' located CBFS at [650200:c00000) |
| 781 | CBFS: Locating 'cmos_layout.bin' |
| 782 | CBFS: Found @ offset 37d00 size 70c |
| 783 | 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| 784 | 1. 0000000000001000-000000000009ffff: RAM |
| 785 | 2. 00000000000a0000-00000000000fffff: RESERVED |
| 786 | 3. 0000000000100000-00000000bff2ffff: RAM |
| 787 | 4. 00000000bff30000-00000000bff7efff: CONFIGURATION TABLES |
| 788 | 5. 00000000bff7f000-00000000bffd1fff: RAMSTAGE |
| 789 | 6. 00000000bffd2000-00000000bfffffff: CONFIGURATION TABLES |
| 790 | 7. 00000000c0000000-00000000c29fffff: RESERVED |
| 791 | 8. 00000000f0000000-00000000f3ffffff: RESERVED |
| 792 | 9. 00000000fed40000-00000000fed44fff: RESERVED |
| 793 | 10. 00000000fed90000-00000000fed91fff: RESERVED |
| 794 | 11. 0000000100000000-000000023d5fffff: RAM |
| 795 | FMAP: area COREBOOT found @ 650200 (5963264 bytes) |
| 796 | CBFS: 'COREBOOT Locator' located CBFS at [650200:c00000) |
| 797 | Wrote coreboot table at: 0xbff66000, 0xa98 bytes, checksum f51d |
| 798 | coreboot table: 2736 bytes. |
| 799 | IMD ROOT 0. 0xbffff000 0x00001000 |
| 800 | IMD SMALL 1. 0xbfffe000 0x00001000 |
| 801 | CONSOLE 2. 0xbffde000 0x00020000 |
| 802 | TIME STAMP 3. 0xbffdd000 0x00000910 |
| 803 | ROMSTG STCK 4. 0xbffdc000 0x00001000 |
| 804 | AFTER CAR 5. 0xbffd2000 0x0000a000 |
| 805 | RAMSTAGE 6. 0xbff7e000 0x00054000 |
| 806 | SMM BACKUP 7. 0xbff6e000 0x00010000 |
| 807 | COREBOOT 8. 0xbff66000 0x00008000 |
| 808 | ACPI 9. 0xbff42000 0x00024000 |
| 809 | ACPI GNVS 10. 0xbff41000 0x00001000 |
| 810 | TCPA TCGLOG11. 0xbff31000 0x00010000 |
| 811 | SMBIOS 12. 0xbff30000 0x00000800 |
| 812 | IMD small region: |
| 813 | IMD ROOT 0. 0xbfffec00 0x00000400 |
| 814 | FMAP 1. 0xbfffeae0 0x0000010a |
| 815 | MEM INFO 2. 0xbfffe920 0x000001b9 |
| 816 | ROMSTAGE 3. 0xbfffe900 0x00000004 |
| 817 | BS: BS_WRITE_TABLES times (ms): entry 0 run 26 exit 0 |
| 818 | FMAP: area COREBOOT found @ 650200 (5963264 bytes) |
| 819 | CBFS: 'COREBOOT Locator' located CBFS at [650200:c00000) |
| 820 | CBFS: Locating 'fallback/payload' |
| 821 | CBFS: Found @ offset 5dd80 size af51c |
| 822 | Checking segment from ROM address 0xffaadfb8 |
| 823 | Checking segment from ROM address 0xffaadfd4 |
| 824 | Loading segment from ROM address 0xffaadfb8 |
| 825 | code (compression=1) |
| 826 | New segment dstaddr 0x00800000 memsize 0x410000 srcaddr 0xffaadff0 filesize 0xaf4e4 |
| 827 | Loading Segment: addr: 0x00800000 memsz: 0x0000000000410000 filesz: 0x00000000000af4e4 |
| 828 | using LZMA |
| 829 | Loading segment from ROM address 0xffaadfd4 |
| 830 | Entry Point 0x008008f0 |
| 831 | BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 267 exit 0 |
| 832 | ICH-NM10-PCH: watchdog disabled |
| 833 | Jumping to boot code at 0x008008f0(0xbff66000) |
| 834 | |