Marshall Dawson | 483081e | 2016-11-18 20:45:42 -0500 | [diff] [blame] | 1 | CPU: ID 0x30679, Processor Type 0x0, Family 0x6, Model 0x37, Stepping 0x9 |
| 2 | Northbridge: 8086:0f00 (Bay Trail) |
| 3 | Southbridge: 8086:0f1c (Bay Trail) |
| 4 | IGD: 8086:0f31 (unknown) |
| 5 | |
| 6 | ===================== SHARED MSRs (All Cores) ===================== |
| 7 | MSR 0x00000000 = 0x00000000:0x00000000 (IA32_P5_MC_ADDR) |
| 8 | MSR 0x00000001 = 0x00000000:0x00000000 (IA32_P5_MC_TYPE) |
| 9 | MSR 0x00000017 = 0x0000000C:0x90040B3E (IA32_PLATFORM_ID) |
| 10 | MSR 0x0000002A = 0x00000000:0x40080000 (MSR_EBC_HARD_POWERON) |
| 11 | MSR 0x000000CD = 0x00000000:0x00000002 (MSR_FSB_FREQ) |
| 12 | MSR 0x000000E2 = 0x00000000:0x000E0008 (MSR_PKG_CST_CONFIG_CONTROL) |
| 13 | MSR 0x000000E4 = 0x00000000:0x00000000 (MSR_PMG_IO_CAPTURE_BASE) |
| 14 | MSR 0x0000011E = 0x00000000:0x7E28010F (BBL_CR_CTL3) |
| 15 | MSR 0x00000198 = 0x00007C00:0x00000B3E (IA32_PERF_STATUS) |
| 16 | MSR 0x000001A2 = 0x00000000:0x006E0000 (MSR_TEMPERATURE_TARGET) |
| 17 | MSR 0x000001A6 = 0x00000000:0x00000000 (MSR_OFFCORE_RSP_0) |
| 18 | MSR 0x000001A7 = 0x00000000:0x00000000 (MSR_OFFCORE_RSP_1) |
| 19 | MSR 0x000001AD = 0x00000000:0x00000000 (MSR_TURBO_RATIO_LIMIT) |
| 20 | MSR 0x000003FA = 0x00000025:0x0E0BC460 (MSR_PKG_C6_RESIDENCY) |
| 21 | MSR 0x00000400 = 0x00000000:0x0000003F (IA32_MC0_CTL) |
| 22 | MSR 0x00000401 = 0x00000000:0x00000000 (IA32_MC0_STATUS) |
| 23 | MSR 0x00000402 = 0x00000000:0x00000000 (IA32_MC0_ADDR) |
| 24 | MSR 0x00000404 = 0x00000000:0x00000001 (IA32_MC1_CTL) |
| 25 | MSR 0x00000405 = 0x00000000:0x00000000 (IA32_MC1_STATUS) |
| 26 | MSR 0x00000408 = 0x00000000:0x00000003 (IA32_MC2_CTL) |
| 27 | MSR 0x00000409 = 0x00000000:0x00000000 (IA32_MC2_STATUS) |
| 28 | MSR 0x0000040A = 0x00000000:0x00000000 (IA32_MC2_ADDR) |
| 29 | MSR 0x00000414 = 0x00000000:0x00000007 (MSR_MC5_CTL) |
| 30 | MSR 0x00000415 = 0x00000000:0x00000000 (MSR_MC5_STATUS) |
| 31 | MSR 0x00000416 = 0x00000000:0x00000000 (MSR_MC5_ADDR) |
| 32 | |
| 33 | ====================== UNIQUE MSRs (core 0) ====================== |
| 34 | MSR 0x00000006 = 0x00000000:0x00000040 (IA32_MONITOR_FILTER_LINE_SIZE) |
| 35 | MSR 0x00000010 = 0x00000065:0x72004294 (IA32_TIME_STAMP_COUNTER) |
| 36 | MSR 0x0000001B = 0x00000000:0xFEE00900 (IA32_APIC_BASE) |
| 37 | MSR 0x00000034 = 0x00000000:0x00000003 (MSR_SMI_COUNT) |
| 38 | MSR 0x0000003A = 0x00000000:0x00000000 (IA32_FEATURE_CONTROL) |
| 39 | MSR 0x00000040 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_FROM_IP) |
| 40 | MSR 0x00000041 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_FROM_IP) |
| 41 | MSR 0x00000042 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_FROM_IP) |
| 42 | MSR 0x00000043 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_FROM_IP) |
| 43 | MSR 0x00000044 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_FROM_IP) |
| 44 | MSR 0x00000045 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_FROM_IP) |
| 45 | MSR 0x00000046 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_FROM_IP) |
| 46 | MSR 0x00000047 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_FROM_IP) |
| 47 | MSR 0x00000060 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_TO_IP) |
| 48 | MSR 0x00000061 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_TO_IP) |
| 49 | MSR 0x00000062 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_TO_IP) |
| 50 | MSR 0x00000063 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_TO_IP) |
| 51 | MSR 0x00000064 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_TO_IP) |
| 52 | MSR 0x00000065 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_TO_IP) |
| 53 | MSR 0x00000066 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_TO_IP) |
| 54 | MSR 0x00000067 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_TO_IP) |
| 55 | MSR 0x0000008B = 0x00000901:0x00000000 (IA32_BIOS_SIGN_ID) |
| 56 | MSR 0x000000C1 = 0x00000000:0x00000000 (IA32_PMC0) |
| 57 | MSR 0x000000C2 = 0x00000000:0x0000FFFF (IA32_PMC1) |
| 58 | MSR 0x000000E7 = 0x00000021:0x08A3B8FB (IA32_MPERF) |
| 59 | MSR 0x000000E8 = 0x0000001E:0xE139CFF6 (IA32_APERF) |
| 60 | MSR 0x000000FE = 0x00000000:0x00000D08 (IA32_MTRRCAP) |
| 61 | MSR 0x00000174 = 0x00000000:0x00000010 (IA32_SYSENTER_CS) |
| 62 | MSR 0x00000175 = 0x00000000:0x00000000 (IA32_SYSENTER_ESP) |
| 63 | MSR 0x00000176 = 0xFFFFFFFF:0x81826A60 (IA32_SYSENTER_EIP) |
| 64 | MSR 0x00000179 = 0x00000000:0x00000806 (IA32_MCG_CAP) |
| 65 | MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS) |
| 66 | MSR 0x00000186 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL0) |
| 67 | MSR 0x00000187 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL1) |
| 68 | MSR 0x00000199 = 0x00000000:0x00000B3E (IA32_PERF_CONTROL) |
| 69 | MSR 0x0000019A = 0x00000000:0x00000000 (IA32_CLOCK_MODULATION) |
| 70 | MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT) |
| 71 | MSR 0x0000019C = 0x00000000:0x88440000 (IA32_THERM_STATUS) |
| 72 | MSR 0x000001A0 = 0x00000000:0x00850089 (IA32_MISC_ENABLES) |
| 73 | MSR 0x000001B0 = 0x00000000:0x00000006 (IA32_ENERGY_PERF_BIAS) |
| 74 | MSR 0x000001C9 = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS) |
| 75 | MSR 0x000001D9 = 0x00000000:0x00000000 (IA32_DEBUGCTL) |
| 76 | MSR 0x000001DD = 0x00000000:0x00000000 (MSR_LER_FROM_LIP) |
| 77 | MSR 0x000001DE = 0x00000000:0x00000000 (MSR_LER_TO_LIP) |
| 78 | MSR 0x000001F2 = 0x00000000:0x7B000006 (IA32_SMRR_PHYSBASE) |
| 79 | MSR 0x000001F3 = 0x00000000:0xFF800800 (IA32_SMRR_PHYSMASK) |
| 80 | MSR 0x00000200 = 0x00000000:0xFF800005 (IA32_MTRR_PHYSBASE0) |
| 81 | MSR 0x00000201 = 0x0000000F:0xFF800800 (IA32_MTRR_PHYSMASK0) |
| 82 | MSR 0x00000202 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE1) |
| 83 | MSR 0x00000203 = 0x0000000F:0x80000800 (IA32_MTRR_PHYSMASK1) |
| 84 | MSR 0x00000204 = 0x00000000:0x7B000000 (IA32_MTRR_PHYSBASE2) |
| 85 | MSR 0x00000205 = 0x0000000F:0xFF000800 (IA32_MTRR_PHYSMASK2) |
| 86 | MSR 0x00000206 = 0x00000000:0x7C000000 (IA32_MTRR_PHYSBASE3) |
| 87 | MSR 0x00000207 = 0x0000000F:0xFC000800 (IA32_MTRR_PHYSMASK3) |
| 88 | MSR 0x00000208 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE4) |
| 89 | MSR 0x00000209 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK4) |
| 90 | MSR 0x0000020A = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE5) |
| 91 | MSR 0x0000020B = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK5) |
| 92 | MSR 0x0000020C = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE6) |
| 93 | MSR 0x0000020D = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK6) |
| 94 | MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7) |
| 95 | MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7) |
| 96 | MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000) |
| 97 | MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000) |
| 98 | MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000) |
| 99 | MSR 0x00000268 = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_C0000) |
| 100 | MSR 0x00000269 = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_C8000) |
| 101 | MSR 0x0000026A = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_D0000) |
| 102 | MSR 0x0000026B = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_D8000) |
| 103 | MSR 0x0000026C = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_E0000) |
| 104 | MSR 0x0000026D = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_E8000) |
| 105 | MSR 0x0000026E = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_F0000) |
| 106 | MSR 0x0000026F = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_F8000) |
| 107 | MSR 0x00000277 = 0x04070106:0x00070106 (IA32_PAT) |
| 108 | MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE) |
| 109 | MSR 0x00000309 = 0x00000000:0x00000000 (IA32_FIXED_CTR0) |
| 110 | MSR 0x0000030A = 0x000000FE:0x6CA70F78 (IA32_FIXED_CTR1) |
| 111 | MSR 0x0000030B = 0x00000000:0x00000000 (IA32_FIXED_CTR2) |
| 112 | MSR 0x00000345 = 0x00000000:0x000032C1 (IA32_PERF_CAPABILITIES) |
| 113 | MSR 0x0000038D = 0x00000000:0x000000B0 (IA32_FIXED_CTR_CTRL) |
| 114 | MSR 0x0000038E = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_STATUS) |
| 115 | MSR 0x0000038F = 0x00000007:0x00000003 (IA32_PERF_GLOBAL_CTRL) |
| 116 | MSR 0x00000390 = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_OVF_CTRL) |
| 117 | MSR 0x000003F1 = 0x00000000:0x00000000 (MSR_PEBS_ENABLE) |
| 118 | MSR 0x000003FD = 0x0000002D:0x72D022E0 (MSR_CORE_C6_RESIDENCY) |
| 119 | MSR 0x0000040C = 0x00000000:0x00000003 (IA32_MC3_CTL) |
| 120 | MSR 0x0000040D = 0x00000000:0x00000000 (IA32_MC3_STATUS) |
| 121 | MSR 0x0000040E = 0x00000000:0x00000000 (IA32_MC3_ADDR) |
| 122 | MSR 0x00000410 = 0x00000000:0x00000001 (IA32_MC4_CTL) |
| 123 | MSR 0x00000411 = 0x00000000:0x00000000 (IA32_MC4_STATUS) |
| 124 | MSR 0x00000412 = 0x00000000:0x00000000 (IA32_MC4_ADDR) |
| 125 | MSR 0x00000480 = 0x00DA0400:0x00000002 (IA32_VMX_BASIC) |
| 126 | MSR 0x00000481 = 0x0000007F:0x00000016 (IA32_VMX_PINBASED_CTLS) |
| 127 | MSR 0x00000482 = 0xFFF9FFFE:0x0401E172 (IA32_VMX_PROCBASED_CTLS) |
| 128 | MSR 0x00000483 = 0x007FFFFF:0x00036DFF (IA32_VMX_EXIT_CTLS) |
| 129 | MSR 0x00000484 = 0x0000FFFF:0x000011FF (IA32_VMX_ENTRY_CTLS) |
| 130 | MSR 0x00000485 = 0x00000000:0x000481E6 (IA32_VMX_MISC) |
| 131 | MSR 0x00000486 = 0x00000000:0x80000021 (IA32_VMX_CR0_FIXED0) |
| 132 | MSR 0x00000487 = 0x00000000:0xFFFFFFFF (IA32_VMX_CR0_FIXED1) |
| 133 | MSR 0x00000488 = 0x00000000:0x00002000 (IA32_VMX_CR4_FIXED0) |
| 134 | MSR 0x00000489 = 0x00000000:0x001027FF (IA32_VMX_CR4_FIXED1) |
| 135 | MSR 0x0000048A = 0x00000000:0x0000002E (IA32_VMX_VMCS_ENUM) |
| 136 | MSR 0x0000048B = 0x000028EF:0x00000000 (IA32_VMX_PROCBASED_CTLS2) |
| 137 | MSR 0x0000048C = 0x00000F01:0x06114141 (IA32_VMX_EPT_VPID_ENUM) |
| 138 | MSR 0x0000048D = 0x0000007F:0x00000016 (IA32_VMX_TRUE_PINBASED_CTLS) |
| 139 | MSR 0x0000048E = 0xFFF9FFFE:0x04006172 (IA32_VMX_TRUE_PROCBASED_CTLS) |
| 140 | MSR 0x0000048F = 0x007FFFFF:0x00036DFB (IA32_VMX_TRUE_EXIT_CTLS) |
| 141 | MSR 0x00000490 = 0x0000FFFF:0x000011FB (IA32_VMX_TRUE_ENTRY_CTLS) |
| 142 | MSR 0x00000491 = 0x00000000:0x00000001 (IA32_VMX_FMFUNC) |
| 143 | MSR 0x000004C1 = 0x00000000:0x00000000 (IA32_A_PMC0) |
| 144 | MSR 0x000004C2 = 0x00000000:0x0000FFFF (IA32_A_PMC1) |
| 145 | MSR 0x00000600 = 0xFFFF8800:0x783D2900 (IA32_DS_AREA) |
| 146 | MSR 0x00000660 = 0x00000015:0xE4056F67 (MSR_CORE_C1_RESIDENCY) |
| 147 | MSR 0x000006E0 = 0x00000065:0x725FDA40 (IA32_TSC_DEADLINE) |
| 148 | |
| 149 | ====================== UNIQUE MSRs (core 1) ====================== |
| 150 | MSR 0x00000006 = 0x00000000:0x00000040 (IA32_MONITOR_FILTER_LINE_SIZE) |
| 151 | MSR 0x00000010 = 0x00000065:0x720FF622 (IA32_TIME_STAMP_COUNTER) |
| 152 | MSR 0x0000001B = 0x00000000:0xFEE00800 (IA32_APIC_BASE) |
| 153 | MSR 0x00000034 = 0x00000000:0x00000003 (MSR_SMI_COUNT) |
| 154 | MSR 0x0000003A = 0x00000000:0x00000000 (IA32_FEATURE_CONTROL) |
| 155 | MSR 0x00000040 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_FROM_IP) |
| 156 | MSR 0x00000041 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_FROM_IP) |
| 157 | MSR 0x00000042 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_FROM_IP) |
| 158 | MSR 0x00000043 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_FROM_IP) |
| 159 | MSR 0x00000044 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_FROM_IP) |
| 160 | MSR 0x00000045 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_FROM_IP) |
| 161 | MSR 0x00000046 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_FROM_IP) |
| 162 | MSR 0x00000047 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_FROM_IP) |
| 163 | MSR 0x00000060 = 0x00000000:0x00000000 (MSR_LASTBRANCH_0_TO_IP) |
| 164 | MSR 0x00000061 = 0x00000000:0x00000000 (MSR_LASTBRANCH_1_TO_IP) |
| 165 | MSR 0x00000062 = 0x00000000:0x00000000 (MSR_LASTBRANCH_2_TO_IP) |
| 166 | MSR 0x00000063 = 0x00000000:0x00000000 (MSR_LASTBRANCH_3_TO_IP) |
| 167 | MSR 0x00000064 = 0x00000000:0x00000000 (MSR_LASTBRANCH_4_TO_IP) |
| 168 | MSR 0x00000065 = 0x00000000:0x00000000 (MSR_LASTBRANCH_5_TO_IP) |
| 169 | MSR 0x00000066 = 0x00000000:0x00000000 (MSR_LASTBRANCH_6_TO_IP) |
| 170 | MSR 0x00000067 = 0x00000000:0x00000000 (MSR_LASTBRANCH_7_TO_IP) |
| 171 | MSR 0x0000008B = 0x00000901:0x00000000 (IA32_BIOS_SIGN_ID) |
| 172 | MSR 0x000000C1 = 0x00000000:0x00000000 (IA32_PMC0) |
| 173 | MSR 0x000000C2 = 0x00000000:0x00000000 (IA32_PMC1) |
| 174 | MSR 0x000000E7 = 0x00000009:0x4F4B9D80 (IA32_MPERF) |
| 175 | MSR 0x000000E8 = 0x00000008:0xC4E40C33 (IA32_APERF) |
| 176 | MSR 0x000000FE = 0x00000000:0x00000D08 (IA32_MTRRCAP) |
| 177 | MSR 0x00000174 = 0x00000000:0x00000010 (IA32_SYSENTER_CS) |
| 178 | MSR 0x00000175 = 0x00000000:0x00000000 (IA32_SYSENTER_ESP) |
| 179 | MSR 0x00000176 = 0xFFFFFFFF:0x81826A60 (IA32_SYSENTER_EIP) |
| 180 | MSR 0x00000179 = 0x00000000:0x00000806 (IA32_MCG_CAP) |
| 181 | MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS) |
| 182 | MSR 0x00000186 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL0) |
| 183 | MSR 0x00000187 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL1) |
| 184 | MSR 0x00000199 = 0x00000000:0x00000B3E (IA32_PERF_CONTROL) |
| 185 | MSR 0x0000019A = 0x00000000:0x00000000 (IA32_CLOCK_MODULATION) |
| 186 | MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT) |
| 187 | MSR 0x0000019C = 0x00000000:0x88460000 (IA32_THERM_STATUS) |
| 188 | MSR 0x000001A0 = 0x00000000:0x00850089 (IA32_MISC_ENABLES) |
| 189 | MSR 0x000001B0 = 0x00000000:0x00000006 (IA32_ENERGY_PERF_BIAS) |
| 190 | MSR 0x000001C9 = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS) |
| 191 | MSR 0x000001D9 = 0x00000000:0x00000000 (IA32_DEBUGCTL) |
| 192 | MSR 0x000001DD = 0x00000000:0x00000000 (MSR_LER_FROM_LIP) |
| 193 | MSR 0x000001DE = 0x00000000:0x00000000 (MSR_LER_TO_LIP) |
| 194 | MSR 0x000001F2 = 0x00000000:0x7B000006 (IA32_SMRR_PHYSBASE) |
| 195 | MSR 0x000001F3 = 0x00000000:0xFF800800 (IA32_SMRR_PHYSMASK) |
| 196 | MSR 0x00000200 = 0x00000000:0xFF800005 (IA32_MTRR_PHYSBASE0) |
| 197 | MSR 0x00000201 = 0x0000000F:0xFF800800 (IA32_MTRR_PHYSMASK0) |
| 198 | MSR 0x00000202 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE1) |
| 199 | MSR 0x00000203 = 0x0000000F:0x80000800 (IA32_MTRR_PHYSMASK1) |
| 200 | MSR 0x00000204 = 0x00000000:0x7B000000 (IA32_MTRR_PHYSBASE2) |
| 201 | MSR 0x00000205 = 0x0000000F:0xFF000800 (IA32_MTRR_PHYSMASK2) |
| 202 | MSR 0x00000206 = 0x00000000:0x7C000000 (IA32_MTRR_PHYSBASE3) |
| 203 | MSR 0x00000207 = 0x0000000F:0xFC000800 (IA32_MTRR_PHYSMASK3) |
| 204 | MSR 0x00000208 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE4) |
| 205 | MSR 0x00000209 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK4) |
| 206 | MSR 0x0000020A = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE5) |
| 207 | MSR 0x0000020B = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK5) |
| 208 | MSR 0x0000020C = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE6) |
| 209 | MSR 0x0000020D = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK6) |
| 210 | MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7) |
| 211 | MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7) |
| 212 | MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000) |
| 213 | MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000) |
| 214 | MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000) |
| 215 | MSR 0x00000268 = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_C0000) |
| 216 | MSR 0x00000269 = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_C8000) |
| 217 | MSR 0x0000026A = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_D0000) |
| 218 | MSR 0x0000026B = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_D8000) |
| 219 | MSR 0x0000026C = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_E0000) |
| 220 | MSR 0x0000026D = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_E8000) |
| 221 | MSR 0x0000026E = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_F0000) |
| 222 | MSR 0x0000026F = 0x06060606:0x06060606 (IA32_MTRR_FIX4K_F8000) |
| 223 | MSR 0x00000277 = 0x04070106:0x00070106 (IA32_PAT) |
| 224 | MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE) |
| 225 | MSR 0x00000309 = 0x00000000:0x00000000 (IA32_FIXED_CTR0) |
| 226 | MSR 0x0000030A = 0x000000FE:0x8441ED44 (IA32_FIXED_CTR1) |
| 227 | MSR 0x0000030B = 0x00000000:0x00000000 (IA32_FIXED_CTR2) |
| 228 | MSR 0x00000345 = 0x00000000:0x000032C1 (IA32_PERF_CAPABILITIES) |
| 229 | MSR 0x0000038D = 0x00000000:0x000000B0 (IA32_FIXED_CTR_CTRL) |
| 230 | MSR 0x0000038E = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_STATUS) |
| 231 | MSR 0x0000038F = 0x00000007:0x00000003 (IA32_PERF_GLOBAL_CTRL) |
| 232 | MSR 0x00000390 = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_OVF_CTRL) |
| 233 | MSR 0x000003F1 = 0x00000000:0x00000000 (MSR_PEBS_ENABLE) |
| 234 | MSR 0x000003FD = 0x0000004F:0x8E7EFC20 (MSR_CORE_C6_RESIDENCY) |
| 235 | MSR 0x0000040C = 0x00000000:0x00000003 (IA32_MC3_CTL) |
| 236 | MSR 0x0000040D = 0x00000000:0x00000000 (IA32_MC3_STATUS) |
| 237 | MSR 0x0000040E = 0x00000000:0x00000000 (IA32_MC3_ADDR) |
| 238 | MSR 0x00000410 = 0x00000000:0x00000001 (IA32_MC4_CTL) |
| 239 | MSR 0x00000411 = 0x00000000:0x00000000 (IA32_MC4_STATUS) |
| 240 | MSR 0x00000412 = 0x00000000:0x00000000 (IA32_MC4_ADDR) |
| 241 | MSR 0x00000480 = 0x00DA0400:0x00000002 (IA32_VMX_BASIC) |
| 242 | MSR 0x00000481 = 0x0000007F:0x00000016 (IA32_VMX_PINBASED_CTLS) |
| 243 | MSR 0x00000482 = 0xFFF9FFFE:0x0401E172 (IA32_VMX_PROCBASED_CTLS) |
| 244 | MSR 0x00000483 = 0x007FFFFF:0x00036DFF (IA32_VMX_EXIT_CTLS) |
| 245 | MSR 0x00000484 = 0x0000FFFF:0x000011FF (IA32_VMX_ENTRY_CTLS) |
| 246 | MSR 0x00000485 = 0x00000000:0x000481E6 (IA32_VMX_MISC) |
| 247 | MSR 0x00000486 = 0x00000000:0x80000021 (IA32_VMX_CR0_FIXED0) |
| 248 | MSR 0x00000487 = 0x00000000:0xFFFFFFFF (IA32_VMX_CR0_FIXED1) |
| 249 | MSR 0x00000488 = 0x00000000:0x00002000 (IA32_VMX_CR4_FIXED0) |
| 250 | MSR 0x00000489 = 0x00000000:0x001027FF (IA32_VMX_CR4_FIXED1) |
| 251 | MSR 0x0000048A = 0x00000000:0x0000002E (IA32_VMX_VMCS_ENUM) |
| 252 | MSR 0x0000048B = 0x000028EF:0x00000000 (IA32_VMX_PROCBASED_CTLS2) |
| 253 | MSR 0x0000048C = 0x00000F01:0x06114141 (IA32_VMX_EPT_VPID_ENUM) |
| 254 | MSR 0x0000048D = 0x0000007F:0x00000016 (IA32_VMX_TRUE_PINBASED_CTLS) |
| 255 | MSR 0x0000048E = 0xFFF9FFFE:0x04006172 (IA32_VMX_TRUE_PROCBASED_CTLS) |
| 256 | MSR 0x0000048F = 0x007FFFFF:0x00036DFB (IA32_VMX_TRUE_EXIT_CTLS) |
| 257 | MSR 0x00000490 = 0x0000FFFF:0x000011FB (IA32_VMX_TRUE_ENTRY_CTLS) |
| 258 | MSR 0x00000491 = 0x00000000:0x00000001 (IA32_VMX_FMFUNC) |
| 259 | MSR 0x000004C1 = 0x00000000:0x00000000 (IA32_A_PMC0) |
| 260 | MSR 0x000004C2 = 0x00000000:0x00000000 (IA32_A_PMC1) |
| 261 | MSR 0x00000600 = 0xFFFF8800:0x783D2980 (IA32_DS_AREA) |
| 262 | MSR 0x00000660 = 0x00000006:0x1459A394 (MSR_CORE_C1_RESIDENCY) |
| 263 | MSR 0x000006E0 = 0x00000065:0x725FDD87 (IA32_TSC_DEADLINE) |
| 264 | |
| 265 | |